RPCS3/llvm-mirror
1
0
Fork 0
mirror of https://github.com/RPCS3/llvm-mirror.git synced 2024-11-25 20:23:11 +01:00
Code Issues Projects Releases Wiki Activity

[AArch64] Audit on rL333634 to fix FP16 Disasm BitPatterns

Browse Source 
llvm-svn: 333879
This commit is contained in:
Luke Geeson 2018-06-04 09:41:32 +00:00
parent ae2d9690a8
commit 053f862513
2 changed files with 2 additions and 2 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

3
lib/Target/AArch64/AArch64InstrFormats.td
View File

@ -7928,9 +7928,10 @@ multiclass SIMDFPScalarRShift<bit U, bits<5> opc, string asm> {
let Inst{19-16} = imm{3-0};
let Inst{23-22} = 0b11;
}
def SHr : BaseSIMDScalarShift<U, opc, {?,?,?,?,?,?,?},
def SHr : BaseSIMDScalarShift<U, opc, {0,0,1,?,?,?,?},
FPR32, FPR16, vecshiftR32, asm, []> {
let Inst{19-16} = imm{3-0};
let Inst{22-21} = 0b01;
}
def HDr : BaseSIMDScalarShift<U, opc, {?,?,?,?,?,?,?},
FPR16, FPR64, vecshiftR32, asm, []> {

1
lib/Target/AArch64/AArch64InstrInfo.td
View File

@ -4984,7 +4984,6 @@ def : Pat<(v1f64 (int_aarch64_neon_vcvtfxu2fp (v1i64 FPR64:$Rn),
def : Pat<(int_aarch64_neon_vcvtfxs2fp FPR32:$Rn, vecshiftR32:$imm),
(SCVTFs FPR32:$Rn, vecshiftR32:$imm)>;
defm SHL : SIMDScalarLShiftD< 0, 0b01010, "shl", AArch64vshl>;
defm SLI : SIMDScalarLShiftDTied<1, 0b01010, "sli">;
defm SQRSHRN : SIMDScalarRShiftBHS< 0, 0b10011, "sqrshrn",