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[InstCombine] Add vector urem tests
Demonstrate missed opportunity for urem -> and combine for powerof2 or zero non-uniform constant dividers llvm-svn: 288510
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test/Transforms/InstCombine/vector-urem.ll
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29
test/Transforms/InstCombine/vector-urem.ll
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; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
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; RUN: opt < %s -instcombine -S | FileCheck %s
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define <4 x i32> @test_v4i32_splatconst_pow2(<4 x i32> %a0) {
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; CHECK-LABEL: @test_v4i32_splatconst_pow2(
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; CHECK-NEXT: [[TMP1:%.*]] = and <4 x i32> %a0, <i32 1, i32 1, i32 1, i32 1>
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; CHECK-NEXT: ret <4 x i32> [[TMP1]]
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;
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%1 = urem <4 x i32> %a0, <i32 2, i32 2, i32 2, i32 2>
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ret <4 x i32> %1
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}
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define <4 x i32> @test_v4i32_const_pow2(<4 x i32> %a0) {
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; CHECK-LABEL: @test_v4i32_const_pow2(
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; CHECK-NEXT: [[TMP1:%.*]] = urem <4 x i32> %a0, <i32 1, i32 2, i32 4, i32 8>
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; CHECK-NEXT: ret <4 x i32> [[TMP1]]
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;
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%1 = urem <4 x i32> %a0, <i32 1, i32 2, i32 4, i32 8>
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ret <4 x i32> %1
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}
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define <4 x i32> @test_v4i32_const_pow2_or_zero(<4 x i32> %a0) {
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; CHECK-LABEL: @test_v4i32_const_pow2_or_zero(
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; CHECK-NEXT: [[TMP1:%.*]] = urem <4 x i32> %a0, <i32 1, i32 2, i32 0, i32 8>
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; CHECK-NEXT: ret <4 x i32> [[TMP1]]
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;
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%1 = urem <4 x i32> %a0, <i32 1, i32 2, i32 0, i32 8>
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ret <4 x i32> %1
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}
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