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VHADD differs from VHSUB at least on A9 - the former reads both operands in the second cycle, while the latter reads second operand in first cycle. Introduce new itin classes to catch this behavior. Whether this is true for A8 as well is WIP.
llvm-svn: 100652
This commit is contained in:
Anton Korobeynikov
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e8688b87a4
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058984f2a8
@ -2257,17 +2257,17 @@ defm VSUBWs : N3VWInt_QHS<0,1,0b0011,0, "vsubw", "s", int_arm_neon_vsubws, 0>;
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defm VSUBWu : N3VWInt_QHS<1,1,0b0011,0, "vsubw", "u", int_arm_neon_vsubwu, 0>;
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// VHSUB : Vector Halving Subtract
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defm VHSUBs : N3VInt_QHS<0, 0, 0b0010, 0, N3RegFrm,
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IIC_VBINi4D, IIC_VBINi4D, IIC_VBINi4Q, IIC_VBINi4Q,
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IIC_VSUBi4D, IIC_VSUBi4D, IIC_VSUBi4Q, IIC_VSUBi4Q,
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"vhsub", "s", int_arm_neon_vhsubs, 0>;
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defm VHSUBu : N3VInt_QHS<1, 0, 0b0010, 0, N3RegFrm,
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IIC_VBINi4D, IIC_VBINi4D, IIC_VBINi4Q, IIC_VBINi4Q,
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IIC_VSUBi4D, IIC_VSUBi4D, IIC_VSUBi4Q, IIC_VSUBi4Q,
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"vhsub", "u", int_arm_neon_vhsubu, 0>;
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// VQSUB : Vector Saturing Subtract
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defm VQSUBs : N3VInt_QHSD<0, 0, 0b0010, 1, N3RegFrm,
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IIC_VBINi4D, IIC_VBINi4D, IIC_VBINi4Q, IIC_VBINi4Q,
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IIC_VSUBi4D, IIC_VSUBi4D, IIC_VSUBi4Q, IIC_VSUBi4Q,
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"vqsub", "s", int_arm_neon_vqsubs, 0>;
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defm VQSUBu : N3VInt_QHSD<1, 0, 0b0010, 1, N3RegFrm,
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IIC_VBINi4D, IIC_VBINi4D, IIC_VBINi4Q, IIC_VBINi4Q,
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IIC_VSUBi4D, IIC_VSUBi4D, IIC_VSUBi4Q, IIC_VSUBi4Q,
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"vqsub", "u", int_arm_neon_vqsubu, 0>;
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// VSUBHN : Vector Subtract and Narrow Returning High Half (D = Q - Q)
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defm VSUBHN : N3VNInt_HSD<0,1,0b0110,0, "vsubhn", "i",
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@ -2279,8 +2279,8 @@ defm VRSUBHN : N3VNInt_HSD<1,1,0b0110,0, "vrsubhn", "i",
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// Vector Comparisons.
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// VCEQ : Vector Compare Equal
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defm VCEQ : N3V_QHS<1, 0, 0b1000, 1, IIC_VBINi4D, IIC_VBINi4D, IIC_VBINi4Q,
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IIC_VBINi4Q, "vceq", "i", NEONvceq, 1>;
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defm VCEQ : N3V_QHS<1, 0, 0b1000, 1, IIC_VSUBi4D, IIC_VSUBi4D, IIC_VSUBi4Q,
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IIC_VSUBi4Q, "vceq", "i", NEONvceq, 1>;
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def VCEQfd : N3VD<0,0,0b00,0b1110,0, IIC_VBIND, "vceq", "f32", v2i32, v2f32,
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NEONvceq, 1>;
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def VCEQfq : N3VQ<0,0,0b00,0b1110,0, IIC_VBINQ, "vceq", "f32", v4i32, v4f32,
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@ -2290,10 +2290,10 @@ defm VCEQz : N2V_QHS_cmp<0b11, 0b11, 0b01, 0b00010, 0, "vceq", "i",
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"$dst, $src, #0">;
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// VCGE : Vector Compare Greater Than or Equal
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defm VCGEs : N3V_QHS<0, 0, 0b0011, 1, IIC_VBINi4D, IIC_VBINi4D, IIC_VBINi4Q,
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IIC_VBINi4Q, "vcge", "s", NEONvcge, 0>;
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defm VCGEu : N3V_QHS<1, 0, 0b0011, 1, IIC_VBINi4D, IIC_VBINi4D, IIC_VBINi4Q,
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IIC_VBINi4Q, "vcge", "u", NEONvcgeu, 0>;
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defm VCGEs : N3V_QHS<0, 0, 0b0011, 1, IIC_VSUBi4D, IIC_VSUBi4D, IIC_VSUBi4Q,
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IIC_VSUBi4Q, "vcge", "s", NEONvcge, 0>;
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defm VCGEu : N3V_QHS<1, 0, 0b0011, 1, IIC_VSUBi4D, IIC_VSUBi4D, IIC_VSUBi4Q,
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IIC_VSUBi4Q, "vcge", "u", NEONvcgeu, 0>;
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def VCGEfd : N3VD<1,0,0b00,0b1110,0, IIC_VBIND, "vcge", "f32", v2i32, v2f32,
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NEONvcge, 0>;
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def VCGEfq : N3VQ<1,0,0b00,0b1110,0, IIC_VBINQ, "vcge", "f32", v4i32, v4f32,
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@ -2306,10 +2306,10 @@ defm VCLEz : N2V_QHS_cmp<0b11, 0b11, 0b01, 0b00011, 0, "vcle", "s",
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"$dst, $src, #0">;
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// VCGT : Vector Compare Greater Than
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defm VCGTs : N3V_QHS<0, 0, 0b0011, 0, IIC_VBINi4D, IIC_VBINi4D, IIC_VBINi4Q,
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IIC_VBINi4Q, "vcgt", "s", NEONvcgt, 0>;
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defm VCGTu : N3V_QHS<1, 0, 0b0011, 0, IIC_VBINi4D, IIC_VBINi4D, IIC_VBINi4Q,
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IIC_VBINi4Q, "vcgt", "u", NEONvcgtu, 0>;
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defm VCGTs : N3V_QHS<0, 0, 0b0011, 0, IIC_VSUBi4D, IIC_VSUBi4D, IIC_VSUBi4Q,
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IIC_VSUBi4Q, "vcgt", "s", NEONvcgt, 0>;
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defm VCGTu : N3V_QHS<1, 0, 0b0011, 0, IIC_VSUBi4D, IIC_VSUBi4D, IIC_VSUBi4Q,
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IIC_VSUBi4Q, "vcgt", "u", NEONvcgtu, 0>;
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def VCGTfd : N3VD<1,0,0b10,0b1110,0, IIC_VBIND, "vcgt", "f32", v2i32, v2f32,
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NEONvcgt, 0>;
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def VCGTfq : N3VQ<1,0,0b10,0b1110,0, IIC_VBINQ, "vcgt", "f32", v4i32, v4f32,
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@ -2446,11 +2446,19 @@ def VBITq : N3VX<1, 0, 0b10, 0b0001, 1, 1,
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// Vector Absolute Differences.
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// VABD : Vector Absolute Difference
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<<<<<<< HEAD
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defm VABDs : N3VInt_QHS<0, 0, 0b0111, 0, N3RegFrm,
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IIC_VBINi4D, IIC_VBINi4D, IIC_VBINi4Q, IIC_VBINi4Q,
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"vabd", "s", int_arm_neon_vabds, 0>;
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defm VABDu : N3VInt_QHS<1, 0, 0b0111, 0, N3RegFrm,
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IIC_VBINi4D, IIC_VBINi4D, IIC_VBINi4Q, IIC_VBINi4Q,
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=======
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defm VABDs : N3VInt_QHS<0, 0, 0b0111, 0, IIC_VSUBi4D, IIC_VSUBi4D,
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IIC_VSUBi4Q, IIC_VSUBi4Q,
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"vabd", "s", int_arm_neon_vabds, 0>;
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defm VABDu : N3VInt_QHS<1, 0, 0b0111, 0, IIC_VSUBi4D, IIC_VSUBi4D,
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IIC_VSUBi4Q, IIC_VSUBi4Q,
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>>>>>>> VHADD differs from VHSUB at least on A9 - the former reads both operands in the
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"vabd", "u", int_arm_neon_vabdu, 0>;
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def VABDfd : N3VDInt<1, 0, 0b10, 0b1101, 0, N3RegFrm, IIC_VBIND,
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"vabd", "f32", v2f32, v2f32, int_arm_neon_vabds, 0>;
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@ -2458,9 +2466,9 @@ def VABDfq : N3VQInt<1, 0, 0b10, 0b1101, 0, N3RegFrm, IIC_VBINQ,
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"vabd", "f32", v4f32, v4f32, int_arm_neon_vabds, 0>;
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// VABDL : Vector Absolute Difference Long (Q = | D - D |)
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defm VABDLs : N3VLInt_QHS<0,1,0b0111,0, IIC_VBINi4Q,
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defm VABDLs : N3VLInt_QHS<0,1,0b0111,0, IIC_VSUBi4Q,
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"vabdl", "s", int_arm_neon_vabdls, 0>;
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defm VABDLu : N3VLInt_QHS<1,1,0b0111,0, IIC_VBINi4Q,
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defm VABDLu : N3VLInt_QHS<1,1,0b0111,0, IIC_VSUBi4Q,
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"vabdl", "u", int_arm_neon_vabdlu, 0>;
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// VABA : Vector Absolute Difference and Accumulate
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@ -2474,6 +2482,7 @@ defm VABALu : N3VLInt3_QHS<1,1,0b0101,0, "vabal", "u", int_arm_neon_vabalu>;
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// Vector Maximum and Minimum.
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// VMAX : Vector Maximum
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<<<<<<< HEAD
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defm VMAXs : N3VInt_QHS<0, 0, 0b0110, 0, N3RegFrm,
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IIC_VBINi4D, IIC_VBINi4D, IIC_VBINi4Q, IIC_VBINi4Q,
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"vmax", "s", int_arm_neon_vmaxs, 1>;
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@ -2496,6 +2505,26 @@ def VMINfd : N3VDInt<0, 0, 0b10, 0b1111, 0, N3RegFrm, IIC_VBIND, "vmin",
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"f32", v2f32, v2f32, int_arm_neon_vmins, 1>;
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def VMINfq : N3VQInt<0, 0, 0b10, 0b1111, 0, N3RegFrm, IIC_VBINQ, "vmin",
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"f32", v4f32, v4f32, int_arm_neon_vmins, 1>;
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=======
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defm VMAXs : N3VInt_QHS<0,0,0b0110,0, IIC_VSUBi4D, IIC_VSUBi4D, IIC_VSUBi4Q,
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IIC_VSUBi4Q, "vmax", "s", int_arm_neon_vmaxs, 1>;
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defm VMAXu : N3VInt_QHS<1,0,0b0110,0, IIC_VSUBi4D, IIC_VSUBi4D, IIC_VSUBi4Q,
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IIC_VSUBi4Q, "vmax", "u", int_arm_neon_vmaxu, 1>;
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def VMAXfd : N3VDInt<0, 0, 0b00, 0b1111, 0, IIC_VBIND, "vmax", "f32",
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v2f32, v2f32, int_arm_neon_vmaxs, 1>;
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def VMAXfq : N3VQInt<0, 0, 0b00, 0b1111, 0, IIC_VBINQ, "vmax", "f32",
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v4f32, v4f32, int_arm_neon_vmaxs, 1>;
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// VMIN : Vector Minimum
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defm VMINs : N3VInt_QHS<0,0,0b0110,1, IIC_VSUBi4D, IIC_VSUBi4D, IIC_VSUBi4Q,
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IIC_VSUBi4Q, "vmin", "s", int_arm_neon_vmins, 1>;
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defm VMINu : N3VInt_QHS<1,0,0b0110,1, IIC_VSUBi4D, IIC_VSUBi4D, IIC_VSUBi4Q,
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IIC_VSUBi4Q, "vmin", "u", int_arm_neon_vminu, 1>;
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def VMINfd : N3VDInt<0, 0, 0b10, 0b1111, 0, IIC_VBIND, "vmin", "f32",
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v2f32, v2f32, int_arm_neon_vmins, 1>;
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def VMINfq : N3VQInt<0, 0, 0b10, 0b1111, 0, IIC_VBINQ, "vmin", "f32",
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v4f32, v4f32, int_arm_neon_vmins, 1>;
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>>>>>>> VHADD differs from VHSUB at least on A9 - the former reads both operands in the
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// Vector Pairwise Operations.
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@ -133,6 +133,8 @@ def IIC_VSUBiD : InstrItinClass;
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def IIC_VSUBiQ : InstrItinClass;
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def IIC_VBINi4D : InstrItinClass;
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def IIC_VBINi4Q : InstrItinClass;
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def IIC_VSUBi4D : InstrItinClass;
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def IIC_VSUBi4Q : InstrItinClass;
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def IIC_VSHLiD : InstrItinClass;
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def IIC_VSHLiQ : InstrItinClass;
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def IIC_VSHLi4D : InstrItinClass;
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@ -480,6 +480,7 @@ def CortexA8Itineraries : ProcessorItineraries<[
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// Quad-register Integer Binary (4 cycle)
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InstrItinData<IIC_VBINi4Q, [InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
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InstrStage<1, [FU_NPipe]>], [4, 2, 1]>,
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//
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// Double-register Integer Subtract
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InstrItinData<IIC_VSUBiD, [InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
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@ -489,6 +490,14 @@ def CortexA8Itineraries : ProcessorItineraries<[
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InstrItinData<IIC_VSUBiQ, [InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
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InstrStage<1, [FU_NPipe]>], [3, 2, 1]>,
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//
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// Double-register Integer Subtract
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InstrItinData<IIC_VSUBi4D, [InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
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InstrStage<1, [FU_NPipe]>], [4, 2, 1]>,
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//
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// Quad-register Integer Subtract
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InstrItinData<IIC_VSUBi4Q, [InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
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InstrStage<1, [FU_NPipe]>], [4, 2, 1]>,
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//
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// Double-register Integer Shift
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InstrItinData<IIC_VSHLiD, [InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
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InstrStage<1, [FU_NPipe]>], [3, 1, 1]>,
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@ -832,7 +841,21 @@ def CortexA9Itineraries : ProcessorItineraries<[
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// Extra 3 latency cycle since wbck is 6 cycles
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InstrStage2<7, [FU_DRegsVFP], 0, Reserved>,
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InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
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InstrStage<1, [FU_NPipe]>], [4, 2, 2]>
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InstrStage<1, [FU_NPipe]>], [4, 2, 2]>,
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//
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// Double-register Integer Subtract (4 cycle)
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InstrItinData<IIC_VSUBiD, [InstrStage2<1, [FU_DRegsN], 0, Required>,
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// Extra 3 latency cycle since wbck is 6 cycles
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InstrStage2<7, [FU_DRegsVFP], 0, Reserved>,
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InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
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InstrStage<1, [FU_NPipe]>], [4, 2, 1]>,
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//
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// Quad-register Integer Subtract (4 cycle)
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InstrItinData<IIC_VSUBiQ, [InstrStage2<1, [FU_DRegsN], 0, Required>,
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// Extra 3 latency cycle since wbck is 6 cycles
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InstrStage2<7, [FU_DRegsVFP], 0, Reserved>,
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InstrStage<1, [FU_Pipe0, FU_Pipe1]>,
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InstrStage<1, [FU_NPipe]>], [4, 2, 1]>
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]>;
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