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[WebAssembly] Enable IndirectBrExpandPass

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Wasm doesn't have a direct way to lower indirectbr, so hook up the
IndirectBrExpandPass to lower indirectbr into a switch.

Fixes PR42498

Reviewers: aheejin

Differential Revision: https://reviews.llvm.org/D64161

llvm-svn: 365096
This commit is contained in:
Derek Schuff 2019-07-03 23:54:06 +00:00
parent 26e5d021eb
commit 05a21c822b
4 changed files with 73 additions and 9 deletions
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1
lib/Target/WebAssembly/WebAssemblySubtarget.h
View File

@ -86,6 +86,7 @@ public:
}
const Triple &getTargetTriple() const { return TargetTriple; }
bool enableAtomicExpand() const override;
bool enableIndirectBrExpand() const override { return true; }
bool enableMachineScheduler() const override;
bool useAA() const override;

3
lib/Target/WebAssembly/WebAssemblyTargetMachine.cpp
View File

@ -368,6 +368,9 @@ void WebAssemblyPassConfig::addIRPasses() {
addPass(createWebAssemblyLowerEmscriptenEHSjLj(EnableEmException,
EnableEmSjLj));
// Expand indirectbr instructions to switches.
addPass(createIndirectBrExpandPass());
TargetPassConfig::addIRPasses();
}

10
lib/Target/WebAssembly/known_gcc_test_failures.txt
View File

@ -7,20 +7,12 @@
# <name> <attributes> # comment
# Computed gotos are not supported (Cannot select BlockAddress/BRIND)
20071220-1.c
20071220-1.c O2
20071220-2.c
20040302-1.c
20041214-1.c O0
20071210-1.c
920501-4.c
920501-5.c
comp-goto-1.c
980526-1.c
990208-1.c
label13.C O0
label13a.C O0
label3.C
pr42462.C O0
# WebAssembly hasn't implemented (will never?) __builtin_return_address
20010122-1.c

68
test/CodeGen/WebAssembly/indirectbr.ll Normal file
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@ -0,0 +1,68 @@
; RUN: llc < %s -asm-verbose=false -disable-wasm-fallthrough-return-opt -wasm-disable-explicit-locals -wasm-keep-registers | FileCheck %s
; This tests that indirectbr instructions are lowered to switches. Currently we
; just re-use the IndirectBrExpand Pass; it has its own IR-level test.
; So this test just ensures that the pass gets run and we can lower indirectbr
target triple = "wasm32"
@test1.targets = constant [4 x i8*] [i8* blockaddress(@test1, %bb0),
i8* blockaddress(@test1, %bb1),
i8* blockaddress(@test1, %bb2),
i8* blockaddress(@test1, %bb3)]
; Just check the barest skeleton of the structure
; CHECK-LABEL: test1:
; CHECK: i32.load
; CHECK: i32.load $[[DEST:.+]]=
; CHECK: loop
; CHECK: block
; CHECK: block
; CHECK: end_block
; CHECK: block
; CHECK: block
; CHECK: br_table $[[DEST]]
; CHECK: end_block
; CHECK: end_block
; CHECK: i32.load $[[DEST]]=
; CHECK: end_loop
; CHECK: test1.targets:
; CHECK-NEXT: .int32
; CHECK-NEXT: .int32
; CHECK-NEXT: .int32
; CHECK-NEXT: .int32
define void @test1(i32* readonly %p, i32* %sink) #0 {
entry:
%i0 = load i32, i32* %p
%target.i0 = getelementptr [4 x i8*], [4 x i8*]* @test1.targets, i32 0, i32 %i0
%target0 = load i8*, i8** %target.i0
; Only a subset of blocks are viable successors here.
indirectbr i8* %target0, [label %bb0, label %bb1]
bb0:
store volatile i32 0, i32* %sink
br label %latch
bb1:
store volatile i32 1, i32* %sink
br label %latch
bb2:
store volatile i32 2, i32* %sink
br label %latch
bb3:
store volatile i32 3, i32* %sink
br label %latch
latch:
%i.next = load i32, i32* %p
%target.i.next = getelementptr [4 x i8*], [4 x i8*]* @test1.targets, i32 0, i32 %i.next
%target.next = load i8*, i8** %target.i.next
; A different subset of blocks are viable successors here.
indirectbr i8* %target.next, [label %bb1, label %bb2]
}