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Add 3DNow! intrinsics.
llvm-svn: 129551
This commit is contained in:
Michael J. Spencer
parent
197d67a987
commit
05b07faeaf
@ -17,6 +17,83 @@ let TargetPrefix = "x86" in { // All intrinsics start with "llvm.x86.".
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def int_x86_int : Intrinsic<[], [llvm_i8_ty]>;
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}
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//===----------------------------------------------------------------------===//
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// 3DNow!
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let TargetPrefix = "x86" in {
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def int_x86_3dnow_pavgusb : GCCBuiltin<"__builtin_ia32_pavgusb">,
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Intrinsic<[llvm_x86mmx_ty], [llvm_x86mmx_ty, llvm_x86mmx_ty],
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[IntrNoMem]>;
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def int_x86_3dnow_pf2id : GCCBuiltin<"__builtin_ia32_pf2id">,
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Intrinsic<[llvm_x86mmx_ty], [llvm_x86mmx_ty], [IntrNoMem]>;
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def int_x86_3dnow_pfacc : GCCBuiltin<"__builtin_ia32_pfacc">,
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Intrinsic<[llvm_x86mmx_ty], [llvm_x86mmx_ty, llvm_x86mmx_ty],
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[IntrNoMem]>;
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def int_x86_3dnow_pfadd : GCCBuiltin<"__builtin_ia32_pfadd">,
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Intrinsic<[llvm_x86mmx_ty], [llvm_x86mmx_ty, llvm_x86mmx_ty],
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[IntrNoMem]>;
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def int_x86_3dnow_pfcmpeq : GCCBuiltin<"__builtin_ia32_pfcmpeq">,
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Intrinsic<[llvm_x86mmx_ty], [llvm_x86mmx_ty, llvm_x86mmx_ty],
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[IntrNoMem]>;
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def int_x86_3dnow_pfcmpge : GCCBuiltin<"__builtin_ia32_pfcmpge">,
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Intrinsic<[llvm_x86mmx_ty], [llvm_x86mmx_ty, llvm_x86mmx_ty],
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[IntrNoMem]>;
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def int_x86_3dnow_pfcmpgt : GCCBuiltin<"__builtin_ia32_pfcmpgt">,
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Intrinsic<[llvm_x86mmx_ty], [llvm_x86mmx_ty, llvm_x86mmx_ty],
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[IntrNoMem]>;
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def int_x86_3dnow_pfmax : GCCBuiltin<"__builtin_ia32_pfmax">,
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Intrinsic<[llvm_x86mmx_ty], [llvm_x86mmx_ty, llvm_x86mmx_ty],
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[IntrNoMem]>;
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def int_x86_3dnow_pfmin : GCCBuiltin<"__builtin_ia32_pfmin">,
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Intrinsic<[llvm_x86mmx_ty], [llvm_x86mmx_ty, llvm_x86mmx_ty],
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[IntrNoMem]>;
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def int_x86_3dnow_pfmul : GCCBuiltin<"__builtin_ia32_pfmul">,
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Intrinsic<[llvm_x86mmx_ty], [llvm_x86mmx_ty, llvm_x86mmx_ty],
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[IntrNoMem]>;
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def int_x86_3dnow_pfrcp : GCCBuiltin<"__builtin_ia32_pfrcp">,
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Intrinsic<[llvm_x86mmx_ty], [llvm_x86mmx_ty], [IntrNoMem]>;
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def int_x86_3dnow_pfrcpit1 : GCCBuiltin<"__builtin_ia32_pfrcpit1">,
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Intrinsic<[llvm_x86mmx_ty], [llvm_x86mmx_ty, llvm_x86mmx_ty],
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[IntrNoMem]>;
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def int_x86_3dnow_pfrcpit2 : GCCBuiltin<"__builtin_ia32_pfrcpit2">,
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Intrinsic<[llvm_x86mmx_ty], [llvm_x86mmx_ty, llvm_x86mmx_ty],
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[IntrNoMem]>;
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def int_x86_3dnow_pfrsqrt : GCCBuiltin<"__builtin_ia32_pfrsqrt">,
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Intrinsic<[llvm_x86mmx_ty], [llvm_x86mmx_ty], [IntrNoMem]>;
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def int_x86_3dnow_pfrsqit1 : GCCBuiltin<"__builtin_ia32_pfrsqit1">,
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Intrinsic<[llvm_x86mmx_ty], [llvm_x86mmx_ty, llvm_x86mmx_ty],
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[IntrNoMem]>;
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def int_x86_3dnow_pfsub : GCCBuiltin<"__builtin_ia32_pfsub">,
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Intrinsic<[llvm_x86mmx_ty], [llvm_x86mmx_ty, llvm_x86mmx_ty],
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[IntrNoMem]>;
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def int_x86_3dnow_pfsubr : GCCBuiltin<"__builtin_ia32_pfsubr">,
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Intrinsic<[llvm_x86mmx_ty], [llvm_x86mmx_ty, llvm_x86mmx_ty],
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[IntrNoMem]>;
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def int_x86_3dnow_pi2fd : GCCBuiltin<"__builtin_ia32_pi2fd">,
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Intrinsic<[llvm_x86mmx_ty], [llvm_x86mmx_ty], [IntrNoMem]>;
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def int_x86_3dnow_pmulhrw : GCCBuiltin<"__builtin_ia32_pmulhrw">,
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Intrinsic<[llvm_x86mmx_ty], [llvm_x86mmx_ty, llvm_x86mmx_ty],
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[IntrNoMem]>;
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}
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//===----------------------------------------------------------------------===//
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// 3DNow! extensions
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let TargetPrefix = "x86" in {
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def int_x86_3dnowa_pf2iw : GCCBuiltin<"__builtin_ia32_pf2iw">,
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Intrinsic<[llvm_x86mmx_ty], [llvm_x86mmx_ty], [IntrNoMem]>;
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def int_x86_3dnowa_pfnacc : GCCBuiltin<"__builtin_ia32_pfnacc">,
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Intrinsic<[llvm_x86mmx_ty], [llvm_x86mmx_ty, llvm_x86mmx_ty],
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[IntrNoMem]>;
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def int_x86_3dnowa_pfpnacc : GCCBuiltin<"__builtin_ia32_pfpnacc">,
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Intrinsic<[llvm_x86mmx_ty], [llvm_x86mmx_ty, llvm_x86mmx_ty],
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[IntrNoMem]>;
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def int_x86_3dnowa_pi2fw : GCCBuiltin<"__builtin_ia32_pi2fw">,
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Intrinsic<[llvm_x86mmx_ty], [llvm_x86mmx_ty], [IntrNoMem]>;
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def int_x86_3dnowa_pswapd :
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Intrinsic<[llvm_x86mmx_ty], [llvm_x86mmx_ty], [IntrNoMem]>;
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}
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//===----------------------------------------------------------------------===//
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// SSE1
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@ -50,7 +50,8 @@ def FeatureSSE42 : SubtargetFeature<"sse42", "X86SSELevel", "SSE42",
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"Enable SSE 4.2 instructions",
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[FeatureSSE41, FeaturePOPCNT]>;
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def Feature3DNow : SubtargetFeature<"3dnow", "X863DNowLevel", "ThreeDNow",
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"Enable 3DNow! instructions">;
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"Enable 3DNow! instructions",
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[FeatureMMX]>;
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def Feature3DNowA : SubtargetFeature<"3dnowa", "X863DNowLevel", "ThreeDNowA",
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"Enable 3DNow! Athlon instructions",
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[Feature3DNow]>;
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@ -125,10 +126,10 @@ def : Proc<"sandybridge", [FeatureSSE42, Feature64Bit,
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FeatureAES, FeatureCLMUL]>;
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def : Proc<"k6", [FeatureMMX]>;
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def : Proc<"k6-2", [FeatureMMX, Feature3DNow]>;
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def : Proc<"k6-3", [FeatureMMX, Feature3DNow]>;
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def : Proc<"athlon", [FeatureMMX, Feature3DNowA, FeatureSlowBTMem]>;
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def : Proc<"athlon-tbird", [FeatureMMX, Feature3DNowA, FeatureSlowBTMem]>;
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def : Proc<"k6-2", [Feature3DNow]>;
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def : Proc<"k6-3", [Feature3DNow]>;
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def : Proc<"athlon", [Feature3DNowA, FeatureSlowBTMem]>;
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def : Proc<"athlon-tbird", [Feature3DNowA, FeatureSlowBTMem]>;
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def : Proc<"athlon-4", [FeatureSSE1, Feature3DNowA, FeatureSlowBTMem]>;
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def : Proc<"athlon-xp", [FeatureSSE1, Feature3DNowA, FeatureSlowBTMem]>;
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def : Proc<"athlon-mp", [FeatureSSE1, Feature3DNowA, FeatureSlowBTMem]>;
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@ -156,8 +157,8 @@ def : Proc<"shanghai", [Feature3DNowA, Feature64Bit, FeatureSSE4A,
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Feature3DNowA]>;
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def : Proc<"winchip-c6", [FeatureMMX]>;
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def : Proc<"winchip2", [FeatureMMX, Feature3DNow]>;
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def : Proc<"c3", [FeatureMMX, Feature3DNow]>;
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def : Proc<"winchip2", [Feature3DNow]>;
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def : Proc<"c3", [Feature3DNow]>;
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def : Proc<"c3-2", [FeatureSSE1]>;
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//===----------------------------------------------------------------------===//
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@ -12,50 +12,76 @@
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//
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//===----------------------------------------------------------------------===//
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// FIXME: We don't support any intrinsics for these instructions yet.
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class I3DNow<bits<8> o, Format F, dag outs, dag ins, string asm,
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list<dag> pattern>
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: I<o, F, outs, ins, asm, pattern>, TB, Requires<[Has3DNow]> {
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class I3DNow<bits<8> o, Format F, dag outs, dag ins, string asm, list<dag> pat>
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: I<o, F, outs, ins, asm, pat>, TB, Requires<[Has3DNow]> {
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}
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class I3DNow_binop<bits<8> o, Format F, dag ins, string Mnemonic>
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: I<o, F, (outs VR64:$dst), ins,
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!strconcat(Mnemonic, "\t{$src2, $dst|$dst, $src2}"), []>,
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TB, Requires<[Has3DNow]>, Has3DNow0F0FOpcode {
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class I3DNow_binop<bits<8> o, Format F, dag ins, string Mnemonic, list<dag> pat>
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: I3DNow<o, F, (outs VR64:$dst), ins,
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!strconcat(Mnemonic, "\t{$src2, $dst|$dst, $src2}"), pat>,
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Has3DNow0F0FOpcode {
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// FIXME: The disassembler doesn't support Has3DNow0F0FOpcode yet.
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let isAsmParserOnly = 1;
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let Constraints = "$src1 = $dst";
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}
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class I3DNow_conv<bits<8> o, Format F, dag ins, string Mnemonic, list<dag> pat>
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: I3DNow<o, F, (outs VR64:$dst), ins,
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!strconcat(Mnemonic, "\t{$src, $dst|$dst, $src}"), pat>,
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Has3DNow0F0FOpcode {
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// FIXME: The disassembler doesn't support Has3DNow0F0FOpcode yet.
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let isAsmParserOnly = 1;
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}
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let Constraints = "$src1 = $dst" in {
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// MMXI_binop_rm_int - Simple MMX binary operator based on intrinsic.
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// When this is cleaned up, remove the FIXME from X86RecognizableInstr.cpp.
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multiclass I3DNow_binop_rm<bits<8> opc, string Mn> {
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def rr : I3DNow_binop<opc, MRMSrcReg, (ins VR64:$src1, VR64:$src2), Mn>;
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def rm : I3DNow_binop<opc, MRMSrcMem, (ins VR64:$src1, i64mem:$src2), Mn>;
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}
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def rr : I3DNow_binop<opc, MRMSrcReg, (ins VR64:$src1, VR64:$src2), Mn, []>;
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def rm : I3DNow_binop<opc, MRMSrcMem, (ins VR64:$src1, i64mem:$src2), Mn, []>;
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}
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defm PAVGUSB : I3DNow_binop_rm<0xBF, "pavgusb">;
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defm PF2ID : I3DNow_binop_rm<0x1D, "pf2id">;
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defm PFACC : I3DNow_binop_rm<0xAE, "pfacc">;
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defm PFADD : I3DNow_binop_rm<0x9E, "pfadd">;
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defm PFCMPEQ : I3DNow_binop_rm<0xB0, "pfcmpeq">;
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defm PFCMPGE : I3DNow_binop_rm<0x90, "pfcmpge">;
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defm PFCMPGT : I3DNow_binop_rm<0xA0, "pfcmpgt">;
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defm PFMAX : I3DNow_binop_rm<0xA4, "pfmax">;
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defm PFMIN : I3DNow_binop_rm<0x94, "pfmin">;
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defm PFMUL : I3DNow_binop_rm<0xB4, "pfmul">;
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defm PFRCP : I3DNow_binop_rm<0x96, "pfrcp">;
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defm PFRCPIT1 : I3DNow_binop_rm<0xA6, "pfrcpit1">;
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defm PFRCPIT2 : I3DNow_binop_rm<0xB6, "pfrcpit2">;
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defm PFRSQIT1 : I3DNow_binop_rm<0xA7, "pfrsqit1">;
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defm PFRSQRT : I3DNow_binop_rm<0x97, "pfrsqrt">;
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defm PFSUB : I3DNow_binop_rm<0x9A, "pfsub">;
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defm PFSUBR : I3DNow_binop_rm<0xAA, "pfsubr">;
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defm PI2FD : I3DNow_binop_rm<0x0D, "pi2fd">;
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defm PMULHRW : I3DNow_binop_rm<0xB7, "pmulhrw">;
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multiclass I3DNow_binop_rm_int<bits<8> opc, string Mn, string Ver = ""> {
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def rr : I3DNow_binop<opc, MRMSrcReg, (ins VR64:$src1, VR64:$src2), Mn,
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[(set VR64:$dst, (!cast<Intrinsic>(
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!strconcat("int_x86_3dnow", Ver, "_", Mn)) VR64:$src1, VR64:$src2))]>;
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def rm : I3DNow_binop<opc, MRMSrcMem, (ins VR64:$src1, i64mem:$src2), Mn,
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[(set VR64:$dst, (!cast<Intrinsic>(
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!strconcat("int_x86_3dnow", Ver, "_", Mn)) VR64:$src1,
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(bitconvert (load_mmx addr:$src2))))]>;
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}
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multiclass I3DNow_conv_rm<bits<8> opc, string Mn> {
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def rr : I3DNow_conv<opc, MRMSrcReg, (ins VR64:$src1), Mn, []>;
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def rm : I3DNow_conv<opc, MRMSrcMem, (ins i64mem:$src1), Mn, []>;
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}
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multiclass I3DNow_conv_rm_int<bits<8> opc, string Mn, string Ver = ""> {
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def rr : I3DNow_conv<opc, MRMSrcReg, (ins VR64:$src), Mn,
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[(set VR64:$dst, (!cast<Intrinsic>(
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!strconcat("int_x86_3dnow", Ver, "_", Mn)) VR64:$src))]>;
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def rm : I3DNow_conv<opc, MRMSrcMem, (ins i64mem:$src), Mn,
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[(set VR64:$dst, (!cast<Intrinsic>(
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!strconcat("int_x86_3dnow", Ver, "_", Mn))
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(bitconvert (load_mmx addr:$src))))]>;
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}
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defm PAVGUSB : I3DNow_binop_rm_int<0xBF, "pavgusb">;
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defm PF2ID : I3DNow_conv_rm_int<0x1D, "pf2id">;
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defm PFACC : I3DNow_binop_rm_int<0xAE, "pfacc">;
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defm PFADD : I3DNow_binop_rm_int<0x9E, "pfadd">;
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defm PFCMPEQ : I3DNow_binop_rm_int<0xB0, "pfcmpeq">;
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defm PFCMPGE : I3DNow_binop_rm_int<0x90, "pfcmpge">;
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defm PFCMPGT : I3DNow_binop_rm_int<0xA0, "pfcmpgt">;
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defm PFMAX : I3DNow_binop_rm_int<0xA4, "pfmax">;
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defm PFMIN : I3DNow_binop_rm_int<0x94, "pfmin">;
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defm PFMUL : I3DNow_binop_rm_int<0xB4, "pfmul">;
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defm PFRCP : I3DNow_conv_rm_int<0x96, "pfrcp">;
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defm PFRCPIT1 : I3DNow_binop_rm_int<0xA6, "pfrcpit1">;
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defm PFRCPIT2 : I3DNow_binop_rm_int<0xB6, "pfrcpit2">;
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defm PFRSQIT1 : I3DNow_binop_rm_int<0xA7, "pfrsqit1">;
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defm PFRSQRT : I3DNow_conv_rm_int<0x97, "pfrsqrt">;
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defm PFSUB : I3DNow_binop_rm_int<0x9A, "pfsub">;
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defm PFSUBR : I3DNow_binop_rm_int<0xAA, "pfsubr">;
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defm PI2FD : I3DNow_conv_rm_int<0x0D, "pi2fd">;
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defm PMULHRW : I3DNow_binop_rm_int<0xB7, "pmulhrw">;
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def FEMMS : I3DNow<0x0E, RawFrm, (outs), (ins), "femms", [(int_x86_mmx_femms)]>;
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@ -64,14 +90,13 @@ def PREFETCH : I3DNow<0x0D, MRM0m, (outs), (ins i32mem:$addr),
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"prefetch $addr", []>;
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// FIXME: Diassembler gets a bogus decode conflict.
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let isAsmParserOnly = 1 in {
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let isAsmParserOnly = 1 in
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def PREFETCHW : I3DNow<0x0D, MRM1m, (outs), (ins i16mem:$addr),
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"prefetchw $addr", []>;
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}
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// "3DNowA" instructions
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defm PF2IW : I3DNow_binop_rm<0x1C, "pf2iw">;
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defm PI2FW : I3DNow_binop_rm<0x0C, "pi2fw">;
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defm PFNACC : I3DNow_binop_rm<0x8A, "pfnacc">;
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defm PFPNACC : I3DNow_binop_rm<0x8E, "pfpnacc">;
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defm PSWAPD : I3DNow_binop_rm<0xBB, "pswapd">;
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defm PF2IW : I3DNow_conv_rm_int<0x1C, "pf2iw", "a">;
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defm PI2FW : I3DNow_conv_rm_int<0x0C, "pi2fw", "a">;
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defm PFNACC : I3DNow_binop_rm_int<0x8A, "pfnacc", "a">;
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defm PFPNACC : I3DNow_binop_rm_int<0x8E, "pfpnacc", "a">;
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defm PSWAPD : I3DNow_conv_rm_int<0xBB, "pswapd", "a">;
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297
test/CodeGen/X86/3dnow-intrinsics.ll
Normal file
297
test/CodeGen/X86/3dnow-intrinsics.ll
Normal file
@ -0,0 +1,297 @@
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; RUN: llc < %s -march=x86 -mattr=+3dnow | FileCheck %s
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define <8 x i8> @test_pavgusb(x86_mmx %a.coerce, x86_mmx %b.coerce) nounwind readnone {
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; CHECK: pavgusb
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entry:
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%0 = bitcast x86_mmx %a.coerce to <8 x i8>
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%1 = bitcast x86_mmx %b.coerce to <8 x i8>
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%2 = bitcast <8 x i8> %0 to x86_mmx
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%3 = bitcast <8 x i8> %1 to x86_mmx
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%4 = call x86_mmx @llvm.x86.3dnow.pavgusb(x86_mmx %2, x86_mmx %3)
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%5 = bitcast x86_mmx %4 to <8 x i8>
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ret <8 x i8> %5
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}
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declare x86_mmx @llvm.x86.3dnow.pavgusb(x86_mmx, x86_mmx) nounwind readnone
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define <2 x i32> @test_pf2id(<2 x float> %a) nounwind readnone {
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; CHECK: pf2id
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entry:
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%0 = bitcast <2 x float> %a to x86_mmx
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%1 = tail call x86_mmx @llvm.x86.3dnow.pf2id(x86_mmx %0)
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%2 = bitcast x86_mmx %1 to <2 x i32>
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ret <2 x i32> %2
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}
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declare x86_mmx @llvm.x86.3dnow.pf2id(x86_mmx) nounwind readnone
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define <2 x float> @test_pfacc(<2 x float> %a, <2 x float> %b) nounwind readnone {
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; CHECK: pfacc
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entry:
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||||
%0 = bitcast <2 x float> %a to x86_mmx
|
||||
%1 = bitcast <2 x float> %b to x86_mmx
|
||||
%2 = tail call x86_mmx @llvm.x86.3dnow.pfacc(x86_mmx %0, x86_mmx %1)
|
||||
%3 = bitcast x86_mmx %2 to <2 x float>
|
||||
ret <2 x float> %3
|
||||
}
|
||||
|
||||
declare x86_mmx @llvm.x86.3dnow.pfacc(x86_mmx, x86_mmx) nounwind readnone
|
||||
|
||||
define <2 x float> @test_pfadd(<2 x float> %a, <2 x float> %b) nounwind readnone {
|
||||
; CHECK: pfadd
|
||||
entry:
|
||||
%0 = bitcast <2 x float> %a to x86_mmx
|
||||
%1 = bitcast <2 x float> %b to x86_mmx
|
||||
%2 = tail call x86_mmx @llvm.x86.3dnow.pfadd(x86_mmx %0, x86_mmx %1)
|
||||
%3 = bitcast x86_mmx %2 to <2 x float>
|
||||
ret <2 x float> %3
|
||||
}
|
||||
|
||||
declare x86_mmx @llvm.x86.3dnow.pfadd(x86_mmx, x86_mmx) nounwind readnone
|
||||
|
||||
define <2 x i32> @test_pfcmpeq(<2 x float> %a, <2 x float> %b) nounwind readnone {
|
||||
; CHECK: pfcmpeq
|
||||
entry:
|
||||
%0 = bitcast <2 x float> %a to x86_mmx
|
||||
%1 = bitcast <2 x float> %b to x86_mmx
|
||||
%2 = tail call x86_mmx @llvm.x86.3dnow.pfcmpeq(x86_mmx %0, x86_mmx %1)
|
||||
%3 = bitcast x86_mmx %2 to <2 x i32>
|
||||
ret <2 x i32> %3
|
||||
}
|
||||
|
||||
declare x86_mmx @llvm.x86.3dnow.pfcmpeq(x86_mmx, x86_mmx) nounwind readnone
|
||||
|
||||
define <2 x i32> @test_pfcmpge(<2 x float> %a, <2 x float> %b) nounwind readnone {
|
||||
; CHECK: pfcmpge
|
||||
entry:
|
||||
%0 = bitcast <2 x float> %a to x86_mmx
|
||||
%1 = bitcast <2 x float> %b to x86_mmx
|
||||
%2 = tail call x86_mmx @llvm.x86.3dnow.pfcmpge(x86_mmx %0, x86_mmx %1)
|
||||
%3 = bitcast x86_mmx %2 to <2 x i32>
|
||||
ret <2 x i32> %3
|
||||
}
|
||||
|
||||
declare x86_mmx @llvm.x86.3dnow.pfcmpge(x86_mmx, x86_mmx) nounwind readnone
|
||||
|
||||
define <2 x i32> @test_pfcmpgt(<2 x float> %a, <2 x float> %b) nounwind readnone {
|
||||
; CHECK: pfcmpgt
|
||||
entry:
|
||||
%0 = bitcast <2 x float> %a to x86_mmx
|
||||
%1 = bitcast <2 x float> %b to x86_mmx
|
||||
%2 = tail call x86_mmx @llvm.x86.3dnow.pfcmpgt(x86_mmx %0, x86_mmx %1)
|
||||
%3 = bitcast x86_mmx %2 to <2 x i32>
|
||||
ret <2 x i32> %3
|
||||
}
|
||||
|
||||
declare x86_mmx @llvm.x86.3dnow.pfcmpgt(x86_mmx, x86_mmx) nounwind readnone
|
||||
|
||||
define <2 x float> @test_pfmax(<2 x float> %a, <2 x float> %b) nounwind readnone {
|
||||
; CHECK: pfmax
|
||||
entry:
|
||||
%0 = bitcast <2 x float> %a to x86_mmx
|
||||
%1 = bitcast <2 x float> %b to x86_mmx
|
||||
%2 = tail call x86_mmx @llvm.x86.3dnow.pfmax(x86_mmx %0, x86_mmx %1)
|
||||
%3 = bitcast x86_mmx %2 to <2 x float>
|
||||
ret <2 x float> %3
|
||||
}
|
||||
|
||||
declare x86_mmx @llvm.x86.3dnow.pfmax(x86_mmx, x86_mmx) nounwind readnone
|
||||
|
||||
define <2 x float> @test_pfmin(<2 x float> %a, <2 x float> %b) nounwind readnone {
|
||||
; CHECK: pfmin
|
||||
entry:
|
||||
%0 = bitcast <2 x float> %a to x86_mmx
|
||||
%1 = bitcast <2 x float> %b to x86_mmx
|
||||
%2 = tail call x86_mmx @llvm.x86.3dnow.pfmin(x86_mmx %0, x86_mmx %1)
|
||||
%3 = bitcast x86_mmx %2 to <2 x float>
|
||||
ret <2 x float> %3
|
||||
}
|
||||
|
||||
declare x86_mmx @llvm.x86.3dnow.pfmin(x86_mmx, x86_mmx) nounwind readnone
|
||||
|
||||
define <2 x float> @test_pfmul(<2 x float> %a, <2 x float> %b) nounwind readnone {
|
||||
; CHECK: pfmul
|
||||
entry:
|
||||
%0 = bitcast <2 x float> %a to x86_mmx
|
||||
%1 = bitcast <2 x float> %b to x86_mmx
|
||||
%2 = tail call x86_mmx @llvm.x86.3dnow.pfmul(x86_mmx %0, x86_mmx %1)
|
||||
%3 = bitcast x86_mmx %2 to <2 x float>
|
||||
ret <2 x float> %3
|
||||
}
|
||||
|
||||
declare x86_mmx @llvm.x86.3dnow.pfmul(x86_mmx, x86_mmx) nounwind readnone
|
||||
|
||||
define <2 x float> @test_pfrcp(<2 x float> %a) nounwind readnone {
|
||||
; CHECK: pfrcp
|
||||
entry:
|
||||
%0 = bitcast <2 x float> %a to x86_mmx
|
||||
%1 = tail call x86_mmx @llvm.x86.3dnow.pfrcp(x86_mmx %0)
|
||||
%2 = bitcast x86_mmx %1 to <2 x float>
|
||||
ret <2 x float> %2
|
||||
}
|
||||
|
||||
declare x86_mmx @llvm.x86.3dnow.pfrcp(x86_mmx) nounwind readnone
|
||||
|
||||
define <2 x float> @test_pfrcpit1(<2 x float> %a, <2 x float> %b) nounwind readnone {
|
||||
; CHECK: pfrcpit1
|
||||
entry:
|
||||
%0 = bitcast <2 x float> %a to x86_mmx
|
||||
%1 = bitcast <2 x float> %b to x86_mmx
|
||||
%2 = tail call x86_mmx @llvm.x86.3dnow.pfrcpit1(x86_mmx %0, x86_mmx %1)
|
||||
%3 = bitcast x86_mmx %2 to <2 x float>
|
||||
ret <2 x float> %3
|
||||
}
|
||||
|
||||
declare x86_mmx @llvm.x86.3dnow.pfrcpit1(x86_mmx, x86_mmx) nounwind readnone
|
||||
|
||||
define <2 x float> @test_pfrcpit2(<2 x float> %a, <2 x float> %b) nounwind readnone {
|
||||
; CHECK: pfrcpit2
|
||||
entry:
|
||||
%0 = bitcast <2 x float> %a to x86_mmx
|
||||
%1 = bitcast <2 x float> %b to x86_mmx
|
||||
%2 = tail call x86_mmx @llvm.x86.3dnow.pfrcpit2(x86_mmx %0, x86_mmx %1)
|
||||
%3 = bitcast x86_mmx %2 to <2 x float>
|
||||
ret <2 x float> %3
|
||||
}
|
||||
|
||||
declare x86_mmx @llvm.x86.3dnow.pfrcpit2(x86_mmx, x86_mmx) nounwind readnone
|
||||
|
||||
define <2 x float> @test_pfrsqrt(<2 x float> %a) nounwind readnone {
|
||||
; CHECK: pfrsqrt
|
||||
entry:
|
||||
%0 = bitcast <2 x float> %a to x86_mmx
|
||||
%1 = tail call x86_mmx @llvm.x86.3dnow.pfrsqrt(x86_mmx %0)
|
||||
%2 = bitcast x86_mmx %1 to <2 x float>
|
||||
ret <2 x float> %2
|
||||
}
|
||||
|
||||
declare x86_mmx @llvm.x86.3dnow.pfrsqrt(x86_mmx) nounwind readnone
|
||||
|
||||
define <2 x float> @test_pfrsqit1(<2 x float> %a, <2 x float> %b) nounwind readnone {
|
||||
; CHECK: pfrsqit1
|
||||
entry:
|
||||
%0 = bitcast <2 x float> %a to x86_mmx
|
||||
%1 = bitcast <2 x float> %b to x86_mmx
|
||||
%2 = tail call x86_mmx @llvm.x86.3dnow.pfrsqit1(x86_mmx %0, x86_mmx %1)
|
||||
%3 = bitcast x86_mmx %2 to <2 x float>
|
||||
ret <2 x float> %3
|
||||
}
|
||||
|
||||
declare x86_mmx @llvm.x86.3dnow.pfrsqit1(x86_mmx, x86_mmx) nounwind readnone
|
||||
|
||||
define <2 x float> @test_pfsub(<2 x float> %a, <2 x float> %b) nounwind readnone {
|
||||
; CHECK: pfsub
|
||||
entry:
|
||||
%0 = bitcast <2 x float> %a to x86_mmx
|
||||
%1 = bitcast <2 x float> %b to x86_mmx
|
||||
%2 = tail call x86_mmx @llvm.x86.3dnow.pfsub(x86_mmx %0, x86_mmx %1)
|
||||
%3 = bitcast x86_mmx %2 to <2 x float>
|
||||
ret <2 x float> %3
|
||||
}
|
||||
|
||||
declare x86_mmx @llvm.x86.3dnow.pfsub(x86_mmx, x86_mmx) nounwind readnone
|
||||
|
||||
define <2 x float> @test_pfsubr(<2 x float> %a, <2 x float> %b) nounwind readnone {
|
||||
; CHECK: pfsubr
|
||||
entry:
|
||||
%0 = bitcast <2 x float> %a to x86_mmx
|
||||
%1 = bitcast <2 x float> %b to x86_mmx
|
||||
%2 = tail call x86_mmx @llvm.x86.3dnow.pfsubr(x86_mmx %0, x86_mmx %1)
|
||||
%3 = bitcast x86_mmx %2 to <2 x float>
|
||||
ret <2 x float> %3
|
||||
}
|
||||
|
||||
declare x86_mmx @llvm.x86.3dnow.pfsubr(x86_mmx, x86_mmx) nounwind readnone
|
||||
|
||||
define <2 x float> @test_pi2fd(x86_mmx %a.coerce) nounwind readnone {
|
||||
; CHECK: pi2fd
|
||||
entry:
|
||||
%0 = bitcast x86_mmx %a.coerce to <2 x i32>
|
||||
%1 = bitcast <2 x i32> %0 to x86_mmx
|
||||
%2 = call x86_mmx @llvm.x86.3dnow.pi2fd(x86_mmx %1)
|
||||
%3 = bitcast x86_mmx %2 to <2 x float>
|
||||
ret <2 x float> %3
|
||||
}
|
||||
|
||||
declare x86_mmx @llvm.x86.3dnow.pi2fd(x86_mmx) nounwind readnone
|
||||
|
||||
define <4 x i16> @test_pmulhrw(x86_mmx %a.coerce, x86_mmx %b.coerce) nounwind readnone {
|
||||
; CHECK: pmulhrw
|
||||
entry:
|
||||
%0 = bitcast x86_mmx %a.coerce to <4 x i16>
|
||||
%1 = bitcast x86_mmx %b.coerce to <4 x i16>
|
||||
%2 = bitcast <4 x i16> %0 to x86_mmx
|
||||
%3 = bitcast <4 x i16> %1 to x86_mmx
|
||||
%4 = call x86_mmx @llvm.x86.3dnow.pmulhrw(x86_mmx %2, x86_mmx %3)
|
||||
%5 = bitcast x86_mmx %4 to <4 x i16>
|
||||
ret <4 x i16> %5
|
||||
}
|
||||
|
||||
declare x86_mmx @llvm.x86.3dnow.pmulhrw(x86_mmx, x86_mmx) nounwind readnone
|
||||
|
||||
define <2 x i32> @test_pf2iw(<2 x float> %a) nounwind readnone {
|
||||
; CHECK: pf2iw
|
||||
entry:
|
||||
%0 = bitcast <2 x float> %a to x86_mmx
|
||||
%1 = tail call x86_mmx @llvm.x86.3dnowa.pf2iw(x86_mmx %0)
|
||||
%2 = bitcast x86_mmx %1 to <2 x i32>
|
||||
ret <2 x i32> %2
|
||||
}
|
||||
|
||||
declare x86_mmx @llvm.x86.3dnowa.pf2iw(x86_mmx) nounwind readnone
|
||||
|
||||
define <2 x float> @test_pfnacc(<2 x float> %a, <2 x float> %b) nounwind readnone {
|
||||
; CHECK: pfnacc
|
||||
entry:
|
||||
%0 = bitcast <2 x float> %a to x86_mmx
|
||||
%1 = bitcast <2 x float> %b to x86_mmx
|
||||
%2 = tail call x86_mmx @llvm.x86.3dnowa.pfnacc(x86_mmx %0, x86_mmx %1)
|
||||
%3 = bitcast x86_mmx %2 to <2 x float>
|
||||
ret <2 x float> %3
|
||||
}
|
||||
|
||||
declare x86_mmx @llvm.x86.3dnowa.pfnacc(x86_mmx, x86_mmx) nounwind readnone
|
||||
|
||||
define <2 x float> @test_pfpnacc(<2 x float> %a, <2 x float> %b) nounwind readnone {
|
||||
; CHECK: pfpnacc
|
||||
entry:
|
||||
%0 = bitcast <2 x float> %a to x86_mmx
|
||||
%1 = bitcast <2 x float> %b to x86_mmx
|
||||
%2 = tail call x86_mmx @llvm.x86.3dnowa.pfpnacc(x86_mmx %0, x86_mmx %1)
|
||||
%3 = bitcast x86_mmx %2 to <2 x float>
|
||||
ret <2 x float> %3
|
||||
}
|
||||
|
||||
declare x86_mmx @llvm.x86.3dnowa.pfpnacc(x86_mmx, x86_mmx) nounwind readnone
|
||||
|
||||
define <2 x float> @test_pi2fw(x86_mmx %a.coerce) nounwind readnone {
|
||||
; CHECK: pi2fw
|
||||
entry:
|
||||
%0 = bitcast x86_mmx %a.coerce to <2 x i32>
|
||||
%1 = bitcast <2 x i32> %0 to x86_mmx
|
||||
%2 = call x86_mmx @llvm.x86.3dnowa.pi2fw(x86_mmx %1)
|
||||
%3 = bitcast x86_mmx %2 to <2 x float>
|
||||
ret <2 x float> %3
|
||||
}
|
||||
|
||||
declare x86_mmx @llvm.x86.3dnowa.pi2fw(x86_mmx) nounwind readnone
|
||||
|
||||
define <2 x float> @test_pswapdsf(<2 x float> %a) nounwind readnone {
|
||||
; CHECK: pswapd
|
||||
entry:
|
||||
%0 = bitcast <2 x float> %a to x86_mmx
|
||||
%1 = tail call x86_mmx @llvm.x86.3dnowa.pswapd(x86_mmx %0)
|
||||
%2 = bitcast x86_mmx %1 to <2 x float>
|
||||
ret <2 x float> %2
|
||||
}
|
||||
|
||||
define <2 x i32> @test_pswapdsi(<2 x i32> %a) nounwind readnone {
|
||||
; CHECK: pswapd
|
||||
entry:
|
||||
%0 = bitcast <2 x i32> %a to x86_mmx
|
||||
%1 = tail call x86_mmx @llvm.x86.3dnowa.pswapd(x86_mmx %0)
|
||||
%2 = bitcast x86_mmx %1 to <2 x i32>
|
||||
ret <2 x i32> %2
|
||||
}
|
||||
|
||||
declare x86_mmx @llvm.x86.3dnowa.pswapd(x86_mmx) nounwind readnone
|
||||
Loading…
Reference in New Issue
Block a user