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[X86] Mark all sizes of (V)MOVUPD as trivially rematerializable.
I don't know for sure that we truly needs this, but its the only vector load that isn't rematerializable. Making it consistent allows it to not be a special case in the td files. llvm-svn: 283083
This commit is contained in:
Craig Topper
parent
c8b06fb7ec
commit
05ed355772
@ -2609,7 +2609,6 @@ defm : mask_shift_lowering<VK2, v2i1>, Requires<[HasAVX512]>;
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multiclass avx512_load<bits<8> opc, string OpcodeStr, X86VectorVTInfo _,
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PatFrag ld_frag, PatFrag mload,
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bit IsReMaterializable = 1,
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SDPatternOperator SelectOprr = vselect> {
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let hasSideEffects = 0 in {
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def rr : AVX512PI<opc, MRMSrcReg, (outs _.RC:$dst), (ins _.RC:$src),
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@ -2624,7 +2623,7 @@ multiclass avx512_load<bits<8> opc, string OpcodeStr, X86VectorVTInfo _,
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_.ImmAllZerosV)))], _.ExeDomain>,
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EVEX, EVEX_KZ;
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let canFoldAsLoad = 1, isReMaterializable = IsReMaterializable,
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let canFoldAsLoad = 1, isReMaterializable = 1,
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SchedRW = [WriteLoad] in
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def rm : AVX512PI<opc, MRMSrcMem, (outs _.RC:$dst), (ins _.MemOp:$src),
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!strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
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@ -2672,37 +2671,32 @@ multiclass avx512_load<bits<8> opc, string OpcodeStr, X86VectorVTInfo _,
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multiclass avx512_alignedload_vl<bits<8> opc, string OpcodeStr,
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AVX512VLVectorVTInfo _,
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Predicate prd,
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bit IsReMaterializable = 1> {
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Predicate prd> {
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let Predicates = [prd] in
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defm Z : avx512_load<opc, OpcodeStr, _.info512, _.info512.AlignedLdFrag,
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masked_load_aligned512, IsReMaterializable>, EVEX_V512;
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masked_load_aligned512>, EVEX_V512;
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let Predicates = [prd, HasVLX] in {
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defm Z256 : avx512_load<opc, OpcodeStr, _.info256, _.info256.AlignedLdFrag,
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masked_load_aligned256, IsReMaterializable>, EVEX_V256;
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masked_load_aligned256>, EVEX_V256;
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defm Z128 : avx512_load<opc, OpcodeStr, _.info128, _.info128.AlignedLdFrag,
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masked_load_aligned128, IsReMaterializable>, EVEX_V128;
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masked_load_aligned128>, EVEX_V128;
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}
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}
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multiclass avx512_load_vl<bits<8> opc, string OpcodeStr,
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AVX512VLVectorVTInfo _,
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Predicate prd,
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bit IsReMaterializable = 1,
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SDPatternOperator SelectOprr = vselect> {
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let Predicates = [prd] in
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defm Z : avx512_load<opc, OpcodeStr, _.info512, _.info512.LdFrag,
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masked_load_unaligned, IsReMaterializable,
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SelectOprr>, EVEX_V512;
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masked_load_unaligned, SelectOprr>, EVEX_V512;
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let Predicates = [prd, HasVLX] in {
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defm Z256 : avx512_load<opc, OpcodeStr, _.info256, _.info256.LdFrag,
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masked_load_unaligned, IsReMaterializable,
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SelectOprr>, EVEX_V256;
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masked_load_unaligned, SelectOprr>, EVEX_V256;
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defm Z128 : avx512_load<opc, OpcodeStr, _.info128, _.info128.LdFrag,
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masked_load_unaligned, IsReMaterializable,
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SelectOprr>, EVEX_V128;
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masked_load_unaligned, SelectOprr>, EVEX_V128;
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}
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}
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@ -2778,11 +2772,11 @@ defm VMOVAPD : avx512_alignedload_vl<0x28, "vmovapd", avx512vl_f64_info,
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HasAVX512>, PD, VEX_W, EVEX_CD8<64, CD8VF>;
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defm VMOVUPS : avx512_load_vl<0x10, "vmovups", avx512vl_f32_info, HasAVX512,
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1, null_frag>,
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null_frag>,
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avx512_store_vl<0x11, "vmovups", avx512vl_f32_info, HasAVX512>,
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PS, EVEX_CD8<32, CD8VF>;
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defm VMOVUPD : avx512_load_vl<0x10, "vmovupd", avx512vl_f64_info, HasAVX512, 0,
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defm VMOVUPD : avx512_load_vl<0x10, "vmovupd", avx512vl_f64_info, HasAVX512,
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null_frag>,
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avx512_store_vl<0x11, "vmovupd", avx512vl_f64_info, HasAVX512>,
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PD, VEX_W, EVEX_CD8<64, CD8VF>;
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@ -2806,12 +2800,12 @@ defm VMOVDQU16 : avx512_load_vl<0x6F, "vmovdqu16", avx512vl_i16_info, HasBWI>,
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HasBWI>, XD, VEX_W, EVEX_CD8<16, CD8VF>;
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defm VMOVDQU32 : avx512_load_vl<0x6F, "vmovdqu32", avx512vl_i32_info, HasAVX512,
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1, null_frag>,
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null_frag>,
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avx512_store_vl<0x7F, "vmovdqu32", avx512vl_i32_info,
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HasAVX512>, XS, EVEX_CD8<32, CD8VF>;
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defm VMOVDQU64 : avx512_load_vl<0x6F, "vmovdqu64", avx512vl_i64_info, HasAVX512,
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1, null_frag>,
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null_frag>,
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avx512_store_vl<0x7F, "vmovdqu64", avx512vl_i64_info,
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HasAVX512>, XS, VEX_W, EVEX_CD8<64, CD8VF>;
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@ -2629,6 +2629,7 @@ bool X86InstrInfo::isReallyTriviallyReMaterializable(const MachineInstr &MI,
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case X86::MOVAPSrm:
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case X86::MOVUPSrm:
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case X86::MOVAPDrm:
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case X86::MOVUPDrm:
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case X86::MOVDQArm:
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case X86::MOVDQUrm:
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case X86::VMOVSSrm:
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@ -2636,11 +2637,13 @@ bool X86InstrInfo::isReallyTriviallyReMaterializable(const MachineInstr &MI,
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case X86::VMOVAPSrm:
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case X86::VMOVUPSrm:
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case X86::VMOVAPDrm:
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case X86::VMOVUPDrm:
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case X86::VMOVDQArm:
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case X86::VMOVDQUrm:
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case X86::VMOVAPSYrm:
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case X86::VMOVUPSYrm:
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case X86::VMOVAPDYrm:
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case X86::VMOVUPDYrm:
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case X86::VMOVDQAYrm:
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case X86::VMOVDQUYrm:
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case X86::MMX_MOVD64rm:
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@ -2674,6 +2677,9 @@ bool X86InstrInfo::isReallyTriviallyReMaterializable(const MachineInstr &MI,
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case X86::VMOVDQU8Z128rm:
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case X86::VMOVDQU8Z256rm:
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case X86::VMOVDQU8Zrm:
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case X86::VMOVUPDZ128rm:
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case X86::VMOVUPDZ256rm:
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case X86::VMOVUPDZrm:
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case X86::VMOVUPSZ128rm:
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case X86::VMOVUPSZ256rm:
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case X86::VMOVUPSZ128rm_NOVLX:
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@ -774,13 +774,12 @@ def : InstAlias<"vmovsd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
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multiclass sse12_mov_packed<bits<8> opc, RegisterClass RC,
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X86MemOperand x86memop, PatFrag ld_frag,
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string asm, Domain d,
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OpndItins itins,
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bit IsReMaterializable = 1> {
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OpndItins itins> {
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let hasSideEffects = 0 in
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def rr : PI<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src),
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!strconcat(asm, "\t{$src, $dst|$dst, $src}"), [], itins.rr, d>,
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Sched<[WriteFShuffle]>;
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let canFoldAsLoad = 1, isReMaterializable = IsReMaterializable in
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let canFoldAsLoad = 1, isReMaterializable = 1 in
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def rm : PI<opc, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
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!strconcat(asm, "\t{$src, $dst|$dst, $src}"),
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[(set RC:$dst, (ld_frag addr:$src))], itins.rm, d>,
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@ -798,7 +797,7 @@ defm VMOVUPS : sse12_mov_packed<0x10, VR128, f128mem, loadv4f32,
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"movups", SSEPackedSingle, SSE_MOVU_ITINS>,
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PS, VEX;
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defm VMOVUPD : sse12_mov_packed<0x10, VR128, f128mem, loadv2f64,
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"movupd", SSEPackedDouble, SSE_MOVU_ITINS, 0>,
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"movupd", SSEPackedDouble, SSE_MOVU_ITINS>,
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PD, VEX;
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defm VMOVAPSY : sse12_mov_packed<0x28, VR256, f256mem, alignedloadv8f32,
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@ -811,7 +810,7 @@ defm VMOVUPSY : sse12_mov_packed<0x10, VR256, f256mem, loadv8f32,
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"movups", SSEPackedSingle, SSE_MOVU_ITINS>,
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PS, VEX, VEX_L;
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defm VMOVUPDY : sse12_mov_packed<0x10, VR256, f256mem, loadv4f64,
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"movupd", SSEPackedDouble, SSE_MOVU_ITINS, 0>,
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"movupd", SSEPackedDouble, SSE_MOVU_ITINS>,
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PD, VEX, VEX_L;
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}
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@ -828,7 +827,7 @@ defm MOVAPD : sse12_mov_packed<0x28, VR128, f128mem, alignedloadv2f64,
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"movapd", SSEPackedDouble, SSE_MOVA_ITINS>,
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PD;
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defm MOVUPD : sse12_mov_packed<0x10, VR128, f128mem, loadv2f64,
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"movupd", SSEPackedDouble, SSE_MOVU_ITINS, 0>,
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"movupd", SSEPackedDouble, SSE_MOVU_ITINS>,
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PD;
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}
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