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GlobalISel: rework CallLowering so that it can be used for libcalls too.
There should be no functional change here, I'm just making the implementation of "frem" (to libcall) legalization easier for a followup. llvm-svn: 279987
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@ -16,11 +16,13 @@
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#define LLVM_CODEGEN_GLOBALISEL_CALLLOWERING_H
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#include "llvm/ADT/SmallVector.h"
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#include "llvm/CodeGen/ValueTypes.h"
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#include "llvm/IR/Function.h"
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namespace llvm {
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// Forward declarations.
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class MachineIRBuilder;
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class MachineOperand;
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class TargetLowering;
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class Value;
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@ -70,9 +72,31 @@ class CallLowering {
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/// This hook must be implemented to lower the given call instruction,
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/// including argument and return value marshalling.
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///
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/// \p CalleeReg is a virtual-register containing the destination if
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/// `CI.getCalledFunction()` returns null (i.e. if the call is indirect);
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/// otherwise it is 0.
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/// \p Callee is the destination of the call. It should be either a register,
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/// globaladdress, or externalsymbol.
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///
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/// \p ResTys is a list of the individual result types this function call will
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/// produce. The types are used to assign physical registers to each slot.
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///
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/// \p ResRegs is a list of the virtual registers that we expect to be defined
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/// by this call, one per entry in \p ResTys.
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///
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/// \p ArgTys is a list of the types each member of \p ArgRegs has; used by
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/// the target to decide which register/stack slot should be allocated.
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///
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/// \p ArgRegs is a list of virtual registers containing each argument that
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/// needs to be passed.
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///
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/// \return true if the lowering succeeded, false otherwise.
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virtual bool lowerCall(MachineIRBuilder &MIRBuilder, MachineOperand &Callee,
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ArrayRef<MVT> ResTys, ArrayRef<unsigned> ResRegs,
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ArrayRef<MVT> ArgTys,
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ArrayRef<unsigned> ArgRegs) const {
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return false;
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}
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/// This hook must be implemented to lower the given call instruction,
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/// including argument and return value marshalling.
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///
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/// \p ResReg is a register where the call's return value should be stored (or
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/// 0 if there is no return value).
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@ -80,12 +104,15 @@ class CallLowering {
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/// \p ArgRegs is a list of virtual registers containing each argument that
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/// needs to be passed.
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///
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/// \p GetCalleeReg is a callback to materialize a register for the callee if
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/// the target determines it cannot jump to the destination based purely on \p
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/// CI. This might be because \p CI is indirect, or because of the limited
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/// range of an immediate jump.
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///
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/// \return true if the lowering succeeded, false otherwise.
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virtual bool lowerCall(MachineIRBuilder &MIRBuilder, const CallInst &CI,
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unsigned CalleeReg, unsigned ResReg,
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ArrayRef<unsigned> ArgRegs) const {
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return false;
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}
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unsigned ResReg, ArrayRef<unsigned> ArgRegs,
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std::function<unsigned()> GetCalleeReg) const;
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};
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} // End namespace llvm.
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@ -1,5 +1,6 @@
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# List of all GlobalISel files.
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set(GLOBAL_ISEL_FILES
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CallLowering.cpp
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IRTranslator.cpp
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InstructionSelect.cpp
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InstructionSelector.cpp
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40
lib/CodeGen/GlobalISel/CallLowering.cpp
Normal file
40
lib/CodeGen/GlobalISel/CallLowering.cpp
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@ -0,0 +1,40 @@
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//===-- lib/CodeGen/GlobalISel/CallLowering.cpp - Call lowering -----------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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///
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/// \file
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/// This file implements some simple delegations needed for call lowering.
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///
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//===----------------------------------------------------------------------===//
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#include "llvm/CodeGen/GlobalISel/CallLowering.h"
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#include "llvm/CodeGen/MachineOperand.h"
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#include "llvm/IR/Instructions.h"
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using namespace llvm;
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bool CallLowering::lowerCall(
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MachineIRBuilder &MIRBuilder, const CallInst &CI, unsigned ResReg,
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ArrayRef<unsigned> ArgRegs, std::function<unsigned()> GetCalleeReg) const {
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// First step is to marshall all the function's parameters into the correct
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// physregs and memory locations. Gather the sequence of argument types that
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// we'll pass to the assigner function.
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SmallVector<MVT, 8> ArgTys;
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for (auto &Arg : CI.arg_operands())
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ArgTys.push_back(MVT::getVT(Arg->getType()));
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MachineOperand Callee = MachineOperand::CreateImm(0);
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if (Function *F = CI.getCalledFunction())
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Callee = MachineOperand::CreateGA(F, 0);
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else
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Callee = MachineOperand::CreateReg(GetCalleeReg(), false);
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return lowerCall(MIRBuilder, Callee, MVT::getVT(CI.getType()),
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ResReg ? ResReg : ArrayRef<unsigned>(), ArgTys, ArgRegs);
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}
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@ -347,9 +347,9 @@ bool IRTranslator::translateCall(const User &U) {
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for (auto &Arg: CI.arg_operands())
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Args.push_back(getOrCreateVReg(*Arg));
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return CLI->lowerCall(MIRBuilder, CI,
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F ? 0 : getOrCreateVReg(*CI.getCalledValue()), Res,
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Args);
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return CLI->lowerCall(MIRBuilder, CI, Res, Args, [&]() {
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return getOrCreateVReg(*CI.getCalledValue());
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});
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}
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Intrinsic::ID ID = F->getIntrinsicID();
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@ -131,19 +131,14 @@ bool AArch64CallLowering::lowerFormalArguments(
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}
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bool AArch64CallLowering::lowerCall(MachineIRBuilder &MIRBuilder,
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const CallInst &CI, unsigned CalleeReg,
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unsigned ResReg,
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MachineOperand &Callee,
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ArrayRef<MVT> ResTys,
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ArrayRef<unsigned> ResRegs,
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ArrayRef<MVT> ArgTys,
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ArrayRef<unsigned> ArgRegs) const {
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MachineFunction &MF = MIRBuilder.getMF();
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const Function &F = *MF.getFunction();
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// First step is to marshall all the function's parameters into the correct
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// physregs and memory locations. Gather the sequence of argument types that
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// we'll pass to the assigner function.
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SmallVector<MVT, 8> ArgTys;
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for (auto &Arg : CI.arg_operands())
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ArgTys.push_back(MVT::getVT(Arg->getType()));
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// Find out which ABI gets to decide where things go.
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const AArch64TargetLowering &TLI = *getTLI<AArch64TargetLowering>();
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CCAssignFn *CallAssignFn =
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@ -160,12 +155,8 @@ bool AArch64CallLowering::lowerCall(MachineIRBuilder &MIRBuilder,
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});
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// Now we can build the actual call instruction.
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MachineInstrBuilder MIB;
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if (CalleeReg)
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MIB = MIRBuilder.buildInstr(AArch64::BLR).addUse(CalleeReg);
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else
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MIB = MIRBuilder.buildInstr(AArch64::BL)
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.addGlobalAddress(CI.getCalledFunction());
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auto MIB = MIRBuilder.buildInstr(Callee.isReg() ? AArch64::BLR : AArch64::BL);
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MIB.addOperand(Callee);
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// Tell the call which registers are clobbered.
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auto TRI = MF.getSubtarget().getRegisterInfo();
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@ -178,9 +169,9 @@ bool AArch64CallLowering::lowerCall(MachineIRBuilder &MIRBuilder,
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// symmetry with the arugments, the physical register must be an
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// implicit-define of the call instruction.
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CCAssignFn *RetAssignFn = TLI.CCAssignFnForReturn(F.getCallingConv());
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if (!CI.getType()->isVoidTy())
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if (!ResRegs.empty())
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handleAssignments(
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MIRBuilder, RetAssignFn, MVT::getVT(CI.getType()), ResReg,
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MIRBuilder, RetAssignFn, ResTys, ResRegs,
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[&](MachineIRBuilder &MIRBuilder, unsigned ValReg, unsigned PhysReg) {
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MIRBuilder.buildCopy(ValReg, PhysReg);
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MIB.addDef(PhysReg, RegState::Implicit);
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@ -34,8 +34,9 @@ class AArch64CallLowering: public CallLowering {
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const Function::ArgumentListType &Args,
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ArrayRef<unsigned> VRegs) const override;
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bool lowerCall(MachineIRBuilder &MIRBuilder, const CallInst &CI,
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unsigned CalleeReg, unsigned ResReg,
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bool lowerCall(MachineIRBuilder &MIRBuilder, MachineOperand &Callee,
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ArrayRef<MVT> ResTys, ArrayRef<unsigned> ResRegs,
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ArrayRef<MVT> ArgTys,
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ArrayRef<unsigned> ArgRegs) const override;
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private:
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