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[AMDGPU] Make sure all super regs of reserved regs are marked reserved.

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Summary:
Move reserveRegisterTuples into AMDGPURegisterInfo and use it in
R600RegisterInfo::getReservedRegs and
R600InstrInfo::reserveIndirectRegisters to ensure that all super
registers of reserved registers are also marked as reserved.

Before this change, under certain circumstances, the registers %t1_x and
%t1_xyzw would be marked as reserved, but %t1_xy and %t1_xyz would not
be, leading to the register allocator sometimes assigning a register to
%t1_xy, which is invalid since %t1_x is reserved.

Reviewers: arsenm, tstellar, MatzeB, qcolombet

Subscribers: kzhuravl, wdng, nhaehnle, yaxunl, dstuttard, tpr, t-tye, mcrosier, llvm-commits

Differential Revision: https://reviews.llvm.org/D42448

llvm-svn: 323356
This commit is contained in:
Geoff Berry 2018-01-24 18:09:53 +00:00
parent 1ae074fb0f
commit 0620939033
7 changed files with 30 additions and 29 deletions
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7
lib/Target/AMDGPU/AMDGPURegisterInfo.cpp
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@ -37,6 +37,13 @@ unsigned AMDGPURegisterInfo::getSubRegFromChannel(unsigned Channel) const {
return SubRegs[Channel];
}
void AMDGPURegisterInfo::reserveRegisterTuples(BitVector &Reserved, unsigned Reg) const {
MCRegAliasIterator R(Reg, this, true);
for (; R.isValid(); ++R)
Reserved.set(*R);
}
#define GET_REGINFO_TARGET_DESC
#include "AMDGPUGenRegisterInfo.inc"

2
lib/Target/AMDGPU/AMDGPURegisterInfo.h
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@ -30,6 +30,8 @@ struct AMDGPURegisterInfo : public AMDGPUGenRegisterInfo {
/// \returns the sub reg enum value for the given \p Channel
/// (e.g. getSubRegFromChannel(0) -> AMDGPU::sub0)
unsigned getSubRegFromChannel(unsigned Channel) const;
void reserveRegisterTuples(BitVector &, unsigned Reg) const;
};
} // End namespace llvm

7
lib/Target/AMDGPU/R600InstrInfo.cpp
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@ -1082,7 +1082,8 @@ bool R600InstrInfo::expandPostRAPseudo(MachineInstr &MI) const {
}
void R600InstrInfo::reserveIndirectRegisters(BitVector &Reserved,
const MachineFunction &MF) const {
const MachineFunction &MF,
const R600RegisterInfo &TRI) const {
const R600Subtarget &ST = MF.getSubtarget<R600Subtarget>();
const R600FrameLowering *TFL = ST.getFrameLowering();
@ -1093,11 +1094,9 @@ void R600InstrInfo::reserveIndirectRegisters(BitVector &Reserved,
return;
for (int Index = getIndirectIndexBegin(MF); Index <= End; ++Index) {
unsigned SuperReg = AMDGPU::R600_Reg128RegClass.getRegister(Index);
Reserved.set(SuperReg);
for (unsigned Chan = 0; Chan < StackWidth; ++Chan) {
unsigned Reg = AMDGPU::R600_TReg32RegClass.getRegister((4 * Index) + Chan);
Reserved.set(Reg);
TRI.reserveRegisterTuples(Reserved, Reg);
}
}
}

3
lib/Target/AMDGPU/R600InstrInfo.h
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@ -211,7 +211,8 @@ public:
/// \brief Reserve the registers that may be accesed using indirect addressing.
void reserveIndirectRegisters(BitVector &Reserved,
const MachineFunction &MF) const;
const MachineFunction &MF,
const R600RegisterInfo &TRI) const;
/// Calculate the "Indirect Address" for the given \p RegIndex and
/// \p Channel

32
lib/Target/AMDGPU/R600RegisterInfo.cpp
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@ -31,27 +31,27 @@ BitVector R600RegisterInfo::getReservedRegs(const MachineFunction &MF) const {
const R600Subtarget &ST = MF.getSubtarget<R600Subtarget>();
const R600InstrInfo *TII = ST.getInstrInfo();
Reserved.set(AMDGPU::ZERO);
Reserved.set(AMDGPU::HALF);
Reserved.set(AMDGPU::ONE);
Reserved.set(AMDGPU::ONE_INT);
Reserved.set(AMDGPU::NEG_HALF);
Reserved.set(AMDGPU::NEG_ONE);
Reserved.set(AMDGPU::PV_X);
Reserved.set(AMDGPU::ALU_LITERAL_X);
Reserved.set(AMDGPU::ALU_CONST);
Reserved.set(AMDGPU::PREDICATE_BIT);
Reserved.set(AMDGPU::PRED_SEL_OFF);
Reserved.set(AMDGPU::PRED_SEL_ZERO);
Reserved.set(AMDGPU::PRED_SEL_ONE);
Reserved.set(AMDGPU::INDIRECT_BASE_ADDR);
reserveRegisterTuples(Reserved, AMDGPU::ZERO);
reserveRegisterTuples(Reserved, AMDGPU::HALF);
reserveRegisterTuples(Reserved, AMDGPU::ONE);
reserveRegisterTuples(Reserved, AMDGPU::ONE_INT);
reserveRegisterTuples(Reserved, AMDGPU::NEG_HALF);
reserveRegisterTuples(Reserved, AMDGPU::NEG_ONE);
reserveRegisterTuples(Reserved, AMDGPU::PV_X);
reserveRegisterTuples(Reserved, AMDGPU::ALU_LITERAL_X);
reserveRegisterTuples(Reserved, AMDGPU::ALU_CONST);
reserveRegisterTuples(Reserved, AMDGPU::PREDICATE_BIT);
reserveRegisterTuples(Reserved, AMDGPU::PRED_SEL_OFF);
reserveRegisterTuples(Reserved, AMDGPU::PRED_SEL_ZERO);
reserveRegisterTuples(Reserved, AMDGPU::PRED_SEL_ONE);
reserveRegisterTuples(Reserved, AMDGPU::INDIRECT_BASE_ADDR);
for (TargetRegisterClass::iterator I = AMDGPU::R600_AddrRegClass.begin(),
E = AMDGPU::R600_AddrRegClass.end(); I != E; ++I) {
Reserved.set(*I);
reserveRegisterTuples(Reserved, *I);
}
TII->reserveIndirectRegisters(Reserved, MF);
TII->reserveIndirectRegisters(Reserved, MF, *this);
return Reserved;
}

7
lib/Target/AMDGPU/SIRegisterInfo.cpp
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@ -101,13 +101,6 @@ SIRegisterInfo::SIRegisterInfo(const SISubtarget &ST) :
VGPRSetID < NumRegPressureSets);
}
void SIRegisterInfo::reserveRegisterTuples(BitVector &Reserved, unsigned Reg) const {
MCRegAliasIterator R(Reg, this, true);
for (; R.isValid(); ++R)
Reserved.set(*R);
}
unsigned SIRegisterInfo::reservedPrivateSegmentBufferReg(
const MachineFunction &MF) const {

1
lib/Target/AMDGPU/SIRegisterInfo.h
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@ -36,7 +36,6 @@ private:
bool SpillSGPRToVGPR;
bool SpillSGPRToSMEM;
void reserveRegisterTuples(BitVector &, unsigned Reg) const;
void classifyPressureSet(unsigned PSetID, unsigned Reg,
BitVector &PressureSets) const;
public: