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[MCA] Add support for in-order CPUs
This patch adds a pipeline to support in-order CPUs such as ARM Cortex-A55. In-order pipeline implements a simplified version of Dispatch, Scheduler and Execute stages as a single stage. Entry and Retire stages are common for both in-order and out-of-order pipelines. Differential Revision: https://reviews.llvm.org/D94928
This commit is contained in:
Andrew Savonichev
parent
848f45b02f
commit
064cc1a22c
@ -16,8 +16,8 @@ available in LLVM (e.g. scheduling models) to statically measure the performance
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of machine code in a specific CPU.
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Performance is measured in terms of throughput as well as processor resource
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consumption. The tool currently works for processors with an out-of-order
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backend, for which there is a scheduling model available in LLVM.
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consumption. The tool currently works for processors with a backend for which
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there is a scheduling model available in LLVM.
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The main goal of this tool is not just to predict the performance of the code
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when run on the target, but also help with diagnosing potential performance
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@ -204,7 +204,8 @@ option specifies "``-``", then the output will also be sent to standard output.
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Print information about bottlenecks that affect the throughput. This analysis
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can be expensive, and it is disabled by default. Bottlenecks are highlighted
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in the summary view.
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in the summary view. Bottleneck analysis is currently not supported for
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processors with an in-order backend.
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.. option:: -json
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@ -388,7 +389,9 @@ overview of the performance throughput. Important performance indicators are
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Throughput).
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Field *DispatchWidth* is the maximum number of micro opcodes that are dispatched
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to the out-of-order backend every simulated cycle.
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to the out-of-order backend every simulated cycle. For processors with an
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in-order backend, *DispatchWidth* is the maximum number of micro opcodes issued
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to the backend every simulated cycle.
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IPC is computed dividing the total number of simulated instructions by the total
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number of cycles.
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@ -653,6 +656,8 @@ performance. By construction, the accuracy of this analysis is strongly
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dependent on the simulation and (as always) by the quality of the processor
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model in llvm.
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Bottleneck analysis is currently not supported for processors with an in-order
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backend.
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Extra Statistics to Further Diagnose Performance Issues
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^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
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@ -797,11 +802,14 @@ process instructions.
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* Write Back (Instruction is executed, and results are written back).
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* Retire (Instruction is retired; writes are architecturally committed).
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The default pipeline only models the out-of-order portion of a processor.
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Therefore, the instruction fetch and decode stages are not modeled. Performance
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bottlenecks in the frontend are not diagnosed. :program:`llvm-mca` assumes that
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instructions have all been decoded and placed into a queue before the simulation
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start. Also, :program:`llvm-mca` does not model branch prediction.
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The in-order pipeline implements the following sequence of stages:
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* InOrderIssue (Instruction is issued to the processor pipelines).
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* Retire (Instruction is retired; writes are architecturally committed).
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:program:`llvm-mca` assumes that instructions have all been decoded and placed
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into a queue before the simulation start. Therefore, the instruction fetch and
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decode stages are not modeled. Performance bottlenecks in the frontend are not
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diagnosed. Also, :program:`llvm-mca` does not model branch prediction.
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Instruction Dispatch
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""""""""""""""""""""
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@ -957,3 +965,17 @@ In conclusion, the full set of load/store consistency rules are:
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#. A load may pass a previous load.
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#. A load may not pass a previous store unless ``-noalias`` is set.
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#. A load has to wait until an older load barrier is fully executed.
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In-order Issue and Execute
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""""""""""""""""""""""""""""""""""""
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In-order processors are modelled as a single ``InOrderIssueStage`` stage. It
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bypasses Dispatch, Scheduler and Load/Store unit. Instructions are issued as
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soon as their operand registers are available and resource requirements are
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met. Multiple instructions can be issued in one cycle according to the value of
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the ``IssueWidth`` parameter in LLVM's scheduling model.
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Once issued, an instruction is moved to ``IssuedInst`` set until it is ready to
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retire. If ``RetireControlUnit`` is defined in the LLVM's scheduling model,
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:program:`llvm-mca` ensures that instructions are retired in-order. However, an
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instruction is allowed to retire out-of-order if ``RetireOOO`` property is true
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for at least one of its writes.
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@ -130,6 +130,9 @@ Changes to the LLVM tools
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* The options ``--build-id-link-{dir,input,output}`` have been deleted.
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(`D96310 <https://reviews.llvm.org/D96310>`_)
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* Support for in-order processors has been added to ``llvm-mca``.
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(`D94928 <https://reviews.llvm.org/D94928>`_)
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Changes to LLDB
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---------------------------------
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@ -108,15 +108,16 @@ struct MCReadAdvanceEntry {
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///
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/// Defined as an aggregate struct for creating tables with initializer lists.
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struct MCSchedClassDesc {
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static const unsigned short InvalidNumMicroOps = (1U << 14) - 1;
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static const unsigned short InvalidNumMicroOps = (1U << 13) - 1;
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static const unsigned short VariantNumMicroOps = InvalidNumMicroOps - 1;
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#if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)
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const char* Name;
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#endif
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uint16_t NumMicroOps : 14;
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uint16_t NumMicroOps : 13;
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uint16_t BeginGroup : 1;
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uint16_t EndGroup : 1;
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uint16_t RetireOOO : 1;
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uint16_t WriteProcResIdx; // First index into WriteProcResTable.
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uint16_t NumWriteProcResEntries;
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uint16_t WriteLatencyIdx; // First index into WriteLatencyTable.
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@ -68,6 +68,11 @@ public:
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/// This pipeline consists of Fetch, Dispatch, Execute, and Retire stages.
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std::unique_ptr<Pipeline> createDefaultPipeline(const PipelineOptions &Opts,
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SourceMgr &SrcMgr);
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/// Construct a basic pipeline for simulating an in-order pipeline.
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/// This pipeline consists of Fetch, InOrderIssue, and Retire stages.
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std::unique_ptr<Pipeline> createInOrderPipeline(const PipelineOptions &Opts,
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SourceMgr &SrcMgr);
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};
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} // namespace mca
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@ -172,11 +172,6 @@ class RegisterFile : public HardwareUnit {
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void freePhysRegs(const RegisterRenamingInfo &Entry,
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MutableArrayRef<unsigned> FreedPhysRegs);
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// Collects writes that are in a RAW dependency with RS.
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// This method is called from `addRegisterRead()`.
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void collectWrites(const ReadState &RS,
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SmallVectorImpl<WriteRef> &Writes) const;
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// Create an instance of RegisterMappingTracker for every register file
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// specified by the processor model.
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// If no register file is specified, then this method creates a default
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@ -187,6 +182,10 @@ public:
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RegisterFile(const MCSchedModel &SM, const MCRegisterInfo &mri,
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unsigned NumRegs = 0);
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// Collects writes that are in a RAW dependency with RS.
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void collectWrites(const ReadState &RS,
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SmallVectorImpl<WriteRef> &Writes) const;
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// This method updates the register mappings inserting a new register
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// definition. This method is also responsible for updating the number of
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// allocated physical registers in each register file modified by the write.
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@ -104,6 +104,9 @@ public:
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#ifndef NDEBUG
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void dump() const;
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#endif
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// Assigned to instructions that are not handled by the RCU.
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static const unsigned UnhandledTokenID = ~0U;
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};
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} // namespace mca
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@ -375,6 +375,7 @@ struct InstrDesc {
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bool HasSideEffects;
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bool BeginGroup;
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bool EndGroup;
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bool RetireOOO;
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// True if all buffered resources are in-order, and there is at least one
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// buffer which is a dispatch hazard (BufferSize = 0).
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84
include/llvm/MCA/Stages/InOrderIssueStage.h
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84
include/llvm/MCA/Stages/InOrderIssueStage.h
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@ -0,0 +1,84 @@
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//===---------------------- InOrderIssueStage.h -----------------*- C++ -*-===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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/// \file
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///
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/// InOrderIssueStage implements an in-order execution pipeline.
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///
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//===----------------------------------------------------------------------===//
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#ifndef LLVM_MCA_IN_ORDER_ISSUE_STAGE_H
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#define LLVM_MCA_IN_ORDER_ISSUE_STAGE_H
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#include "llvm/ADT/SmallVector.h"
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#include "llvm/MCA/SourceMgr.h"
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#include "llvm/MCA/Stages/Stage.h"
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#include <queue>
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namespace llvm {
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struct MCSchedModel;
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class MCSubtargetInfo;
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namespace mca {
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class RegisterFile;
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class ResourceManager;
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struct RetireControlUnit;
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class InOrderIssueStage final : public Stage {
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const MCSchedModel &SM;
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const MCSubtargetInfo &STI;
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RetireControlUnit &RCU;
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RegisterFile &PRF;
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std::unique_ptr<ResourceManager> RM;
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/// Instructions that were issued, but not executed yet.
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SmallVector<InstRef, 4> IssuedInst;
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/// Number of instructions issued in the current cycle.
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unsigned NumIssued;
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/// If an instruction cannot execute due to an unmet register or resource
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/// dependency, the it is stalled for StallCyclesLeft.
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InstRef StalledInst;
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unsigned StallCyclesLeft;
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/// Number of instructions that can be issued in the current cycle.
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unsigned Bandwidth;
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InOrderIssueStage(const InOrderIssueStage &Other) = delete;
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InOrderIssueStage &operator=(const InOrderIssueStage &Other) = delete;
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/// If IR has an unmet register or resource dependency, canExecute returns
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/// false. StallCycles is set to the number of cycles left before the
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/// instruction can be issued.
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bool canExecute(const InstRef &IR, unsigned *StallCycles) const;
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/// Issue the instruction, or update StallCycles if IR is stalled.
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Error tryIssue(InstRef &IR, unsigned *StallCycles);
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/// Update status of instructions from IssuedInst.
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Error updateIssuedInst();
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public:
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InOrderIssueStage(RetireControlUnit &RCU, RegisterFile &PRF,
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const MCSchedModel &SM, const MCSubtargetInfo &STI)
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: SM(SM), STI(STI), RCU(RCU), PRF(PRF),
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RM(std::make_unique<ResourceManager>(SM)), StallCyclesLeft(0),
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Bandwidth(0) {}
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bool isAvailable(const InstRef &) const override;
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bool hasWorkToComplete() const override;
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Error execute(InstRef &IR) override;
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Error cycleStart() override;
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Error cycleEnd() override;
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};
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} // namespace mca
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} // namespace llvm
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#endif // LLVM_MCA_IN_ORDER_ISSUE_STAGE_H
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@ -16,6 +16,7 @@
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#ifndef LLVM_MCA_STAGES_RETIRESTAGE_H
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#define LLVM_MCA_STAGES_RETIRESTAGE_H
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#include "llvm/ADT/SmallVector.h"
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#include "llvm/MCA/HardwareUnits/LSUnit.h"
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#include "llvm/MCA/HardwareUnits/RegisterFile.h"
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#include "llvm/MCA/HardwareUnits/RetireControlUnit.h"
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@ -29,6 +30,7 @@ class RetireStage final : public Stage {
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RetireControlUnit &RCU;
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RegisterFile &PRF;
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LSUnitBase &LSU;
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SmallVector<InstRef, 4> RetireInst;
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RetireStage(const RetireStage &Other) = delete;
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RetireStage &operator=(const RetireStage &Other) = delete;
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@ -37,7 +39,9 @@ public:
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RetireStage(RetireControlUnit &R, RegisterFile &F, LSUnitBase &LS)
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: Stage(), RCU(R), PRF(F), LSU(LS) {}
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bool hasWorkToComplete() const override { return !RCU.isEmpty(); }
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bool hasWorkToComplete() const override {
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return !RCU.isEmpty() || !RetireInst.empty();
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}
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Error cycleStart() override;
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Error execute(InstRef &IR) override;
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void notifyInstructionRetired(const InstRef &IR) const;
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@ -262,6 +262,10 @@ class ProcWriteResources<list<ProcResourceKind> resources> {
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// Allow a processor to mark some scheduling classes as single-issue.
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// SingleIssue is an alias for Begin/End Group.
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bit SingleIssue = false;
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// An instruction is allowed to retire out-of-order if RetireOOO is
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// true for at least one of its writes. This field is only used by
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// MCA for in-order subtargets, and is ignored for other targets.
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bit RetireOOO = false;
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SchedMachineModel SchedModel = ?;
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}
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@ -14,6 +14,7 @@ add_llvm_component_library(LLVMMCA
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Stages/DispatchStage.cpp
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Stages/EntryStage.cpp
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Stages/ExecuteStage.cpp
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Stages/InOrderIssueStage.cpp
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Stages/InstructionTables.cpp
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Stages/MicroOpQueueStage.cpp
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Stages/RetireStage.cpp
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@ -21,6 +21,7 @@
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#include "llvm/MCA/Stages/DispatchStage.h"
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#include "llvm/MCA/Stages/EntryStage.h"
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#include "llvm/MCA/Stages/ExecuteStage.h"
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#include "llvm/MCA/Stages/InOrderIssueStage.h"
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#include "llvm/MCA/Stages/MicroOpQueueStage.h"
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#include "llvm/MCA/Stages/RetireStage.h"
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@ -31,6 +32,9 @@ std::unique_ptr<Pipeline>
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Context::createDefaultPipeline(const PipelineOptions &Opts, SourceMgr &SrcMgr) {
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const MCSchedModel &SM = STI.getSchedModel();
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if (!SM.isOutOfOrder())
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return createInOrderPipeline(Opts, SrcMgr);
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// Create the hardware units defining the backend.
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auto RCU = std::make_unique<RetireControlUnit>(SM);
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auto PRF = std::make_unique<RegisterFile>(SM, MRI, Opts.RegisterFileSize);
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@ -64,5 +68,29 @@ Context::createDefaultPipeline(const PipelineOptions &Opts, SourceMgr &SrcMgr) {
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return StagePipeline;
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}
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std::unique_ptr<Pipeline>
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Context::createInOrderPipeline(const PipelineOptions &Opts, SourceMgr &SrcMgr) {
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const MCSchedModel &SM = STI.getSchedModel();
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auto RCU = std::make_unique<RetireControlUnit>(SM);
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auto PRF = std::make_unique<RegisterFile>(SM, MRI, Opts.RegisterFileSize);
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auto LSU = std::make_unique<LSUnit>(SM, Opts.LoadQueueSize,
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Opts.StoreQueueSize, Opts.AssumeNoAlias);
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auto Entry = std::make_unique<EntryStage>(SrcMgr);
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auto InOrderIssue = std::make_unique<InOrderIssueStage>(*RCU, *PRF, SM, STI);
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auto Retire = std::make_unique<RetireStage>(*RCU, *PRF, *LSU);
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auto StagePipeline = std::make_unique<Pipeline>();
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StagePipeline->appendStage(std::move(Entry));
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StagePipeline->appendStage(std::move(InOrderIssue));
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StagePipeline->appendStage(std::move(Retire));
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addHardwareUnit(std::move(RCU));
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addHardwareUnit(std::move(PRF));
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addHardwareUnit(std::move(LSU));
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return StagePipeline;
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}
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} // namespace mca
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} // namespace llvm
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@ -33,12 +33,18 @@ RetireControlUnit::RetireControlUnit(const MCSchedModel &SM)
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MaxRetirePerCycle = EPI.MaxRetirePerCycle;
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}
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NumROBEntries = AvailableEntries;
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bool IsOutOfOrder = SM.MicroOpBufferSize;
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if (!IsOutOfOrder && !NumROBEntries)
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return;
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assert(NumROBEntries && "Invalid reorder buffer size!");
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Queue.resize(2 * NumROBEntries);
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}
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// Reserves a number of slots, and returns a new token.
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unsigned RetireControlUnit::dispatch(const InstRef &IR) {
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if (!NumROBEntries)
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return UnhandledTokenID;
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const Instruction &Inst = *IR.getInstruction();
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unsigned Entries = normalizeQuantity(Inst.getNumMicroOps());
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assert((AvailableEntries >= Entries) && "Reorder Buffer unavailable!");
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@ -47,6 +53,7 @@ unsigned RetireControlUnit::dispatch(const InstRef &IR) {
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Queue[NextAvailableSlotIdx] = {IR, Entries, false};
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NextAvailableSlotIdx += std::max(1U, Entries);
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NextAvailableSlotIdx %= Queue.size();
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assert(TokenID < UnhandledTokenID && "Invalid token ID");
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AvailableEntries -= Entries;
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return TokenID;
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@ -570,6 +570,7 @@ InstrBuilder::createInstrDescImpl(const MCInst &MCI) {
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ID->HasSideEffects = MCDesc.hasUnmodeledSideEffects();
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ID->BeginGroup = SCDesc.BeginGroup;
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ID->EndGroup = SCDesc.EndGroup;
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ID->RetireOOO = SCDesc.RetireOOO;
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initializeUsedResources(*ID, SCDesc, STI, ProcResourceMasks);
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computeMaxLatency(*ID, MCDesc, SCDesc, STI);
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292
lib/MCA/Stages/InOrderIssueStage.cpp
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292
lib/MCA/Stages/InOrderIssueStage.cpp
Normal file
@ -0,0 +1,292 @@
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//===---------------------- InOrderIssueStage.cpp ---------------*- C++ -*-===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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/// \file
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///
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/// InOrderIssueStage implements an in-order execution pipeline.
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///
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//===----------------------------------------------------------------------===//
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#include "llvm/MCA/Stages/InOrderIssueStage.h"
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#include "llvm/MC/MCSchedule.h"
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#include "llvm/MCA/HWEventListener.h"
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#include "llvm/MCA/HardwareUnits/RegisterFile.h"
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#include "llvm/MCA/HardwareUnits/ResourceManager.h"
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#include "llvm/MCA/HardwareUnits/RetireControlUnit.h"
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#include "llvm/MCA/Instruction.h"
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#include "llvm/Support/Debug.h"
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#include "llvm/Support/Error.h"
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#include <algorithm>
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#define DEBUG_TYPE "llvm-mca"
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namespace llvm {
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namespace mca {
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bool InOrderIssueStage::hasWorkToComplete() const {
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return !IssuedInst.empty() || StalledInst;
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}
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bool InOrderIssueStage::isAvailable(const InstRef &IR) const {
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const Instruction &Inst = *IR.getInstruction();
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unsigned NumMicroOps = Inst.getNumMicroOps();
|
||||
const InstrDesc &Desc = Inst.getDesc();
|
||||
|
||||
if (Bandwidth < NumMicroOps)
|
||||
return false;
|
||||
|
||||
// Instruction with BeginGroup must be the first instruction to be issued in a
|
||||
// cycle.
|
||||
if (Desc.BeginGroup && NumIssued != 0)
|
||||
return false;
|
||||
|
||||
return true;
|
||||
}
|
||||
|
||||
static bool hasResourceHazard(const ResourceManager &RM, const InstRef &IR) {
|
||||
if (RM.checkAvailability(IR.getInstruction()->getDesc())) {
|
||||
LLVM_DEBUG(dbgs() << "[E] Stall #" << IR << '\n');
|
||||
return true;
|
||||
}
|
||||
|
||||
return false;
|
||||
}
|
||||
|
||||
/// Return a number of cycles left until register requirements of the
|
||||
/// instructions are met.
|
||||
static unsigned checkRegisterHazard(const RegisterFile &PRF,
|
||||
const MCSchedModel &SM,
|
||||
const MCSubtargetInfo &STI,
|
||||
const InstRef &IR) {
|
||||
unsigned StallCycles = 0;
|
||||
SmallVector<WriteRef, 4> Writes;
|
||||
|
||||
for (const ReadState &RS : IR.getInstruction()->getUses()) {
|
||||
const ReadDescriptor &RD = RS.getDescriptor();
|
||||
const MCSchedClassDesc *SC = SM.getSchedClassDesc(RD.SchedClassID);
|
||||
|
||||
PRF.collectWrites(RS, Writes);
|
||||
for (const WriteRef &WR : Writes) {
|
||||
const WriteState *WS = WR.getWriteState();
|
||||
unsigned WriteResID = WS->getWriteResourceID();
|
||||
int ReadAdvance = STI.getReadAdvanceCycles(SC, RD.UseIndex, WriteResID);
|
||||
LLVM_DEBUG(dbgs() << "[E] ReadAdvance for #" << IR << ": " << ReadAdvance
|
||||
<< '\n');
|
||||
|
||||
if (WS->getCyclesLeft() == UNKNOWN_CYCLES) {
|
||||
// Try again in the next cycle until the value is known
|
||||
StallCycles = std::max(StallCycles, 1U);
|
||||
continue;
|
||||
}
|
||||
|
||||
int CyclesLeft = WS->getCyclesLeft() - ReadAdvance;
|
||||
if (CyclesLeft > 0) {
|
||||
LLVM_DEBUG(dbgs() << "[E] Register hazard: " << WS->getRegisterID()
|
||||
<< '\n');
|
||||
StallCycles = std::max(StallCycles, (unsigned)CyclesLeft);
|
||||
}
|
||||
}
|
||||
Writes.clear();
|
||||
}
|
||||
|
||||
return StallCycles;
|
||||
}
|
||||
|
||||
bool InOrderIssueStage::canExecute(const InstRef &IR,
|
||||
unsigned *StallCycles) const {
|
||||
*StallCycles = 0;
|
||||
|
||||
if (unsigned RegStall = checkRegisterHazard(PRF, SM, STI, IR)) {
|
||||
*StallCycles = RegStall;
|
||||
// FIXME: add a parameter to HWStallEvent to indicate a number of cycles.
|
||||
for (unsigned I = 0; I < RegStall; ++I) {
|
||||
notifyEvent<HWStallEvent>(
|
||||
HWStallEvent(HWStallEvent::RegisterFileStall, IR));
|
||||
notifyEvent<HWPressureEvent>(
|
||||
HWPressureEvent(HWPressureEvent::REGISTER_DEPS, IR));
|
||||
}
|
||||
} else if (hasResourceHazard(*RM, IR)) {
|
||||
*StallCycles = 1;
|
||||
notifyEvent<HWStallEvent>(
|
||||
HWStallEvent(HWStallEvent::DispatchGroupStall, IR));
|
||||
notifyEvent<HWPressureEvent>(
|
||||
HWPressureEvent(HWPressureEvent::RESOURCES, IR));
|
||||
}
|
||||
|
||||
return *StallCycles == 0;
|
||||
}
|
||||
|
||||
static void addRegisterReadWrite(RegisterFile &PRF, Instruction &IS,
|
||||
unsigned SourceIndex,
|
||||
const MCSubtargetInfo &STI,
|
||||
SmallVectorImpl<unsigned> &UsedRegs) {
|
||||
assert(!IS.isEliminated());
|
||||
|
||||
for (ReadState &RS : IS.getUses())
|
||||
PRF.addRegisterRead(RS, STI);
|
||||
|
||||
for (WriteState &WS : IS.getDefs())
|
||||
PRF.addRegisterWrite(WriteRef(SourceIndex, &WS), UsedRegs);
|
||||
}
|
||||
|
||||
static void notifyInstructionExecute(
|
||||
const InstRef &IR,
|
||||
const SmallVectorImpl<std::pair<ResourceRef, ResourceCycles>> &UsedRes,
|
||||
const Stage &S) {
|
||||
|
||||
S.notifyEvent<HWInstructionEvent>(
|
||||
HWInstructionEvent(HWInstructionEvent::Ready, IR));
|
||||
S.notifyEvent<HWInstructionEvent>(HWInstructionIssuedEvent(IR, UsedRes));
|
||||
|
||||
LLVM_DEBUG(dbgs() << "[E] Issued #" << IR << "\n");
|
||||
}
|
||||
|
||||
static void notifyInstructionDispatch(const InstRef &IR, unsigned Ops,
|
||||
const SmallVectorImpl<unsigned> &UsedRegs,
|
||||
const Stage &S) {
|
||||
|
||||
S.notifyEvent<HWInstructionEvent>(
|
||||
HWInstructionDispatchedEvent(IR, UsedRegs, Ops));
|
||||
|
||||
LLVM_DEBUG(dbgs() << "[E] Dispatched #" << IR << "\n");
|
||||
}
|
||||
|
||||
llvm::Error InOrderIssueStage::execute(InstRef &IR) {
|
||||
Instruction &IS = *IR.getInstruction();
|
||||
const InstrDesc &Desc = IS.getDesc();
|
||||
|
||||
unsigned RCUTokenID = RetireControlUnit::UnhandledTokenID;
|
||||
if (!Desc.RetireOOO)
|
||||
RCUTokenID = RCU.dispatch(IR);
|
||||
IS.dispatch(RCUTokenID);
|
||||
|
||||
if (Desc.EndGroup) {
|
||||
Bandwidth = 0;
|
||||
} else {
|
||||
unsigned NumMicroOps = IR.getInstruction()->getNumMicroOps();
|
||||
assert(Bandwidth >= NumMicroOps);
|
||||
Bandwidth -= NumMicroOps;
|
||||
}
|
||||
|
||||
if (llvm::Error E = tryIssue(IR, &StallCyclesLeft))
|
||||
return E;
|
||||
|
||||
if (StallCyclesLeft) {
|
||||
StalledInst = IR;
|
||||
Bandwidth = 0;
|
||||
}
|
||||
|
||||
return llvm::ErrorSuccess();
|
||||
}
|
||||
|
||||
llvm::Error InOrderIssueStage::tryIssue(InstRef &IR, unsigned *StallCycles) {
|
||||
Instruction &IS = *IR.getInstruction();
|
||||
unsigned SourceIndex = IR.getSourceIndex();
|
||||
|
||||
if (!canExecute(IR, StallCycles)) {
|
||||
LLVM_DEBUG(dbgs() << "[E] Stalled #" << IR << " for " << *StallCycles
|
||||
<< " cycles\n");
|
||||
return llvm::ErrorSuccess();
|
||||
}
|
||||
|
||||
SmallVector<unsigned, 4> UsedRegs(PRF.getNumRegisterFiles());
|
||||
addRegisterReadWrite(PRF, IS, SourceIndex, STI, UsedRegs);
|
||||
|
||||
notifyInstructionDispatch(IR, IS.getDesc().NumMicroOps, UsedRegs, *this);
|
||||
|
||||
SmallVector<std::pair<ResourceRef, ResourceCycles>, 4> UsedResources;
|
||||
RM->issueInstruction(IS.getDesc(), UsedResources);
|
||||
IS.execute(SourceIndex);
|
||||
|
||||
// Replace resource masks with valid resource processor IDs.
|
||||
for (std::pair<ResourceRef, ResourceCycles> &Use : UsedResources) {
|
||||
uint64_t Mask = Use.first.first;
|
||||
Use.first.first = RM->resolveResourceMask(Mask);
|
||||
}
|
||||
notifyInstructionExecute(IR, UsedResources, *this);
|
||||
|
||||
IssuedInst.push_back(IR);
|
||||
++NumIssued;
|
||||
|
||||
return llvm::ErrorSuccess();
|
||||
}
|
||||
|
||||
llvm::Error InOrderIssueStage::updateIssuedInst() {
|
||||
// Update other instructions. Executed instructions will be retired during the
|
||||
// next cycle.
|
||||
unsigned NumExecuted = 0;
|
||||
for (auto I = IssuedInst.begin(), E = IssuedInst.end();
|
||||
I != (E - NumExecuted);) {
|
||||
InstRef &IR = *I;
|
||||
Instruction &IS = *IR.getInstruction();
|
||||
|
||||
IS.cycleEvent();
|
||||
if (!IS.isExecuted()) {
|
||||
LLVM_DEBUG(dbgs() << "[E] Instruction #" << IR
|
||||
<< " is still executing\n");
|
||||
++I;
|
||||
continue;
|
||||
}
|
||||
notifyEvent<HWInstructionEvent>(
|
||||
HWInstructionEvent(HWInstructionEvent::Executed, IR));
|
||||
|
||||
LLVM_DEBUG(dbgs() << "[E] Instruction #" << IR << " is executed\n");
|
||||
++NumExecuted;
|
||||
std::iter_swap(I, E - NumExecuted);
|
||||
}
|
||||
|
||||
// Retire instructions in the next cycle
|
||||
if (NumExecuted) {
|
||||
for (auto I = IssuedInst.end() - NumExecuted, E = IssuedInst.end(); I != E;
|
||||
++I) {
|
||||
if (llvm::Error E = moveToTheNextStage(*I))
|
||||
return E;
|
||||
}
|
||||
IssuedInst.resize(IssuedInst.size() - NumExecuted);
|
||||
}
|
||||
|
||||
return llvm::ErrorSuccess();
|
||||
}
|
||||
|
||||
llvm::Error InOrderIssueStage::cycleStart() {
|
||||
NumIssued = 0;
|
||||
|
||||
// Release consumed resources.
|
||||
SmallVector<ResourceRef, 4> Freed;
|
||||
RM->cycleEvent(Freed);
|
||||
|
||||
if (llvm::Error E = updateIssuedInst())
|
||||
return E;
|
||||
|
||||
// Issue instructions scheduled for this cycle
|
||||
if (!StallCyclesLeft && StalledInst) {
|
||||
if (llvm::Error E = tryIssue(StalledInst, &StallCyclesLeft))
|
||||
return E;
|
||||
}
|
||||
|
||||
if (!StallCyclesLeft) {
|
||||
StalledInst.invalidate();
|
||||
assert(NumIssued <= SM.IssueWidth && "Overflow.");
|
||||
Bandwidth = SM.IssueWidth - NumIssued;
|
||||
} else {
|
||||
// The instruction is still stalled, cannot issue any new instructions in
|
||||
// this cycle.
|
||||
Bandwidth = 0;
|
||||
}
|
||||
|
||||
return llvm::ErrorSuccess();
|
||||
}
|
||||
|
||||
llvm::Error InOrderIssueStage::cycleEnd() {
|
||||
if (StallCyclesLeft > 0)
|
||||
--StallCyclesLeft;
|
||||
return llvm::ErrorSuccess();
|
||||
}
|
||||
|
||||
} // namespace mca
|
||||
} // namespace llvm
|
||||
@ -23,9 +23,6 @@ namespace llvm {
|
||||
namespace mca {
|
||||
|
||||
llvm::Error RetireStage::cycleStart() {
|
||||
if (RCU.isEmpty())
|
||||
return llvm::ErrorSuccess();
|
||||
|
||||
const unsigned MaxRetirePerCycle = RCU.getMaxRetirePerCycle();
|
||||
unsigned NumRetired = 0;
|
||||
while (!RCU.isEmpty()) {
|
||||
@ -39,11 +36,26 @@ llvm::Error RetireStage::cycleStart() {
|
||||
NumRetired++;
|
||||
}
|
||||
|
||||
// Retire instructions that are not controlled by the RCU
|
||||
for (InstRef &IR : RetireInst) {
|
||||
IR.getInstruction()->retire();
|
||||
notifyInstructionRetired(IR);
|
||||
}
|
||||
RetireInst.resize(0);
|
||||
|
||||
return llvm::ErrorSuccess();
|
||||
}
|
||||
|
||||
llvm::Error RetireStage::execute(InstRef &IR) {
|
||||
RCU.onInstructionExecuted(IR.getInstruction()->getRCUTokenID());
|
||||
Instruction &IS = *IR.getInstruction();
|
||||
|
||||
unsigned TokenID = IS.getRCUTokenID();
|
||||
if (TokenID != RetireControlUnit::UnhandledTokenID) {
|
||||
RCU.onInstructionExecuted(TokenID);
|
||||
return llvm::ErrorSuccess();
|
||||
}
|
||||
|
||||
RetireInst.push_back(IR);
|
||||
return llvm::ErrorSuccess();
|
||||
}
|
||||
|
||||
|
||||
@ -151,6 +151,8 @@ def CortexA55WriteFPALU_F5 : SchedWriteRes<[CortexA55UnitFPALU]> { let Latency =
|
||||
|
||||
// FP Mul, Div, Sqrt. Div/Sqrt are not pipelined
|
||||
def : WriteRes<WriteFMul, [CortexA55UnitFPMAC]> { let Latency = 4; }
|
||||
|
||||
let RetireOOO = 1 in {
|
||||
def : WriteRes<WriteFDiv, [CortexA55UnitFPDIV]> { let Latency = 22;
|
||||
let ResourceCycles = [29]; }
|
||||
def CortexA55WriteFMAC : SchedWriteRes<[CortexA55UnitFPMAC]> { let Latency = 4; }
|
||||
@ -166,7 +168,7 @@ def CortexA55WriteFSqrtSP : SchedWriteRes<[CortexA55UnitFPDIV]> { let Latency =
|
||||
let ResourceCycles = [9]; }
|
||||
def CortexA55WriteFSqrtDP : SchedWriteRes<[CortexA55UnitFPDIV]> { let Latency = 22;
|
||||
let ResourceCycles = [19]; }
|
||||
|
||||
}
|
||||
//===----------------------------------------------------------------------===//
|
||||
// Subtarget-specific SchedRead types.
|
||||
|
||||
@ -336,4 +338,6 @@ def : InstRW<[CortexA55WriteFDivDP], (instregex "^FDIVv.*64$")>;
|
||||
def : InstRW<[CortexA55WriteFSqrtHP], (instregex "^.*SQRT.*16$")>;
|
||||
def : InstRW<[CortexA55WriteFSqrtSP], (instregex "^.*SQRT.*32$")>;
|
||||
def : InstRW<[CortexA55WriteFSqrtDP], (instregex "^.*SQRT.*64$")>;
|
||||
|
||||
def A55RCU : RetireControlUnit<64, 0>;
|
||||
}
|
||||
|
||||
@ -19,7 +19,7 @@ let CompleteModel = 0 in {
|
||||
// Inst_B didn't have the resoures, and it is invalid.
|
||||
// CHECK: SchedModel_ASchedClasses[] = {
|
||||
// CHECK: {DBGFIELD("Inst_A") 1
|
||||
// CHECK-NEXT: {DBGFIELD("Inst_B") 16383
|
||||
// CHECK-NEXT: {DBGFIELD("Inst_B") 8191
|
||||
let SchedModel = SchedModel_A in {
|
||||
def Write_A : SchedWriteRes<[]>;
|
||||
def : InstRW<[Write_A], (instrs Inst_A)>;
|
||||
@ -27,7 +27,7 @@ let SchedModel = SchedModel_A in {
|
||||
|
||||
// Inst_A didn't have the resoures, and it is invalid.
|
||||
// CHECK: SchedModel_BSchedClasses[] = {
|
||||
// CHECK: {DBGFIELD("Inst_A") 16383
|
||||
// CHECK: {DBGFIELD("Inst_A") 8191
|
||||
// CHECK-NEXT: {DBGFIELD("Inst_B") 1
|
||||
let SchedModel = SchedModel_B in {
|
||||
def Write_B: SchedWriteRes<[]>;
|
||||
|
||||
81
test/tools/llvm-mca/AArch64/Cortex/A55-add-sequence.s
Normal file
81
test/tools/llvm-mca/AArch64/Cortex/A55-add-sequence.s
Normal file
@ -0,0 +1,81 @@
|
||||
# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
|
||||
# RUN: llvm-mca -mtriple=aarch64 -mcpu=cortex-a55 --timeline --iterations=2 < %s | FileCheck %s
|
||||
|
||||
add w2, w3, #1
|
||||
add w4, w3, #2, lsl #12
|
||||
add w0, w4, #3
|
||||
add w1, w0, #4
|
||||
|
||||
# CHECK: Iterations: 2
|
||||
# CHECK-NEXT: Instructions: 8
|
||||
# CHECK-NEXT: Total Cycles: 10
|
||||
# CHECK-NEXT: Total uOps: 8
|
||||
|
||||
# CHECK: Dispatch Width: 2
|
||||
# CHECK-NEXT: uOps Per Cycle: 0.80
|
||||
# CHECK-NEXT: IPC: 0.80
|
||||
# CHECK-NEXT: Block RThroughput: 2.0
|
||||
|
||||
# CHECK: Instruction Info:
|
||||
# CHECK-NEXT: [1]: #uOps
|
||||
# CHECK-NEXT: [2]: Latency
|
||||
# CHECK-NEXT: [3]: RThroughput
|
||||
# CHECK-NEXT: [4]: MayLoad
|
||||
# CHECK-NEXT: [5]: MayStore
|
||||
# CHECK-NEXT: [6]: HasSideEffects (U)
|
||||
|
||||
# CHECK: [1] [2] [3] [4] [5] [6] Instructions:
|
||||
# CHECK-NEXT: 1 3 0.50 add w2, w3, #1
|
||||
# CHECK-NEXT: 1 3 0.50 add w4, w3, #2, lsl #12
|
||||
# CHECK-NEXT: 1 3 0.50 add w0, w4, #3
|
||||
# CHECK-NEXT: 1 3 0.50 add w1, w0, #4
|
||||
|
||||
# CHECK: Resources:
|
||||
# CHECK-NEXT: [0.0] - CortexA55UnitALU
|
||||
# CHECK-NEXT: [0.1] - CortexA55UnitALU
|
||||
# CHECK-NEXT: [1] - CortexA55UnitB
|
||||
# CHECK-NEXT: [2] - CortexA55UnitDiv
|
||||
# CHECK-NEXT: [3.0] - CortexA55UnitFPALU
|
||||
# CHECK-NEXT: [3.1] - CortexA55UnitFPALU
|
||||
# CHECK-NEXT: [4] - CortexA55UnitFPDIV
|
||||
# CHECK-NEXT: [5.0] - CortexA55UnitFPMAC
|
||||
# CHECK-NEXT: [5.1] - CortexA55UnitFPMAC
|
||||
# CHECK-NEXT: [6] - CortexA55UnitLd
|
||||
# CHECK-NEXT: [7] - CortexA55UnitMAC
|
||||
# CHECK-NEXT: [8] - CortexA55UnitSt
|
||||
|
||||
# CHECK: Resource pressure per iteration:
|
||||
# CHECK-NEXT: [0.0] [0.1] [1] [2] [3.0] [3.1] [4] [5.0] [5.1] [6] [7] [8]
|
||||
# CHECK-NEXT: 2.00 2.00 - - - - - - - - - -
|
||||
|
||||
# CHECK: Resource pressure by instruction:
|
||||
# CHECK-NEXT: [0.0] [0.1] [1] [2] [3.0] [3.1] [4] [5.0] [5.1] [6] [7] [8] Instructions:
|
||||
# CHECK-NEXT: - 1.00 - - - - - - - - - - add w2, w3, #1
|
||||
# CHECK-NEXT: 1.00 - - - - - - - - - - - add w4, w3, #2, lsl #12
|
||||
# CHECK-NEXT: - 1.00 - - - - - - - - - - add w0, w4, #3
|
||||
# CHECK-NEXT: 1.00 - - - - - - - - - - - add w1, w0, #4
|
||||
|
||||
# CHECK: Timeline view:
|
||||
# CHECK-NEXT: Index 0123456789
|
||||
|
||||
# CHECK: [0,0] DeeER. . add w2, w3, #1
|
||||
# CHECK-NEXT: [0,1] DeeER. . add w4, w3, #2, lsl #12
|
||||
# CHECK-NEXT: [0,2] .DeeER . add w0, w4, #3
|
||||
# CHECK-NEXT: [0,3] . DeeER . add w1, w0, #4
|
||||
# CHECK-NEXT: [1,0] . DeeER . add w2, w3, #1
|
||||
# CHECK-NEXT: [1,1] . DeeER . add w4, w3, #2, lsl #12
|
||||
# CHECK-NEXT: [1,2] . DeeER. add w0, w4, #3
|
||||
# CHECK-NEXT: [1,3] . DeeER add w1, w0, #4
|
||||
|
||||
# CHECK: Average Wait times (based on the timeline view):
|
||||
# CHECK-NEXT: [0]: Executions
|
||||
# CHECK-NEXT: [1]: Average time spent waiting in a scheduler's queue
|
||||
# CHECK-NEXT: [2]: Average time spent waiting in a scheduler's queue while ready
|
||||
# CHECK-NEXT: [3]: Average time elapsed from WB until retire stage
|
||||
|
||||
# CHECK: [0] [1] [2] [3]
|
||||
# CHECK-NEXT: 0. 2 0.0 0.0 0.0 add w2, w3, #1
|
||||
# CHECK-NEXT: 1. 2 0.0 0.0 0.0 add w4, w3, #2, lsl #12
|
||||
# CHECK-NEXT: 2. 2 0.0 0.0 0.0 add w0, w4, #3
|
||||
# CHECK-NEXT: 3. 2 0.0 0.0 0.0 add w1, w0, #4
|
||||
# CHECK-NEXT: 2 0.0 0.0 0.0 <total>
|
||||
100
test/tools/llvm-mca/AArch64/Cortex/A55-all-stats.s
Normal file
100
test/tools/llvm-mca/AArch64/Cortex/A55-all-stats.s
Normal file
@ -0,0 +1,100 @@
|
||||
# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
|
||||
# RUN: llvm-mca -mtriple=aarch64 -mcpu=cortex-a55 --all-stats --iterations=2 < %s | FileCheck %s
|
||||
|
||||
ldr w4, [x2], #4
|
||||
ldr w5, [x3]
|
||||
madd w0, w5, w4, w0
|
||||
add x3, x3, x13
|
||||
subs x1, x1, #1
|
||||
str w0, [x21, x18, lsl #2]
|
||||
|
||||
# CHECK: Iterations: 2
|
||||
# CHECK-NEXT: Instructions: 12
|
||||
# CHECK-NEXT: Total Cycles: 21
|
||||
# CHECK-NEXT: Total uOps: 14
|
||||
|
||||
# CHECK: Dispatch Width: 2
|
||||
# CHECK-NEXT: uOps Per Cycle: 0.67
|
||||
# CHECK-NEXT: IPC: 0.57
|
||||
# CHECK-NEXT: Block RThroughput: 3.5
|
||||
|
||||
# CHECK: Instruction Info:
|
||||
# CHECK-NEXT: [1]: #uOps
|
||||
# CHECK-NEXT: [2]: Latency
|
||||
# CHECK-NEXT: [3]: RThroughput
|
||||
# CHECK-NEXT: [4]: MayLoad
|
||||
# CHECK-NEXT: [5]: MayStore
|
||||
# CHECK-NEXT: [6]: HasSideEffects (U)
|
||||
|
||||
# CHECK: [1] [2] [3] [4] [5] [6] Instructions:
|
||||
# CHECK-NEXT: 2 3 1.00 * ldr w4, [x2], #4
|
||||
# CHECK-NEXT: 1 3 1.00 * ldr w5, [x3]
|
||||
# CHECK-NEXT: 1 4 1.00 madd w0, w5, w4, w0
|
||||
# CHECK-NEXT: 1 3 0.50 add x3, x3, x13
|
||||
# CHECK-NEXT: 1 3 0.50 subs x1, x1, #1
|
||||
# CHECK-NEXT: 1 4 1.00 * str w0, [x21, x18, lsl #2]
|
||||
|
||||
# CHECK: Dynamic Dispatch Stall Cycles:
|
||||
# CHECK-NEXT: RAT - Register unavailable: 10 (47.6%)
|
||||
# CHECK-NEXT: RCU - Retire tokens unavailable: 0
|
||||
# CHECK-NEXT: SCHEDQ - Scheduler full: 0
|
||||
# CHECK-NEXT: LQ - Load queue full: 0
|
||||
# CHECK-NEXT: SQ - Store queue full: 0
|
||||
# CHECK-NEXT: GROUP - Static restrictions on the dispatch group: 0
|
||||
|
||||
# CHECK: Dispatch Logic - number of cycles where we saw N micro opcodes dispatched:
|
||||
# CHECK-NEXT: [# dispatched], [# cycles]
|
||||
# CHECK-NEXT: 0, 11 (52.4%)
|
||||
# CHECK-NEXT: 1, 6 (28.6%)
|
||||
# CHECK-NEXT: 2, 4 (19.0%)
|
||||
|
||||
# CHECK: Schedulers - number of cycles where we saw N micro opcodes issued:
|
||||
# CHECK-NEXT: [# issued], [# cycles]
|
||||
# CHECK-NEXT: 0, 11 (52.4%)
|
||||
# CHECK-NEXT: 1, 6 (28.6%)
|
||||
# CHECK-NEXT: 2, 4 (19.0%)
|
||||
|
||||
# CHECK: Scheduler's queue usage:
|
||||
# CHECK-NEXT: No scheduler resources used.
|
||||
|
||||
# CHECK: Retire Control Unit - number of cycles where we saw N instructions retired:
|
||||
# CHECK-NEXT: [# retired], [# cycles]
|
||||
# CHECK-NEXT: 0, 14 (66.7%)
|
||||
# CHECK-NEXT: 1, 4 (19.0%)
|
||||
# CHECK-NEXT: 2, 1 (4.8%)
|
||||
# CHECK-NEXT: 3, 2 (9.5%)
|
||||
|
||||
# CHECK: Total ROB Entries: 64
|
||||
# CHECK-NEXT: Max Used ROB Entries: 6 ( 9.4% )
|
||||
# CHECK-NEXT: Average Used ROB Entries per cy: 2 ( 3.1% )
|
||||
|
||||
# CHECK: Register File statistics:
|
||||
# CHECK-NEXT: Total number of mappings created: 14
|
||||
# CHECK-NEXT: Max number of mappings used: 6
|
||||
|
||||
# CHECK: Resources:
|
||||
# CHECK-NEXT: [0.0] - CortexA55UnitALU
|
||||
# CHECK-NEXT: [0.1] - CortexA55UnitALU
|
||||
# CHECK-NEXT: [1] - CortexA55UnitB
|
||||
# CHECK-NEXT: [2] - CortexA55UnitDiv
|
||||
# CHECK-NEXT: [3.0] - CortexA55UnitFPALU
|
||||
# CHECK-NEXT: [3.1] - CortexA55UnitFPALU
|
||||
# CHECK-NEXT: [4] - CortexA55UnitFPDIV
|
||||
# CHECK-NEXT: [5.0] - CortexA55UnitFPMAC
|
||||
# CHECK-NEXT: [5.1] - CortexA55UnitFPMAC
|
||||
# CHECK-NEXT: [6] - CortexA55UnitLd
|
||||
# CHECK-NEXT: [7] - CortexA55UnitMAC
|
||||
# CHECK-NEXT: [8] - CortexA55UnitSt
|
||||
|
||||
# CHECK: Resource pressure per iteration:
|
||||
# CHECK-NEXT: [0.0] [0.1] [1] [2] [3.0] [3.1] [4] [5.0] [5.1] [6] [7] [8]
|
||||
# CHECK-NEXT: 1.00 1.00 - - - - - - - 2.00 1.00 1.00
|
||||
|
||||
# CHECK: Resource pressure by instruction:
|
||||
# CHECK-NEXT: [0.0] [0.1] [1] [2] [3.0] [3.1] [4] [5.0] [5.1] [6] [7] [8] Instructions:
|
||||
# CHECK-NEXT: - - - - - - - - - 1.00 - - ldr w4, [x2], #4
|
||||
# CHECK-NEXT: - - - - - - - - - 1.00 - - ldr w5, [x3]
|
||||
# CHECK-NEXT: - - - - - - - - - - 1.00 - madd w0, w5, w4, w0
|
||||
# CHECK-NEXT: - 1.00 - - - - - - - - - - add x3, x3, x13
|
||||
# CHECK-NEXT: 1.00 - - - - - - - - - - - subs x1, x1, #1
|
||||
# CHECK-NEXT: - - - - - - - - - - - 1.00 str w0, [x21, x18, lsl #2]
|
||||
132
test/tools/llvm-mca/AArch64/Cortex/A55-all-views.s
Normal file
132
test/tools/llvm-mca/AArch64/Cortex/A55-all-views.s
Normal file
@ -0,0 +1,132 @@
|
||||
# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
|
||||
# RUN: llvm-mca -mtriple=aarch64 -mcpu=cortex-a55 --all-views --iterations=2 < %s | FileCheck %s
|
||||
|
||||
ldr w4, [x2], #4
|
||||
ldr w5, [x3]
|
||||
madd w0, w5, w4, w0
|
||||
add x3, x3, x13
|
||||
subs x1, x1, #1
|
||||
str w0, [x21, x18, lsl #2]
|
||||
|
||||
# CHECK: Iterations: 2
|
||||
# CHECK-NEXT: Instructions: 12
|
||||
# CHECK-NEXT: Total Cycles: 21
|
||||
# CHECK-NEXT: Total uOps: 14
|
||||
|
||||
# CHECK: Dispatch Width: 2
|
||||
# CHECK-NEXT: uOps Per Cycle: 0.67
|
||||
# CHECK-NEXT: IPC: 0.57
|
||||
# CHECK-NEXT: Block RThroughput: 3.5
|
||||
|
||||
# CHECK: Instruction Info:
|
||||
# CHECK-NEXT: [1]: #uOps
|
||||
# CHECK-NEXT: [2]: Latency
|
||||
# CHECK-NEXT: [3]: RThroughput
|
||||
# CHECK-NEXT: [4]: MayLoad
|
||||
# CHECK-NEXT: [5]: MayStore
|
||||
# CHECK-NEXT: [6]: HasSideEffects (U)
|
||||
|
||||
# CHECK: [1] [2] [3] [4] [5] [6] Instructions:
|
||||
# CHECK-NEXT: 2 3 1.00 * ldr w4, [x2], #4
|
||||
# CHECK-NEXT: 1 3 1.00 * ldr w5, [x3]
|
||||
# CHECK-NEXT: 1 4 1.00 madd w0, w5, w4, w0
|
||||
# CHECK-NEXT: 1 3 0.50 add x3, x3, x13
|
||||
# CHECK-NEXT: 1 3 0.50 subs x1, x1, #1
|
||||
# CHECK-NEXT: 1 4 1.00 * str w0, [x21, x18, lsl #2]
|
||||
|
||||
# CHECK: Dynamic Dispatch Stall Cycles:
|
||||
# CHECK-NEXT: RAT - Register unavailable: 10 (47.6%)
|
||||
# CHECK-NEXT: RCU - Retire tokens unavailable: 0
|
||||
# CHECK-NEXT: SCHEDQ - Scheduler full: 0
|
||||
# CHECK-NEXT: LQ - Load queue full: 0
|
||||
# CHECK-NEXT: SQ - Store queue full: 0
|
||||
# CHECK-NEXT: GROUP - Static restrictions on the dispatch group: 0
|
||||
|
||||
# CHECK: Dispatch Logic - number of cycles where we saw N micro opcodes dispatched:
|
||||
# CHECK-NEXT: [# dispatched], [# cycles]
|
||||
# CHECK-NEXT: 0, 11 (52.4%)
|
||||
# CHECK-NEXT: 1, 6 (28.6%)
|
||||
# CHECK-NEXT: 2, 4 (19.0%)
|
||||
|
||||
# CHECK: Schedulers - number of cycles where we saw N micro opcodes issued:
|
||||
# CHECK-NEXT: [# issued], [# cycles]
|
||||
# CHECK-NEXT: 0, 11 (52.4%)
|
||||
# CHECK-NEXT: 1, 6 (28.6%)
|
||||
# CHECK-NEXT: 2, 4 (19.0%)
|
||||
|
||||
# CHECK: Scheduler's queue usage:
|
||||
# CHECK-NEXT: No scheduler resources used.
|
||||
|
||||
# CHECK: Retire Control Unit - number of cycles where we saw N instructions retired:
|
||||
# CHECK-NEXT: [# retired], [# cycles]
|
||||
# CHECK-NEXT: 0, 14 (66.7%)
|
||||
# CHECK-NEXT: 1, 4 (19.0%)
|
||||
# CHECK-NEXT: 2, 1 (4.8%)
|
||||
# CHECK-NEXT: 3, 2 (9.5%)
|
||||
|
||||
# CHECK: Total ROB Entries: 64
|
||||
# CHECK-NEXT: Max Used ROB Entries: 6 ( 9.4% )
|
||||
# CHECK-NEXT: Average Used ROB Entries per cy: 2 ( 3.1% )
|
||||
|
||||
# CHECK: Register File statistics:
|
||||
# CHECK-NEXT: Total number of mappings created: 14
|
||||
# CHECK-NEXT: Max number of mappings used: 6
|
||||
|
||||
# CHECK: Resources:
|
||||
# CHECK-NEXT: [0.0] - CortexA55UnitALU
|
||||
# CHECK-NEXT: [0.1] - CortexA55UnitALU
|
||||
# CHECK-NEXT: [1] - CortexA55UnitB
|
||||
# CHECK-NEXT: [2] - CortexA55UnitDiv
|
||||
# CHECK-NEXT: [3.0] - CortexA55UnitFPALU
|
||||
# CHECK-NEXT: [3.1] - CortexA55UnitFPALU
|
||||
# CHECK-NEXT: [4] - CortexA55UnitFPDIV
|
||||
# CHECK-NEXT: [5.0] - CortexA55UnitFPMAC
|
||||
# CHECK-NEXT: [5.1] - CortexA55UnitFPMAC
|
||||
# CHECK-NEXT: [6] - CortexA55UnitLd
|
||||
# CHECK-NEXT: [7] - CortexA55UnitMAC
|
||||
# CHECK-NEXT: [8] - CortexA55UnitSt
|
||||
|
||||
# CHECK: Resource pressure per iteration:
|
||||
# CHECK-NEXT: [0.0] [0.1] [1] [2] [3.0] [3.1] [4] [5.0] [5.1] [6] [7] [8]
|
||||
# CHECK-NEXT: 1.00 1.00 - - - - - - - 2.00 1.00 1.00
|
||||
|
||||
# CHECK: Resource pressure by instruction:
|
||||
# CHECK-NEXT: [0.0] [0.1] [1] [2] [3.0] [3.1] [4] [5.0] [5.1] [6] [7] [8] Instructions:
|
||||
# CHECK-NEXT: - - - - - - - - - 1.00 - - ldr w4, [x2], #4
|
||||
# CHECK-NEXT: - - - - - - - - - 1.00 - - ldr w5, [x3]
|
||||
# CHECK-NEXT: - - - - - - - - - - 1.00 - madd w0, w5, w4, w0
|
||||
# CHECK-NEXT: - 1.00 - - - - - - - - - - add x3, x3, x13
|
||||
# CHECK-NEXT: 1.00 - - - - - - - - - - - subs x1, x1, #1
|
||||
# CHECK-NEXT: - - - - - - - - - - - 1.00 str w0, [x21, x18, lsl #2]
|
||||
|
||||
# CHECK: Timeline view:
|
||||
# CHECK-NEXT: 0123456789
|
||||
# CHECK-NEXT: Index 0123456789 0
|
||||
|
||||
# CHECK: [0,0] DeeER. . . . ldr w4, [x2], #4
|
||||
# CHECK-NEXT: [0,1] .DeeER . . . ldr w5, [x3]
|
||||
# CHECK-NEXT: [0,2] . DeeeER. . . madd w0, w5, w4, w0
|
||||
# CHECK-NEXT: [0,3] . DeeE-R. . . add x3, x3, x13
|
||||
# CHECK-NEXT: [0,4] . DeeER. . . subs x1, x1, #1
|
||||
# CHECK-NEXT: [0,5] . . DeeeER . . str w0, [x21, x18, lsl #2]
|
||||
# CHECK-NEXT: [1,0] . . DeeER . . ldr w4, [x2], #4
|
||||
# CHECK-NEXT: [1,1] . . DeeER . . ldr w5, [x3]
|
||||
# CHECK-NEXT: [1,2] . . . DeeeER . madd w0, w5, w4, w0
|
||||
# CHECK-NEXT: [1,3] . . . DeeE-R . add x3, x3, x13
|
||||
# CHECK-NEXT: [1,4] . . . DeeER . subs x1, x1, #1
|
||||
# CHECK-NEXT: [1,5] . . . DeeeER str w0, [x21, x18, lsl #2]
|
||||
|
||||
# CHECK: Average Wait times (based on the timeline view):
|
||||
# CHECK-NEXT: [0]: Executions
|
||||
# CHECK-NEXT: [1]: Average time spent waiting in a scheduler's queue
|
||||
# CHECK-NEXT: [2]: Average time spent waiting in a scheduler's queue while ready
|
||||
# CHECK-NEXT: [3]: Average time elapsed from WB until retire stage
|
||||
|
||||
# CHECK: [0] [1] [2] [3]
|
||||
# CHECK-NEXT: 0. 2 0.0 0.0 0.0 ldr w4, [x2], #4
|
||||
# CHECK-NEXT: 1. 2 0.0 0.0 0.0 ldr w5, [x3]
|
||||
# CHECK-NEXT: 2. 2 0.0 0.0 0.0 madd w0, w5, w4, w0
|
||||
# CHECK-NEXT: 3. 2 0.0 0.0 1.0 add x3, x3, x13
|
||||
# CHECK-NEXT: 4. 2 0.0 0.0 0.0 subs x1, x1, #1
|
||||
# CHECK-NEXT: 5. 2 0.0 0.0 0.0 str w0, [x21, x18, lsl #2]
|
||||
# CHECK-NEXT: 2 0.0 0.0 0.2 <total>
|
||||
128
test/tools/llvm-mca/AArch64/Cortex/A55-in-order-retire.s
Normal file
128
test/tools/llvm-mca/AArch64/Cortex/A55-in-order-retire.s
Normal file
@ -0,0 +1,128 @@
|
||||
# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
|
||||
# RUN: llvm-mca -mtriple=aarch64 -mcpu=cortex-a55 --all-stats --all-views --iterations=2 < %s | FileCheck %s
|
||||
|
||||
sdiv w12, w21, w0
|
||||
add w8, w8, #1
|
||||
add w1, w2, w0
|
||||
add w3, w4, #1
|
||||
add w5, w6, w0
|
||||
add w7, w9, w0
|
||||
|
||||
# CHECK: Iterations: 2
|
||||
# CHECK-NEXT: Instructions: 12
|
||||
# CHECK-NEXT: Total Cycles: 18
|
||||
# CHECK-NEXT: Total uOps: 12
|
||||
|
||||
# CHECK: Dispatch Width: 2
|
||||
# CHECK-NEXT: uOps Per Cycle: 0.67
|
||||
# CHECK-NEXT: IPC: 0.67
|
||||
# CHECK-NEXT: Block RThroughput: 8.0
|
||||
|
||||
# CHECK: Instruction Info:
|
||||
# CHECK-NEXT: [1]: #uOps
|
||||
# CHECK-NEXT: [2]: Latency
|
||||
# CHECK-NEXT: [3]: RThroughput
|
||||
# CHECK-NEXT: [4]: MayLoad
|
||||
# CHECK-NEXT: [5]: MayStore
|
||||
# CHECK-NEXT: [6]: HasSideEffects (U)
|
||||
|
||||
# CHECK: [1] [2] [3] [4] [5] [6] Instructions:
|
||||
# CHECK-NEXT: 1 8 8.00 sdiv w12, w21, w0
|
||||
# CHECK-NEXT: 1 3 0.50 add w8, w8, #1
|
||||
# CHECK-NEXT: 1 3 0.50 add w1, w2, w0
|
||||
# CHECK-NEXT: 1 3 0.50 add w3, w4, #1
|
||||
# CHECK-NEXT: 1 3 0.50 add w5, w6, w0
|
||||
# CHECK-NEXT: 1 3 0.50 add w7, w9, w0
|
||||
|
||||
# CHECK: Dynamic Dispatch Stall Cycles:
|
||||
# CHECK-NEXT: RAT - Register unavailable: 0
|
||||
# CHECK-NEXT: RCU - Retire tokens unavailable: 0
|
||||
# CHECK-NEXT: SCHEDQ - Scheduler full: 0
|
||||
# CHECK-NEXT: LQ - Load queue full: 0
|
||||
# CHECK-NEXT: SQ - Store queue full: 0
|
||||
# CHECK-NEXT: GROUP - Static restrictions on the dispatch group: 5 (27.8%)
|
||||
|
||||
# CHECK: Dispatch Logic - number of cycles where we saw N micro opcodes dispatched:
|
||||
# CHECK-NEXT: [# dispatched], [# cycles]
|
||||
# CHECK-NEXT: 0, 12 (66.7%)
|
||||
# CHECK-NEXT: 2, 6 (33.3%)
|
||||
|
||||
# CHECK: Schedulers - number of cycles where we saw N micro opcodes issued:
|
||||
# CHECK-NEXT: [# issued], [# cycles]
|
||||
# CHECK-NEXT: 0, 12 (66.7%)
|
||||
# CHECK-NEXT: 2, 6 (33.3%)
|
||||
|
||||
# CHECK: Scheduler's queue usage:
|
||||
# CHECK-NEXT: No scheduler resources used.
|
||||
|
||||
# CHECK: Retire Control Unit - number of cycles where we saw N instructions retired:
|
||||
# CHECK-NEXT: [# retired], [# cycles]
|
||||
# CHECK-NEXT: 0, 16 (88.9%)
|
||||
# CHECK-NEXT: 6, 2 (11.1%)
|
||||
|
||||
# CHECK: Total ROB Entries: 64
|
||||
# CHECK-NEXT: Max Used ROB Entries: 8 ( 12.5% )
|
||||
# CHECK-NEXT: Average Used ROB Entries per cy: 5 ( 7.8% )
|
||||
|
||||
# CHECK: Register File statistics:
|
||||
# CHECK-NEXT: Total number of mappings created: 12
|
||||
# CHECK-NEXT: Max number of mappings used: 8
|
||||
|
||||
# CHECK: Resources:
|
||||
# CHECK-NEXT: [0.0] - CortexA55UnitALU
|
||||
# CHECK-NEXT: [0.1] - CortexA55UnitALU
|
||||
# CHECK-NEXT: [1] - CortexA55UnitB
|
||||
# CHECK-NEXT: [2] - CortexA55UnitDiv
|
||||
# CHECK-NEXT: [3.0] - CortexA55UnitFPALU
|
||||
# CHECK-NEXT: [3.1] - CortexA55UnitFPALU
|
||||
# CHECK-NEXT: [4] - CortexA55UnitFPDIV
|
||||
# CHECK-NEXT: [5.0] - CortexA55UnitFPMAC
|
||||
# CHECK-NEXT: [5.1] - CortexA55UnitFPMAC
|
||||
# CHECK-NEXT: [6] - CortexA55UnitLd
|
||||
# CHECK-NEXT: [7] - CortexA55UnitMAC
|
||||
# CHECK-NEXT: [8] - CortexA55UnitSt
|
||||
|
||||
# CHECK: Resource pressure per iteration:
|
||||
# CHECK-NEXT: [0.0] [0.1] [1] [2] [3.0] [3.1] [4] [5.0] [5.1] [6] [7] [8]
|
||||
# CHECK-NEXT: 2.50 2.50 - 8.00 - - - - - - - -
|
||||
|
||||
# CHECK: Resource pressure by instruction:
|
||||
# CHECK-NEXT: [0.0] [0.1] [1] [2] [3.0] [3.1] [4] [5.0] [5.1] [6] [7] [8] Instructions:
|
||||
# CHECK-NEXT: - - - 8.00 - - - - - - - - sdiv w12, w21, w0
|
||||
# CHECK-NEXT: 0.50 0.50 - - - - - - - - - - add w8, w8, #1
|
||||
# CHECK-NEXT: 0.50 0.50 - - - - - - - - - - add w1, w2, w0
|
||||
# CHECK-NEXT: 0.50 0.50 - - - - - - - - - - add w3, w4, #1
|
||||
# CHECK-NEXT: 0.50 0.50 - - - - - - - - - - add w5, w6, w0
|
||||
# CHECK-NEXT: 0.50 0.50 - - - - - - - - - - add w7, w9, w0
|
||||
|
||||
# CHECK: Timeline view:
|
||||
# CHECK-NEXT: 01234567
|
||||
# CHECK-NEXT: Index 0123456789
|
||||
|
||||
# CHECK: [0,0] DeeeeeeeER. . . sdiv w12, w21, w0
|
||||
# CHECK-NEXT: [0,1] DeeE-----R. . . add w8, w8, #1
|
||||
# CHECK-NEXT: [0,2] .DeeE----R. . . add w1, w2, w0
|
||||
# CHECK-NEXT: [0,3] .DeeE----R. . . add w3, w4, #1
|
||||
# CHECK-NEXT: [0,4] . DeeE---R. . . add w5, w6, w0
|
||||
# CHECK-NEXT: [0,5] . DeeE---R. . . add w7, w9, w0
|
||||
# CHECK-NEXT: [1,0] . . DeeeeeeeER sdiv w12, w21, w0
|
||||
# CHECK-NEXT: [1,1] . . DeeE-----R add w8, w8, #1
|
||||
# CHECK-NEXT: [1,2] . . DeeE----R add w1, w2, w0
|
||||
# CHECK-NEXT: [1,3] . . DeeE----R add w3, w4, #1
|
||||
# CHECK-NEXT: [1,4] . . DeeE---R add w5, w6, w0
|
||||
# CHECK-NEXT: [1,5] . . DeeE---R add w7, w9, w0
|
||||
|
||||
# CHECK: Average Wait times (based on the timeline view):
|
||||
# CHECK-NEXT: [0]: Executions
|
||||
# CHECK-NEXT: [1]: Average time spent waiting in a scheduler's queue
|
||||
# CHECK-NEXT: [2]: Average time spent waiting in a scheduler's queue while ready
|
||||
# CHECK-NEXT: [3]: Average time elapsed from WB until retire stage
|
||||
|
||||
# CHECK: [0] [1] [2] [3]
|
||||
# CHECK-NEXT: 0. 2 0.0 0.0 0.0 sdiv w12, w21, w0
|
||||
# CHECK-NEXT: 1. 2 0.0 0.0 5.0 add w8, w8, #1
|
||||
# CHECK-NEXT: 2. 2 0.0 0.0 4.0 add w1, w2, w0
|
||||
# CHECK-NEXT: 3. 2 0.0 0.0 4.0 add w3, w4, #1
|
||||
# CHECK-NEXT: 4. 2 0.0 0.0 3.0 add w5, w6, w0
|
||||
# CHECK-NEXT: 5. 2 0.0 0.0 3.0 add w7, w9, w0
|
||||
# CHECK-NEXT: 2 0.0 0.0 3.2 <total>
|
||||
129
test/tools/llvm-mca/AArch64/Cortex/A55-out-of-order-retire.s
Normal file
129
test/tools/llvm-mca/AArch64/Cortex/A55-out-of-order-retire.s
Normal file
@ -0,0 +1,129 @@
|
||||
# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
|
||||
# RUN: llvm-mca -mtriple=aarch64 -mcpu=cortex-a55 --all-stats --all-views --iterations=2 < %s | FileCheck %s
|
||||
|
||||
fdiv s1, s2, s3
|
||||
add w8, w8, #1
|
||||
add w1, w2, w0
|
||||
add w3, w4, #1
|
||||
add w5, w6, w0
|
||||
add w7, w9, w0
|
||||
|
||||
# CHECK: Iterations: 2
|
||||
# CHECK-NEXT: Instructions: 12
|
||||
# CHECK-NEXT: Total Cycles: 25
|
||||
# CHECK-NEXT: Total uOps: 12
|
||||
|
||||
# CHECK: Dispatch Width: 2
|
||||
# CHECK-NEXT: uOps Per Cycle: 0.48
|
||||
# CHECK-NEXT: IPC: 0.48
|
||||
# CHECK-NEXT: Block RThroughput: 10.0
|
||||
|
||||
# CHECK: Instruction Info:
|
||||
# CHECK-NEXT: [1]: #uOps
|
||||
# CHECK-NEXT: [2]: Latency
|
||||
# CHECK-NEXT: [3]: RThroughput
|
||||
# CHECK-NEXT: [4]: MayLoad
|
||||
# CHECK-NEXT: [5]: MayStore
|
||||
# CHECK-NEXT: [6]: HasSideEffects (U)
|
||||
|
||||
# CHECK: [1] [2] [3] [4] [5] [6] Instructions:
|
||||
# CHECK-NEXT: 1 13 10.00 fdiv s1, s2, s3
|
||||
# CHECK-NEXT: 1 3 0.50 add w8, w8, #1
|
||||
# CHECK-NEXT: 1 3 0.50 add w1, w2, w0
|
||||
# CHECK-NEXT: 1 3 0.50 add w3, w4, #1
|
||||
# CHECK-NEXT: 1 3 0.50 add w5, w6, w0
|
||||
# CHECK-NEXT: 1 3 0.50 add w7, w9, w0
|
||||
|
||||
# CHECK: Dynamic Dispatch Stall Cycles:
|
||||
# CHECK-NEXT: RAT - Register unavailable: 0
|
||||
# CHECK-NEXT: RCU - Retire tokens unavailable: 0
|
||||
# CHECK-NEXT: SCHEDQ - Scheduler full: 0
|
||||
# CHECK-NEXT: LQ - Load queue full: 0
|
||||
# CHECK-NEXT: SQ - Store queue full: 0
|
||||
# CHECK-NEXT: GROUP - Static restrictions on the dispatch group: 7 (28.0%)
|
||||
|
||||
# CHECK: Dispatch Logic - number of cycles where we saw N micro opcodes dispatched:
|
||||
# CHECK-NEXT: [# dispatched], [# cycles]
|
||||
# CHECK-NEXT: 0, 19 (76.0%)
|
||||
# CHECK-NEXT: 2, 6 (24.0%)
|
||||
|
||||
# CHECK: Schedulers - number of cycles where we saw N micro opcodes issued:
|
||||
# CHECK-NEXT: [# issued], [# cycles]
|
||||
# CHECK-NEXT: 0, 19 (76.0%)
|
||||
# CHECK-NEXT: 2, 6 (24.0%)
|
||||
|
||||
# CHECK: Scheduler's queue usage:
|
||||
# CHECK-NEXT: No scheduler resources used.
|
||||
|
||||
# CHECK: Retire Control Unit - number of cycles where we saw N instructions retired:
|
||||
# CHECK-NEXT: [# retired], [# cycles]
|
||||
# CHECK-NEXT: 0, 18 (72.0%)
|
||||
# CHECK-NEXT: 1, 2 (8.0%)
|
||||
# CHECK-NEXT: 2, 5 (20.0%)
|
||||
|
||||
# CHECK: Total ROB Entries: 64
|
||||
# CHECK-NEXT: Max Used ROB Entries: 7 ( 10.9% )
|
||||
# CHECK-NEXT: Average Used ROB Entries per cy: 2 ( 3.1% )
|
||||
|
||||
# CHECK: Register File statistics:
|
||||
# CHECK-NEXT: Total number of mappings created: 12
|
||||
# CHECK-NEXT: Max number of mappings used: 7
|
||||
|
||||
# CHECK: Resources:
|
||||
# CHECK-NEXT: [0.0] - CortexA55UnitALU
|
||||
# CHECK-NEXT: [0.1] - CortexA55UnitALU
|
||||
# CHECK-NEXT: [1] - CortexA55UnitB
|
||||
# CHECK-NEXT: [2] - CortexA55UnitDiv
|
||||
# CHECK-NEXT: [3.0] - CortexA55UnitFPALU
|
||||
# CHECK-NEXT: [3.1] - CortexA55UnitFPALU
|
||||
# CHECK-NEXT: [4] - CortexA55UnitFPDIV
|
||||
# CHECK-NEXT: [5.0] - CortexA55UnitFPMAC
|
||||
# CHECK-NEXT: [5.1] - CortexA55UnitFPMAC
|
||||
# CHECK-NEXT: [6] - CortexA55UnitLd
|
||||
# CHECK-NEXT: [7] - CortexA55UnitMAC
|
||||
# CHECK-NEXT: [8] - CortexA55UnitSt
|
||||
|
||||
# CHECK: Resource pressure per iteration:
|
||||
# CHECK-NEXT: [0.0] [0.1] [1] [2] [3.0] [3.1] [4] [5.0] [5.1] [6] [7] [8]
|
||||
# CHECK-NEXT: 2.50 2.50 - - - - 10.00 - - - - -
|
||||
|
||||
# CHECK: Resource pressure by instruction:
|
||||
# CHECK-NEXT: [0.0] [0.1] [1] [2] [3.0] [3.1] [4] [5.0] [5.1] [6] [7] [8] Instructions:
|
||||
# CHECK-NEXT: - - - - - - 10.00 - - - - - fdiv s1, s2, s3
|
||||
# CHECK-NEXT: 0.50 0.50 - - - - - - - - - - add w8, w8, #1
|
||||
# CHECK-NEXT: 0.50 0.50 - - - - - - - - - - add w1, w2, w0
|
||||
# CHECK-NEXT: 0.50 0.50 - - - - - - - - - - add w3, w4, #1
|
||||
# CHECK-NEXT: 0.50 0.50 - - - - - - - - - - add w5, w6, w0
|
||||
# CHECK-NEXT: 0.50 0.50 - - - - - - - - - - add w7, w9, w0
|
||||
|
||||
# CHECK: Timeline view:
|
||||
# CHECK-NEXT: 0123456789
|
||||
# CHECK-NEXT: Index 0123456789 01234
|
||||
|
||||
# CHECK: [0,0] DeeeeeeeeeeeeER. . . fdiv s1, s2, s3
|
||||
# CHECK-NEXT: [0,1] DeeER. . . . . add w8, w8, #1
|
||||
# CHECK-NEXT: [0,2] .DeeER . . . . add w1, w2, w0
|
||||
# CHECK-NEXT: [0,3] .DeeER . . . . add w3, w4, #1
|
||||
# CHECK-NEXT: [0,4] . DeeER . . . . add w5, w6, w0
|
||||
# CHECK-NEXT: [0,5] . DeeER . . . . add w7, w9, w0
|
||||
# CHECK-NEXT: [1,0] . . DeeeeeeeeeeeeER fdiv s1, s2, s3
|
||||
# CHECK-NEXT: [1,1] . . DeeER. . . add w8, w8, #1
|
||||
# CHECK-NEXT: [1,2] . . .DeeER . . add w1, w2, w0
|
||||
# CHECK-NEXT: [1,3] . . .DeeER . . add w3, w4, #1
|
||||
# CHECK-NEXT: [1,4] . . . DeeER . . add w5, w6, w0
|
||||
# CHECK-NEXT: [1,5] . . . DeeER . . add w7, w9, w0
|
||||
|
||||
# CHECK: Average Wait times (based on the timeline view):
|
||||
# CHECK-NEXT: [0]: Executions
|
||||
# CHECK-NEXT: [1]: Average time spent waiting in a scheduler's queue
|
||||
# CHECK-NEXT: [2]: Average time spent waiting in a scheduler's queue while ready
|
||||
# CHECK-NEXT: [3]: Average time elapsed from WB until retire stage
|
||||
|
||||
# CHECK: [0] [1] [2] [3]
|
||||
# CHECK-NEXT: 0. 2 0.0 0.0 0.0 fdiv s1, s2, s3
|
||||
# CHECK-NEXT: 1. 2 0.0 0.0 0.0 add w8, w8, #1
|
||||
# CHECK-NEXT: 2. 2 0.0 0.0 0.0 add w1, w2, w0
|
||||
# CHECK-NEXT: 3. 2 0.0 0.0 0.0 add w3, w4, #1
|
||||
# CHECK-NEXT: 4. 2 0.0 0.0 0.0 add w5, w6, w0
|
||||
# CHECK-NEXT: 5. 2 0.0 0.0 0.0 add w7, w9, w0
|
||||
# CHECK-NEXT: 2 0.0 0.0 0.0 <total>
|
||||
@ -0,0 +1,8 @@
|
||||
# RUN: llvm-mca -mtriple=aarch64 -mcpu=cortex-a55 --all-views < %s | FileCheck %s
|
||||
# CHECK-NOT: Throughput Bottlenecks
|
||||
|
||||
# RUN: llvm-mca -mtriple=aarch64 -mcpu=cortex-a55 --bottleneck-analysis < %s -o /dev/null 2>&1 | FileCheck %s --check-prefix=CHECK-WARN
|
||||
# CHECK-WARN: warning: bottleneck analysis is not supported for in-order CPU 'cortex-a55'
|
||||
|
||||
add w2, w3, #1
|
||||
|
||||
75
test/tools/llvm-mca/ARM/m7-negative-readadvance.s
Normal file
75
test/tools/llvm-mca/ARM/m7-negative-readadvance.s
Normal file
@ -0,0 +1,75 @@
|
||||
# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
|
||||
# RUN: llvm-mca -mtriple=arm -mcpu=cortex-m7 --timeline --iterations=1 < %s | FileCheck %s
|
||||
|
||||
add r1, r1, #1
|
||||
# ReadAdvance: 0
|
||||
add r1, r1, #2
|
||||
# ReadAdvance: -1
|
||||
vldr d0, [r1]
|
||||
|
||||
# CHECK: Iterations: 1
|
||||
# CHECK-NEXT: Instructions: 3
|
||||
# CHECK-NEXT: Total Cycles: 7
|
||||
# CHECK-NEXT: Total uOps: 3
|
||||
|
||||
# CHECK: Dispatch Width: 2
|
||||
# CHECK-NEXT: uOps Per Cycle: 0.43
|
||||
# CHECK-NEXT: IPC: 0.43
|
||||
# CHECK-NEXT: Block RThroughput: 1.5
|
||||
|
||||
# CHECK: Instruction Info:
|
||||
# CHECK-NEXT: [1]: #uOps
|
||||
# CHECK-NEXT: [2]: Latency
|
||||
# CHECK-NEXT: [3]: RThroughput
|
||||
# CHECK-NEXT: [4]: MayLoad
|
||||
# CHECK-NEXT: [5]: MayStore
|
||||
# CHECK-NEXT: [6]: HasSideEffects (U)
|
||||
|
||||
# CHECK: [1] [2] [3] [4] [5] [6] Instructions:
|
||||
# CHECK-NEXT: 1 1 0.50 add.w r1, r1, #1
|
||||
# CHECK-NEXT: 1 1 0.50 add.w r1, r1, #2
|
||||
# CHECK-NEXT: 1 3 1.00 * vldr d0, [r1]
|
||||
|
||||
# CHECK: Resources:
|
||||
# CHECK-NEXT: [0.0] - M7UnitALU
|
||||
# CHECK-NEXT: [0.1] - M7UnitALU
|
||||
# CHECK-NEXT: [1] - M7UnitBranch
|
||||
# CHECK-NEXT: [2.0] - M7UnitLoad
|
||||
# CHECK-NEXT: [2.1] - M7UnitLoad
|
||||
# CHECK-NEXT: [3] - M7UnitMAC
|
||||
# CHECK-NEXT: [4] - M7UnitSIMD
|
||||
# CHECK-NEXT: [5] - M7UnitShift1
|
||||
# CHECK-NEXT: [6] - M7UnitShift2
|
||||
# CHECK-NEXT: [7] - M7UnitStore
|
||||
# CHECK-NEXT: [8] - M7UnitVFP
|
||||
# CHECK-NEXT: [9.0] - M7UnitVPort
|
||||
# CHECK-NEXT: [9.1] - M7UnitVPort
|
||||
|
||||
# CHECK: Resource pressure per iteration:
|
||||
# CHECK-NEXT: [0.0] [0.1] [1] [2.0] [2.1] [3] [4] [5] [6] [7] [8] [9.0] [9.1]
|
||||
# CHECK-NEXT: 1.00 1.00 - - 1.00 - - - - - - - 2.00
|
||||
|
||||
# CHECK: Resource pressure by instruction:
|
||||
# CHECK-NEXT: [0.0] [0.1] [1] [2.0] [2.1] [3] [4] [5] [6] [7] [8] [9.0] [9.1] Instructions:
|
||||
# CHECK-NEXT: - 1.00 - - - - - - - - - - - add.w r1, r1, #1
|
||||
# CHECK-NEXT: 1.00 - - - - - - - - - - - - add.w r1, r1, #2
|
||||
# CHECK-NEXT: - - - - 1.00 - - - - - - - 2.00 vldr d0, [r1]
|
||||
|
||||
# CHECK: Timeline view:
|
||||
# CHECK-NEXT: Index 0123456
|
||||
|
||||
# CHECK: [0,0] DER .. add.w r1, r1, #1
|
||||
# CHECK-NEXT: [0,1] .DER .. add.w r1, r1, #2
|
||||
# CHECK-NEXT: [0,2] . DeER vldr d0, [r1]
|
||||
|
||||
# CHECK: Average Wait times (based on the timeline view):
|
||||
# CHECK-NEXT: [0]: Executions
|
||||
# CHECK-NEXT: [1]: Average time spent waiting in a scheduler's queue
|
||||
# CHECK-NEXT: [2]: Average time spent waiting in a scheduler's queue while ready
|
||||
# CHECK-NEXT: [3]: Average time elapsed from WB until retire stage
|
||||
|
||||
# CHECK: [0] [1] [2] [3]
|
||||
# CHECK-NEXT: 0. 1 0.0 0.0 0.0 add.w r1, r1, #1
|
||||
# CHECK-NEXT: 1. 1 0.0 0.0 0.0 add.w r1, r1, #2
|
||||
# CHECK-NEXT: 2. 1 0.0 0.0 0.0 vldr d0, [r1]
|
||||
# CHECK-NEXT: 1 0.0 0.0 0.0 <total>
|
||||
@ -1,3 +1,3 @@
|
||||
# RUN: not llvm-mca %s -mtriple=x86_64-unknown-unknown -mcpu=atom -o /dev/null 2>&1 | FileCheck %s
|
||||
|
||||
# CHECK: error: please specify an out-of-order cpu. 'atom' is an in-order cpu.
|
||||
# RUN: llvm-mca %s -mtriple=x86_64-unknown-unknown -mcpu=atom -o /dev/null 2>&1 | FileCheck %s
|
||||
# CHECK: warning: support for in-order CPU 'atom' is experimental.
|
||||
movsbw %al, %di
|
||||
|
||||
@ -257,14 +257,15 @@ static void processOptionImpl(cl::opt<bool> &O, const cl::opt<bool> &Default) {
|
||||
O = Default.getValue();
|
||||
}
|
||||
|
||||
static void processViewOptions() {
|
||||
static void processViewOptions(bool IsOutOfOrder) {
|
||||
if (!EnableAllViews.getNumOccurrences() &&
|
||||
!EnableAllStats.getNumOccurrences())
|
||||
return;
|
||||
|
||||
if (EnableAllViews.getNumOccurrences()) {
|
||||
processOptionImpl(PrintSummaryView, EnableAllViews);
|
||||
processOptionImpl(EnableBottleneckAnalysis, EnableAllViews);
|
||||
if (IsOutOfOrder)
|
||||
processOptionImpl(EnableBottleneckAnalysis, EnableAllViews);
|
||||
processOptionImpl(PrintResourcePressureView, EnableAllViews);
|
||||
processOptionImpl(PrintTimelineView, EnableAllViews);
|
||||
processOptionImpl(PrintInstructionInfoView, EnableAllViews);
|
||||
@ -327,9 +328,6 @@ int main(int argc, char **argv) {
|
||||
return 1;
|
||||
}
|
||||
|
||||
// Apply overrides to llvm-mca specific options.
|
||||
processViewOptions();
|
||||
|
||||
if (MCPU == "native")
|
||||
MCPU = std::string(llvm::sys::getHostCPUName());
|
||||
|
||||
@ -339,10 +337,10 @@ int main(int argc, char **argv) {
|
||||
if (!STI->isCPUStringValid(MCPU))
|
||||
return 1;
|
||||
|
||||
if (!PrintInstructionTables && !STI->getSchedModel().isOutOfOrder()) {
|
||||
WithColor::error() << "please specify an out-of-order cpu. '" << MCPU
|
||||
<< "' is an in-order cpu.\n";
|
||||
return 1;
|
||||
bool IsOutOfOrder = STI->getSchedModel().isOutOfOrder();
|
||||
if (!PrintInstructionTables && !IsOutOfOrder) {
|
||||
WithColor::warning() << "support for in-order CPU '" << MCPU
|
||||
<< "' is experimental.\n";
|
||||
}
|
||||
|
||||
if (!STI->getSchedModel().hasInstrSchedModel()) {
|
||||
@ -358,6 +356,9 @@ int main(int argc, char **argv) {
|
||||
return 1;
|
||||
}
|
||||
|
||||
// Apply overrides to llvm-mca specific options.
|
||||
processViewOptions(IsOutOfOrder);
|
||||
|
||||
std::unique_ptr<MCRegisterInfo> MRI(TheTarget->createMCRegInfo(TripleName));
|
||||
assert(MRI && "Unable to create target register info!");
|
||||
|
||||
@ -539,6 +540,11 @@ int main(int argc, char **argv) {
|
||||
std::make_unique<mca::SummaryView>(SM, Insts, DispatchWidth));
|
||||
|
||||
if (EnableBottleneckAnalysis) {
|
||||
if (!IsOutOfOrder) {
|
||||
WithColor::warning()
|
||||
<< "bottleneck analysis is not supported for in-order CPU '" << MCPU
|
||||
<< "'.\n";
|
||||
}
|
||||
Printer.addView(std::make_unique<mca::BottleneckAnalysis>(
|
||||
*STI, *IP, Insts, S.getNumIterations()));
|
||||
}
|
||||
|
||||
@ -993,6 +993,7 @@ void SubtargetEmitter::GenSchedClassTables(const CodeGenProcModel &ProcModel,
|
||||
SCDesc.NumMicroOps = 0;
|
||||
SCDesc.BeginGroup = false;
|
||||
SCDesc.EndGroup = false;
|
||||
SCDesc.RetireOOO = false;
|
||||
SCDesc.WriteProcResIdx = 0;
|
||||
SCDesc.WriteLatencyIdx = 0;
|
||||
SCDesc.ReadAdvanceIdx = 0;
|
||||
@ -1095,6 +1096,7 @@ void SubtargetEmitter::GenSchedClassTables(const CodeGenProcModel &ProcModel,
|
||||
SCDesc.EndGroup |= WriteRes->getValueAsBit("EndGroup");
|
||||
SCDesc.BeginGroup |= WriteRes->getValueAsBit("SingleIssue");
|
||||
SCDesc.EndGroup |= WriteRes->getValueAsBit("SingleIssue");
|
||||
SCDesc.RetireOOO |= WriteRes->getValueAsBit("RetireOOO");
|
||||
|
||||
// Create an entry for each ProcResource listed in WriteRes.
|
||||
RecVec PRVec = WriteRes->getValueAsListOfDefs("ProcResources");
|
||||
@ -1293,7 +1295,7 @@ void SubtargetEmitter::EmitSchedClassTables(SchedClassTables &SchedTables,
|
||||
std::vector<MCSchedClassDesc> &SCTab =
|
||||
SchedTables.ProcSchedClasses[1 + (PI - SchedModels.procModelBegin())];
|
||||
|
||||
OS << "\n// {Name, NumMicroOps, BeginGroup, EndGroup,"
|
||||
OS << "\n// {Name, NumMicroOps, BeginGroup, EndGroup, RetireOOO,"
|
||||
<< " WriteProcResIdx,#, WriteLatencyIdx,#, ReadAdvanceIdx,#}\n";
|
||||
OS << "static const llvm::MCSchedClassDesc "
|
||||
<< PI->ModelName << "SchedClasses[] = {\n";
|
||||
@ -1304,7 +1306,7 @@ void SubtargetEmitter::EmitSchedClassTables(SchedClassTables &SchedTables,
|
||||
&& "invalid class not first");
|
||||
OS << " {DBGFIELD(\"InvalidSchedClass\") "
|
||||
<< MCSchedClassDesc::InvalidNumMicroOps
|
||||
<< ", false, false, 0, 0, 0, 0, 0, 0},\n";
|
||||
<< ", false, false, false, 0, 0, 0, 0, 0, 0},\n";
|
||||
|
||||
for (unsigned SCIdx = 1, SCEnd = SCTab.size(); SCIdx != SCEnd; ++SCIdx) {
|
||||
MCSchedClassDesc &MCDesc = SCTab[SCIdx];
|
||||
@ -1315,6 +1317,7 @@ void SubtargetEmitter::EmitSchedClassTables(SchedClassTables &SchedTables,
|
||||
OS << MCDesc.NumMicroOps
|
||||
<< ", " << ( MCDesc.BeginGroup ? "true" : "false" )
|
||||
<< ", " << ( MCDesc.EndGroup ? "true" : "false" )
|
||||
<< ", " << ( MCDesc.RetireOOO ? "true" : "false" )
|
||||
<< ", " << format("%2d", MCDesc.WriteProcResIdx)
|
||||
<< ", " << MCDesc.NumWriteProcResEntries
|
||||
<< ", " << format("%2d", MCDesc.WriteLatencyIdx)
|
||||
|
||||
Loading…
Reference in New Issue
Block a user