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[X86] Don't create FILD ISD nodes when X87 is disabled.

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The included test case previously asserted because the type legalizer tried to soften the FILD ISD node.

Fixes PR38819.

llvm-svn: 342934
This commit is contained in:
Craig Topper 2018-09-25 00:16:57 +00:00
parent 1ab73060d7
commit 064d1312b6
2 changed files with 28 additions and 1 deletions
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3
lib/Target/X86/X86ISelLowering.cpp
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@ -39073,7 +39073,8 @@ static SDValue combineSIntToFP(SDNode *N, SelectionDAG &DAG,
// Transform (SINT_TO_FP (i64 ...)) into an x87 operation if we have
// a 32-bit target where SSE doesn't support i64->FP operations.
if (!Subtarget.useSoftFloat() && Op0.getOpcode() == ISD::LOAD) {
if (!Subtarget.useSoftFloat() && Subtarget.hasX87() &&
Op0.getOpcode() == ISD::LOAD) {
LoadSDNode *Ld = cast<LoadSDNode>(Op0.getNode());
EVT LdVT = Ld->getValueType(0);

26
test/CodeGen/X86/pr38819.ll Normal file
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@ -0,0 +1,26 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc < %s -mtriple=i686-unknown-unknown -mattr=+sse,-sse2,-x87 | FileCheck %s
define void @foo(i64 %x, float* %b) {
; CHECK-LABEL: foo:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: pushl %esi
; CHECK-NEXT: .cfi_def_cfa_offset 8
; CHECK-NEXT: .cfi_offset %esi, -8
; CHECK-NEXT: movl {{[0-9]+}}(%esp), %esi
; CHECK-NEXT: pushl {{[0-9]+}}(%esp)
; CHECK-NEXT: .cfi_adjust_cfa_offset 4
; CHECK-NEXT: pushl {{[0-9]+}}(%esp)
; CHECK-NEXT: .cfi_adjust_cfa_offset 4
; CHECK-NEXT: calll __floatdisf
; CHECK-NEXT: addl $8, %esp
; CHECK-NEXT: .cfi_adjust_cfa_offset -8
; CHECK-NEXT: movl %eax, (%esi)
; CHECK-NEXT: popl %esi
; CHECK-NEXT: .cfi_def_cfa_offset 4
; CHECK-NEXT: retl
entry:
%conv = sitofp i64 %x to float
store float %conv, float* %b
ret void
}