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[ARM] BFloat MatMul Intrinsics&CodeGen
Summary: This patch adds support for BFloat Matrix Multiplication Intrinsics and Code Generation from __bf16 to AArch32. This includes IR intrinsics. Tests are provided as needed. This patch is part of a series implementing the Bfloat16 extension of the Armv8.6-a architecture, as detailed here: https://community.arm.com/developer/ip-products/processors/b/processors-ip-blog/posts/arm-architecture-developments-armv8-6-a The bfloat type and its properties are specified in the Arm Architecture Reference Manual: https://developer.arm.com/docs/ddi0487/latest/arm-architecture-reference-manual-armv8-for-armv8-a-architecture-profile The following people contributed to this patch: - Luke Geeson - Momchil Velikov - Mikhail Maltsev - Luke Cheeseman - Simon Tatham Reviewers: stuij, t.p.northover, SjoerdMeijer, sdesmalen, fpetrogalli, LukeGeeson, simon_tatham, dmgreen, MarkMurrayARM Reviewed By: MarkMurrayARM Subscribers: MarkMurrayARM, danielkiss, kristof.beyls, hiraditya, cfe-commits, llvm-commits, chill, miyuki Tags: #clang, #llvm Differential Revision: https://reviews.llvm.org/D81740
This commit is contained in:
Mikhail Maltsev
parent
f764419b10
commit
069aeafb71
@ -785,6 +785,15 @@ def int_arm_neon_usmmla : Neon_MatMul_Intrinsic;
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def int_arm_neon_usdot : Neon_Dot_Intrinsic;
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// v8.6-A Bfloat Intrinsics
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def int_arm_neon_bfdot : Neon_Dot_Intrinsic;
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def int_arm_neon_bfmmla : Neon_MatMul_Intrinsic;
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class Neon_FML_Intrinsic
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: Intrinsic<[llvm_anyvector_ty],
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[LLVMMatchType<0>, llvm_anyvector_ty, LLVMMatchType<1>],
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[IntrNoMem]>;
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def int_arm_neon_bfmlalb : Neon_FML_Intrinsic;
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def int_arm_neon_bfmlalt : Neon_FML_Intrinsic;
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def int_arm_cls: Intrinsic<[llvm_i32_ty], [llvm_i32_ty], [IntrNoMem]>;
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def int_arm_cls64: Intrinsic<[llvm_i32_ty], [llvm_i64_ty], [IntrNoMem]>;
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@ -9099,15 +9099,20 @@ def : NEONInstAlias<"vmov${p}.f32 $Vd, $imm",
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// ARMv8.6a BFloat16 instructions.
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let Predicates = [HasBF16, HasNEON] in {
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class BF16VDOT<bits<5> op27_23, bits<2> op21_20, bit op6,
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dag oops, dag iops>
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dag oops, dag iops, list<dag> pattern>
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: N3Vnp<op27_23, op21_20, 0b1101, op6, 0, oops, iops,
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N3RegFrm, IIC_VDOTPROD, "", "", []> {
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N3RegFrm, IIC_VDOTPROD, "", "", pattern>
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{
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let DecoderNamespace = "VFPV8";
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}
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class BF16VDOTS<bit Q, RegisterClass RegTy, string opc, ValueType AccumTy, ValueType InputTy>
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: BF16VDOT<0b11000, 0b00, Q, (outs RegTy:$dst),
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(ins RegTy:$Vd, RegTy:$Vn, RegTy:$Vm)> {
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(ins RegTy:$Vd, RegTy:$Vn, RegTy:$Vm),
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[(set (AccumTy RegTy:$dst),
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(int_arm_neon_bfdot (AccumTy RegTy:$Vd),
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(InputTy RegTy:$Vn),
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(InputTy RegTy:$Vm)))]> {
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let Constraints = "$dst = $Vd";
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let AsmString = !strconcat(opc, ".bf16", "\t$Vd, $Vn, $Vm");
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let DecoderNamespace = "VFPV8";
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@ -9118,7 +9123,7 @@ multiclass BF16VDOTI<bit Q, RegisterClass RegTy, string opc, ValueType AccumTy,
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def "" : BF16VDOT<0b11100, 0b00, Q, (outs RegTy:$dst),
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(ins RegTy:$Vd, RegTy:$Vn,
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DPR_VFP2:$Vm, VectorIndex32:$lane)> {
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DPR_VFP2:$Vm, VectorIndex32:$lane), []> {
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bit lane;
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let Inst{5} = lane;
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let Constraints = "$dst = $Vd";
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@ -9126,6 +9131,13 @@ multiclass BF16VDOTI<bit Q, RegisterClass RegTy, string opc, ValueType AccumTy,
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let DecoderNamespace = "VFPV8";
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}
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def : Pat<
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(AccumTy (int_arm_neon_bfdot (AccumTy RegTy:$Vd),
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(InputTy RegTy:$Vn),
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(InputTy (bitconvert (AccumTy
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(ARMvduplane (AccumTy RegTy:$Vm),
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VectorIndex32:$lane)))))),
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(!cast<Instruction>(NAME) RegTy:$Vd, RegTy:$Vn, RHS, VectorIndex32:$lane)>;
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}
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def BF16VDOTS_VDOTD : BF16VDOTS<0, DPR, "vdot", v2f32, v8i8>;
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@ -9138,7 +9150,10 @@ class BF16MM<bit Q, RegisterClass RegTy,
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string opc>
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: N3Vnp<0b11000, 0b00, 0b1100, Q, 0,
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(outs RegTy:$dst), (ins RegTy:$Vd, RegTy:$Vn, RegTy:$Vm),
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N3RegFrm, IIC_VDOTPROD, "", "", []> {
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N3RegFrm, IIC_VDOTPROD, "", "",
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[(set (v4f32 QPR:$dst), (int_arm_neon_bfmmla (v4f32 QPR:$Vd),
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(v16i8 QPR:$Vn),
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(v16i8 QPR:$Vm)))]> {
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let Constraints = "$dst = $Vd";
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let AsmString = !strconcat(opc, ".bf16", "\t$Vd, $Vn, $Vm");
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let DecoderNamespace = "VFPV8";
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@ -9146,19 +9161,22 @@ class BF16MM<bit Q, RegisterClass RegTy,
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def VMMLA : BF16MM<1, QPR, "vmmla">;
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class VBF16MALQ<bit T, string suffix>
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class VBF16MALQ<bit T, string suffix, SDPatternOperator OpNode>
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: N3VCP8<0b00, 0b11, T, 1,
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(outs QPR:$dst), (ins QPR:$Vd, QPR:$Vn, QPR:$Vm),
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NoItinerary, "vfma" # suffix, "bf16", "$Vd, $Vn, $Vm", "",
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[]> { // TODO: Add intrinsics
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[(set (v4f32 QPR:$dst),
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(OpNode (v4f32 QPR:$Vd),
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(v16i8 QPR:$Vn),
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(v16i8 QPR:$Vm)))]> {
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let Constraints = "$dst = $Vd";
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let DecoderNamespace = "VFPV8";
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}
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def VBF16MALTQ: VBF16MALQ<1, "t">;
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def VBF16MALBQ: VBF16MALQ<0, "b">;
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def VBF16MALTQ: VBF16MALQ<1, "t", int_arm_neon_bfmlalt>;
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def VBF16MALBQ: VBF16MALQ<0, "b", int_arm_neon_bfmlalb>;
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multiclass VBF16MALQI<bit T, string suffix> {
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multiclass VBF16MALQI<bit T, string suffix, SDPatternOperator OpNode> {
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def "" : N3VLaneCP8<0, 0b11, T, 1, (outs QPR:$dst),
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(ins QPR:$Vd, QPR:$Vn, DPR_8:$Vm, VectorIndex16:$idx),
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IIC_VMACD, "vfma" # suffix, "bf16", "$Vd, $Vn, $Vm$idx", "", []> {
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@ -9169,10 +9187,20 @@ multiclass VBF16MALQI<bit T, string suffix> {
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let DecoderNamespace = "VFPV8";
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}
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def : Pat<
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(v4f32 (OpNode (v4f32 QPR:$Vd),
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(v16i8 QPR:$Vn),
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(v16i8 (bitconvert (v8bf16 (ARMvduplane (v8bf16 QPR:$Vm),
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VectorIndex16:$lane)))))),
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(!cast<Instruction>(NAME) QPR:$Vd,
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QPR:$Vn,
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(EXTRACT_SUBREG QPR:$Vm,
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(DSubReg_i16_reg VectorIndex16:$lane)),
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(SubReg_i16_lane VectorIndex16:$lane))>;
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}
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defm VBF16MALTQI: VBF16MALQI<1, "t">;
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defm VBF16MALBQI: VBF16MALQI<0, "b">;
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defm VBF16MALTQI: VBF16MALQI<1, "t", int_arm_neon_bfmlalt>;
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defm VBF16MALBQI: VBF16MALQI<0, "b", int_arm_neon_bfmlalb>;
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def BF16_VCVT : N2V<0b11, 0b11, 0b01, 0b10, 0b01100, 1, 0,
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(outs DPR:$Vd), (ins QPR:$Vm),
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194
test/CodeGen/ARM/arm-bf16-dotprod-intrinsics.ll
Normal file
194
test/CodeGen/ARM/arm-bf16-dotprod-intrinsics.ll
Normal file
@ -0,0 +1,194 @@
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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -mtriple armv8.6a-arm-none-eabi -mattr=+neon,+bf16 -float-abi=hard -verify-machineinstrs < %s -o - | FileCheck %s
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define arm_aapcs_vfpcc <2 x float> @test_vbfdot_f32(<2 x float> %r, <4 x bfloat> %a, <4 x bfloat> %b) {
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; CHECK-LABEL: test_vbfdot_f32:
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; CHECK: @ %bb.0: @ %entry
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; CHECK-NEXT: vdot.bf16 d0, d1, d2
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; CHECK-NEXT: bx lr
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entry:
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%0 = bitcast <4 x bfloat> %a to <8 x i8>
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%1 = bitcast <4 x bfloat> %b to <8 x i8>
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%vbfdot1.i = call <2 x float> @llvm.arm.neon.bfdot.v2f32.v8i8(<2 x float> %r, <8 x i8> %0, <8 x i8> %1)
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ret <2 x float> %vbfdot1.i
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}
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define <4 x float> @test_vbfdotq_f32(<4 x float> %r, <8 x bfloat> %a, <8 x bfloat> %b) {
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; CHECK-LABEL: test_vbfdotq_f32:
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; CHECK: @ %bb.0: @ %entry
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; CHECK-NEXT: vdot.bf16 q0, q1, q2
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; CHECK-NEXT: bx lr
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entry:
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%0 = bitcast <8 x bfloat> %a to <16 x i8>
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%1 = bitcast <8 x bfloat> %b to <16 x i8>
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%vbfdot1.i = call <4 x float> @llvm.arm.neon.bfdot.v4f32.v16i8(<4 x float> %r, <16 x i8> %0, <16 x i8> %1)
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ret <4 x float> %vbfdot1.i
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}
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define <2 x float> @test_vbfdot_lane_f32(<2 x float> %r, <4 x bfloat> %a, <4 x bfloat> %b) {
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; CHECK-LABEL: test_vbfdot_lane_f32:
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; CHECK: @ %bb.0: @ %entry
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; CHECK-NEXT: vdot.bf16 d0, d1, d2[0]
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; CHECK-NEXT: bx lr
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entry:
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%0 = bitcast <4 x bfloat> %b to <2 x float>
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%shuffle = shufflevector <2 x float> %0, <2 x float> undef, <2 x i32> zeroinitializer
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%1 = bitcast <4 x bfloat> %a to <8 x i8>
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%2 = bitcast <2 x float> %shuffle to <8 x i8>
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%vbfdot1.i = call <2 x float> @llvm.arm.neon.bfdot.v2f32.v8i8(<2 x float> %r, <8 x i8> %1, <8 x i8> %2)
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ret <2 x float> %vbfdot1.i
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}
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define <4 x float> @test_vbfdotq_laneq_f32(<4 x float> %r, <8 x bfloat> %a, <8 x bfloat> %b) {
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; CHECK-LABEL: test_vbfdotq_laneq_f32:
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; CHECK: @ %bb.0: @ %entry
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; CHECK-NEXT: vdup.32 q8, d5[1]
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; CHECK-NEXT: vdot.bf16 q0, q1, q8
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; CHECK-NEXT: bx lr
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entry:
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%0 = bitcast <8 x bfloat> %b to <4 x float>
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%shuffle = shufflevector <4 x float> %0, <4 x float> undef, <4 x i32> <i32 3, i32 3, i32 3, i32 3>
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%1 = bitcast <8 x bfloat> %a to <16 x i8>
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%2 = bitcast <4 x float> %shuffle to <16 x i8>
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%vbfdot1.i = call <4 x float> @llvm.arm.neon.bfdot.v4f32.v16i8(<4 x float> %r, <16 x i8> %1, <16 x i8> %2)
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ret <4 x float> %vbfdot1.i
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}
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define <2 x float> @test_vbfdot_laneq_f32(<2 x float> %r, <4 x bfloat> %a, <8 x bfloat> %b) {
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; CHECK-LABEL: test_vbfdot_laneq_f32:
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; CHECK: @ %bb.0: @ %entry
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; CHECK-NEXT: vdot.bf16 d0, d1, d3[1]
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; CHECK-NEXT: bx lr
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entry:
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%0 = bitcast <8 x bfloat> %b to <4 x float>
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%shuffle = shufflevector <4 x float> %0, <4 x float> undef, <2 x i32> <i32 3, i32 3>
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%1 = bitcast <4 x bfloat> %a to <8 x i8>
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%2 = bitcast <2 x float> %shuffle to <8 x i8>
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%vbfdot1.i = call <2 x float> @llvm.arm.neon.bfdot.v2f32.v8i8(<2 x float> %r, <8 x i8> %1, <8 x i8> %2)
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ret <2 x float> %vbfdot1.i
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}
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define <4 x float> @test_vbfdotq_lane_f32(<4 x float> %r, <8 x bfloat> %a, <4 x bfloat> %b) {
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; CHECK-LABEL: test_vbfdotq_lane_f32:
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; CHECK: @ %bb.0: @ %entry
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; CHECK-NEXT: @ kill: def $d4 killed $d4 def $q2
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; CHECK-NEXT: vdot.bf16 q0, q1, d4[0]
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; CHECK-NEXT: bx lr
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entry:
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%0 = bitcast <4 x bfloat> %b to <2 x float>
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%shuffle = shufflevector <2 x float> %0, <2 x float> undef, <4 x i32> zeroinitializer
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%1 = bitcast <8 x bfloat> %a to <16 x i8>
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%2 = bitcast <4 x float> %shuffle to <16 x i8>
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%vbfdot1.i = call <4 x float> @llvm.arm.neon.bfdot.v4f32.v16i8(<4 x float> %r, <16 x i8> %1, <16 x i8> %2)
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ret <4 x float> %vbfdot1.i
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}
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define <4 x float> @test_vbfmmlaq_f32(<4 x float> %r, <8 x bfloat> %a, <8 x bfloat> %b) {
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; CHECK-LABEL: test_vbfmmlaq_f32:
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; CHECK: @ %bb.0: @ %entry
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; CHECK-NEXT: vmmla.bf16 q0, q1, q2
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; CHECK-NEXT: bx lr
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entry:
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%0 = bitcast <8 x bfloat> %a to <16 x i8>
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%1 = bitcast <8 x bfloat> %b to <16 x i8>
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%vbfmmla1.i = call <4 x float> @llvm.arm.neon.bfmmla.v4f32.v16i8(<4 x float> %r, <16 x i8> %0, <16 x i8> %1)
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ret <4 x float> %vbfmmla1.i
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}
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define <4 x float> @test_vbfmlalbq_f32(<4 x float> %r, <8 x bfloat> %a, <8 x bfloat> %b) {
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; CHECK-LABEL: test_vbfmlalbq_f32:
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; CHECK: @ %bb.0: @ %entry
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; CHECK-NEXT: vfmab.bf16 q0, q1, q2
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; CHECK-NEXT: bx lr
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entry:
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%0 = bitcast <8 x bfloat> %a to <16 x i8>
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%1 = bitcast <8 x bfloat> %b to <16 x i8>
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%vbfmlalb1.i = call <4 x float> @llvm.arm.neon.bfmlalb.v4f32.v16i8(<4 x float> %r, <16 x i8> %0, <16 x i8> %1)
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ret <4 x float> %vbfmlalb1.i
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}
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define <4 x float> @test_vbfmlaltq_f32(<4 x float> %r, <8 x bfloat> %a, <8 x bfloat> %b) {
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; CHECK-LABEL: test_vbfmlaltq_f32:
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; CHECK: @ %bb.0: @ %entry
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; CHECK-NEXT: vfmat.bf16 q0, q1, q2
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; CHECK-NEXT: bx lr
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entry:
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%0 = bitcast <8 x bfloat> %a to <16 x i8>
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%1 = bitcast <8 x bfloat> %b to <16 x i8>
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%vbfmlalt1.i = call <4 x float> @llvm.arm.neon.bfmlalt.v4f32.v16i8(<4 x float> %r, <16 x i8> %0, <16 x i8> %1)
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ret <4 x float> %vbfmlalt1.i
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}
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define <4 x float> @test_vbfmlalbq_lane_f32(<4 x float> %r, <8 x bfloat> %a, <4 x bfloat> %b) {
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; CHECK-LABEL: test_vbfmlalbq_lane_f32:
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; CHECK: @ %bb.0: @ %entry
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; CHECK-NEXT: @ kill: def $d4 killed $d4 def $q2
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; CHECK-NEXT: vfmab.bf16 q0, q1, d4[0]
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; CHECK-NEXT: bx lr
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entry:
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%vecinit35 = shufflevector <4 x bfloat> %b, <4 x bfloat> undef, <8 x i32> zeroinitializer
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%0 = bitcast <8 x bfloat> %a to <16 x i8>
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%1 = bitcast <8 x bfloat> %vecinit35 to <16 x i8>
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%vbfmlalb1.i = call <4 x float> @llvm.arm.neon.bfmlalb.v4f32.v16i8(<4 x float> %r, <16 x i8> %0, <16 x i8> %1)
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ret <4 x float> %vbfmlalb1.i
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}
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define <4 x float> @test_vbfmlalbq_laneq_f32(<4 x float> %r, <8 x bfloat> %a, <8 x bfloat> %b) {
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; CHECK-LABEL: test_vbfmlalbq_laneq_f32:
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; CHECK: @ %bb.0: @ %entry
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; CHECK-NEXT: vfmab.bf16 q0, q1, d4[3]
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; CHECK-NEXT: bx lr
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entry:
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%vecinit35 = shufflevector <8 x bfloat> %b, <8 x bfloat> undef, <8 x i32> <i32 3, i32 3, i32 3, i32 3, i32 3, i32 3, i32 3, i32 3>
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%0 = bitcast <8 x bfloat> %a to <16 x i8>
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%1 = bitcast <8 x bfloat> %vecinit35 to <16 x i8>
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%vbfmlalb1.i = call <4 x float> @llvm.arm.neon.bfmlalb.v4f32.v16i8(<4 x float> %r, <16 x i8> %0, <16 x i8> %1)
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ret <4 x float> %vbfmlalb1.i
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}
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define <4 x float> @test_vbfmlaltq_lane_f32(<4 x float> %r, <8 x bfloat> %a, <4 x bfloat> %b) {
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; CHECK-LABEL: test_vbfmlaltq_lane_f32:
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; CHECK: @ %bb.0: @ %entry
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; CHECK-NEXT: @ kill: def $d4 killed $d4 def $q2
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; CHECK-NEXT: vfmat.bf16 q0, q1, d4[0]
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; CHECK-NEXT: bx lr
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entry:
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%vecinit35 = shufflevector <4 x bfloat> %b, <4 x bfloat> undef, <8 x i32> zeroinitializer
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%0 = bitcast <8 x bfloat> %a to <16 x i8>
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%1 = bitcast <8 x bfloat> %vecinit35 to <16 x i8>
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%vbfmlalt1.i = call <4 x float> @llvm.arm.neon.bfmlalt.v4f32.v16i8(<4 x float> %r, <16 x i8> %0, <16 x i8> %1)
|
||||
ret <4 x float> %vbfmlalt1.i
|
||||
}
|
||||
|
||||
define <4 x float> @test_vbfmlaltq_laneq_f32(<4 x float> %r, <8 x bfloat> %a, <8 x bfloat> %b) {
|
||||
; CHECK-LABEL: test_vbfmlaltq_laneq_f32:
|
||||
; CHECK: @ %bb.0: @ %entry
|
||||
; CHECK-NEXT: vfmat.bf16 q0, q1, d4[3]
|
||||
; CHECK-NEXT: bx lr
|
||||
entry:
|
||||
%vecinit35 = shufflevector <8 x bfloat> %b, <8 x bfloat> undef, <8 x i32> <i32 3, i32 3, i32 3, i32 3, i32 3, i32 3, i32 3, i32 3>
|
||||
%0 = bitcast <8 x bfloat> %a to <16 x i8>
|
||||
%1 = bitcast <8 x bfloat> %vecinit35 to <16 x i8>
|
||||
%vbfmlalt1.i = call <4 x float> @llvm.arm.neon.bfmlalt.v4f32.v16i8(<4 x float> %r, <16 x i8> %0, <16 x i8> %1)
|
||||
ret <4 x float> %vbfmlalt1.i
|
||||
}
|
||||
|
||||
define <4 x float> @test_vbfmlaltq_laneq_f32_v2(<4 x float> %r, <8 x bfloat> %a, <8 x bfloat> %b) {
|
||||
; CHECK-LABEL: test_vbfmlaltq_laneq_f32_v2:
|
||||
; CHECK: @ %bb.0: @ %entry
|
||||
; CHECK-NEXT: vdup.16 q8, d5[2]
|
||||
; CHECK-NEXT: vfmat.bf16 q0, q1, q8
|
||||
; CHECK-NEXT: bx lr
|
||||
entry:
|
||||
%vecinit35 = shufflevector <8 x bfloat> %b, <8 x bfloat> undef, <8 x i32> <i32 6, i32 6, i32 6, i32 6, i32 6, i32 6, i32 6, i32 6>
|
||||
%0 = bitcast <8 x bfloat> %a to <16 x i8>
|
||||
%1 = bitcast <8 x bfloat> %vecinit35 to <16 x i8>
|
||||
%vbfmlalt1.i = call <4 x float> @llvm.arm.neon.bfmlalt.v4f32.v16i8(<4 x float> %r, <16 x i8> %0, <16 x i8> %1)
|
||||
ret <4 x float> %vbfmlalt1.i
|
||||
}
|
||||
|
||||
declare <2 x float> @llvm.arm.neon.bfdot.v2f32.v8i8(<2 x float>, <8 x i8>, <8 x i8>)
|
||||
declare <4 x float> @llvm.arm.neon.bfdot.v4f32.v16i8(<4 x float>, <16 x i8>, <16 x i8>)
|
||||
declare <4 x float> @llvm.arm.neon.bfmmla.v4f32.v16i8(<4 x float>, <16 x i8>, <16 x i8>)
|
||||
declare <4 x float> @llvm.arm.neon.bfmlalb.v4f32.v16i8(<4 x float>, <16 x i8>, <16 x i8>)
|
||||
declare <4 x float> @llvm.arm.neon.bfmlalt.v4f32.v16i8(<4 x float>, <16 x i8>, <16 x i8>)
|
||||
Loading…
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Reference in New Issue
Block a user