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Revert "[VirtRegRewriter] Avoid clobbering registers when expanding copy bundles"
There's an msan failure: http://lab.llvm.org:8011/builders/sanitizer-x86_64-linux-fast/builds/19549 This reverts r334750. llvm-svn: 334754
This commit is contained in:
Justin Bogner
parent
c2f9b2d826
commit
0705216f21
@ -406,8 +406,6 @@ void VirtRegRewriter::expandCopyBundle(MachineInstr &MI) const {
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return;
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if (MI.isBundledWithPred() && !MI.isBundledWithSucc()) {
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SmallVector<MachineInstr *, 2> MIs({&MI});
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// Only do this when the complete bundle is made out of COPYs.
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MachineBasicBlock &MBB = *MI.getParent();
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for (MachineBasicBlock::reverse_instr_iterator I =
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@ -415,53 +413,16 @@ void VirtRegRewriter::expandCopyBundle(MachineInstr &MI) const {
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I != E && I->isBundledWithSucc(); ++I) {
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if (!I->isCopy())
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return;
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MIs.push_back(&*I);
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}
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MachineInstr *FirstMI = MIs.back();
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auto anyRegsAlias = [](const MachineInstr *Dst,
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ArrayRef<MachineInstr *> Srcs,
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const TargetRegisterInfo *TRI) {
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for (const MachineInstr *Src : Srcs)
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if (Src != Dst)
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if (TRI->regsOverlap(Dst->getOperand(0).getReg(),
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Src->getOperand(1).getReg()))
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return true;
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return false;
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};
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// If any of the destination registers in the bundle of copies alias any of
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// the source registers, try to schedule the instructions to avoid any
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// clobbering.
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for (int E = MIs.size(), PrevE; E > 1; PrevE = E) {
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for (int I = E; I--; )
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if (!anyRegsAlias(MIs[I], makeArrayRef(MIs).take_front(E), TRI)) {
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if (I + 1 != E)
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std::swap(MIs[I], MIs[E - 1]);
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--E;
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}
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if (PrevE == E) {
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MF->getFunction().getContext().emitError(
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"register rewriting failed: cycle in copy bundle");
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break;
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}
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}
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MachineInstr *BundleStart = FirstMI;
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for (MachineInstr *BundledMI : llvm::reverse(MIs)) {
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// If instruction is in the middle of the bundle, move it before the
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// bundle starts, otherwise, just unbundle it. When we get to the last
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// instruction, the bundle will have been completely undone.
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if (BundledMI != BundleStart) {
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BundledMI->removeFromBundle();
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MBB.insert(FirstMI, BundledMI);
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} else if (BundledMI->isBundledWithSucc()) {
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BundledMI->unbundleFromSucc();
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BundleStart = &*std::next(BundledMI->getIterator());
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}
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for (MachineBasicBlock::reverse_instr_iterator I = MI.getReverseIterator();
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I->isBundledWithPred(); ) {
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MachineInstr &MI = *I;
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++I;
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if (Indexes && BundledMI != FirstMI)
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Indexes->insertMachineInstrInMaps(*BundledMI);
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MI.unbundleFromPred();
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if (Indexes)
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Indexes->insertMachineInstrInMaps(MI);
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}
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}
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}
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@ -1,16 +0,0 @@
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# RUN: not llc -mtriple=aarch64-apple-ios -run-pass=greedy -run-pass=virtregrewriter %s -o /dev/null 2>&1 | FileCheck %s
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# Check we don't infinitely loop on cycles in copy bundles.
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# CHECK: error: register rewriting failed: cycle in copy bundle
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---
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name: func0
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body: |
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bb.0:
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$x0 = IMPLICIT_DEF
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$q0_q1_q2_q3 = IMPLICIT_DEF
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$q1_q2_q3 = COPY $q0_q1_q2 {
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$q2_q3_q4 = COPY $q1_q2_q3
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}
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ST4i64 $q1_q2_q3_q4, 0, $x0
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...
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@ -1,80 +0,0 @@
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# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
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# RUN: llc -mtriple=aarch64-apple-ios -run-pass=greedy -run-pass=virtregrewriter %s -o - | FileCheck %s
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---
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name: func0
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body: |
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bb.0:
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; Make sure we don't clobber q3 when we expand the bundle
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; CHECK-LABEL: name: func0
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; CHECK: $x0 = IMPLICIT_DEF
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; CHECK: $q0_q1_q2_q3 = IMPLICIT_DEF
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; CHECK: $q4 = COPY $q3
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; CHECK: $q1_q2_q3 = COPY $q0_q1_q2
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; CHECK: ST4i64 $q1_q2_q3_q4, 0, $x0
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$x0 = IMPLICIT_DEF
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$q0_q1_q2_q3 = IMPLICIT_DEF
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$q1_q2_q3 = COPY $q0_q1_q2 {
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$q4 = COPY $q3
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}
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ST4i64 $q1_q2_q3_q4, 0, $x0
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...
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---
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name: func1
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body: |
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bb.0:
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; If it was already ordered, make sure we don't break it
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; CHECK-LABEL: name: func1
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; CHECK: $x0 = IMPLICIT_DEF
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; CHECK: $q0_q1_q2_q3 = IMPLICIT_DEF
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; CHECK: $q4 = COPY $q3
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; CHECK: $q1_q2_q3 = COPY $q0_q1_q2
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; CHECK: ST4i64 $q1_q2_q3_q4, 0, $x0
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$x0 = IMPLICIT_DEF
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$q0_q1_q2_q3 = IMPLICIT_DEF
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$q4 = COPY $q3 {
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$q1_q2_q3 = COPY $q0_q1_q2
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}
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ST4i64 $q1_q2_q3_q4, 0, $x0
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...
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---
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name: func2
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body: |
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bb.0:
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; A bit less realistic, but check that we handle multiple nodes
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; CHECK-LABEL: name: func2
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; CHECK: $x0 = IMPLICIT_DEF
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; CHECK: $q0_q1_q2_q3 = IMPLICIT_DEF
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; CHECK: $q3 = COPY $q2
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; CHECK: $q4 = COPY $q1
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; CHECK: $q1_q2 = COPY $q0_q1
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; CHECK: ST4i64 $q1_q2_q3_q4, 0, $x0
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$x0 = IMPLICIT_DEF
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$q0_q1_q2_q3 = IMPLICIT_DEF
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$q1_q2 = COPY $q0_q1 {
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$q3 = COPY $q2
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$q4 = COPY $q1
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}
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ST4i64 $q1_q2_q3_q4, 0, $x0
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...
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---
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name: func3
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body: |
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bb.0:
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; If there was nothing wrong, don't change the order for no reason
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; CHECK-LABEL: name: func3
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; CHECK: $x0 = IMPLICIT_DEF
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; CHECK: $q1_q2_q3_q4 = IMPLICIT_DEF
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; CHECK: $q0_q1 = COPY $q1_q2
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; CHECK: $q2_q3 = COPY $q3_q4
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; CHECK: ST4i64 $q0_q1_q2_q3, 0, $x0
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$x0 = IMPLICIT_DEF
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$q1_q2_q3_q4 = IMPLICIT_DEF
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$q0_q1 = COPY $q1_q2 {
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$q2_q3 = COPY $q3_q4
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}
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ST4i64 $q0_q1_q2_q3, 0, $x0
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...
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