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[WebAssembly] SIMD extract_lane
Implement instruction selection for all versions of the extract_lane instruction. Use explicit sext/zext to differentiate between extract_lane_s and extract_lane_u for applicable types, otherwise default to extract_lane_u. Reviewers: aheejin Subscribers: sunfish, jgravelle-google, sbc100, llvm-commits Differential Revision: https://reviews.llvm.org/D50597 Patch by Thomas Lively (tlively) llvm-svn: 339707
This commit is contained in:
Heejin Ahn
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8add466d59
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0706bd283b
@ -12,19 +12,79 @@
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///
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//===----------------------------------------------------------------------===//
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let Defs = [ARGUMENTS] in {
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// Immediate argument types
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def ImmByte : ImmLeaf<i32, [{ return 0 <= Imm && Imm < 256; }]>;
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foreach SIZE = [2, 4, 8, 16, 32] in
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def LaneIdx#SIZE : ImmLeaf<i32, "return 0 <= Imm && Imm < "#SIZE#";">;
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// lane extraction
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multiclass ExtractLane<ValueType vec_t, ImmLeaf imm_t,
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WebAssemblyRegClass reg_t, string name, bits<32> simdop,
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SDNode extract = vector_extract> {
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defm "" : SIMD_I<(outs reg_t:$dst), (ins V128:$vec, I32:$idx),
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(outs), (ins I32:$idx),
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[(set reg_t:$dst,
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(extract (vec_t V128:$vec), (i32 imm_t:$idx)))],
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name#"\t$dst, $vec, $idx", name#"\t$idx", simdop>;
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}
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multiclass ExtractPat<ValueType lane_t, int mask> {
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def _s : PatFrag<(ops node:$vec, node:$idx),
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(i32 (sext_inreg
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(i32 (vector_extract
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node:$vec,
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node:$idx
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)),
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lane_t
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))>;
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def _u : PatFrag<(ops node:$vec, node:$idx),
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(i32 (and
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(i32 (vector_extract
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node:$vec,
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node:$idx
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)),
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(i32 mask)
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))>;
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}
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defm extract_i8x16 : ExtractPat<i8, 0xff>;
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defm extract_i16x8 : ExtractPat<i16, 0xffff>;
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multiclass ExtractLaneExtended<string sign, bits<32> baseInst> {
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defm _I8x16 : ExtractLane<v16i8, LaneIdx16, I32, "i8x16.extract_lane"#sign,
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baseInst, !cast<PatFrag>("extract_i8x16"#sign)>;
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defm _I16x8 : ExtractLane<v8i16, LaneIdx8, I32, "i16x8.extract_lane"#sign,
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!add(baseInst, 2),
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!cast<PatFrag>("extract_i16x8"#sign)>;
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}
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let Defs = [ARGUMENTS] in {
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defm EXTRACT_LANE_S : ExtractLaneExtended<"_s", 9>;
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defm EXTRACT_LANE_U : ExtractLaneExtended<"_u", 10>;
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defm EXTRACT_LANE_I32x4 :
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ExtractLane<v4i32, LaneIdx4, I32, "i32x4.extract_lane", 13>;
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defm EXTRACT_LANE_I64x2 :
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ExtractLane<v2i64, LaneIdx2, I64, "i64x2.extract_lane", 14>;
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defm EXTRACT_LANE_F32x4 :
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ExtractLane<v4f32, LaneIdx4, F32, "f32x4.extract_lane", 15>;
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defm EXTRACT_LANE_F64x2 :
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ExtractLane<v2f64, LaneIdx2, F64, "f64x2.extract_lane", 16>;
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} // Defs = [ARGUMENTS]
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// follow convention of making implicit expansions unsigned
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def : Pat<(i32 (vector_extract (v16i8 V128:$vec), (i32 LaneIdx16:$idx))),
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(EXTRACT_LANE_U_I8x16 V128:$vec, (i32 LaneIdx16:$idx))>;
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def : Pat<(i32 (vector_extract (v8i16 V128:$vec), (i32 LaneIdx8:$idx))),
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(EXTRACT_LANE_U_I16x8 V128:$vec, (i32 LaneIdx8:$idx))>;
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// arithmetic
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let Defs = [ARGUMENTS] in {
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let isCommutable = 1 in
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defm ADD : SIMDBinaryInt<add, "add ", 24>;
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defm SUB : SIMDBinaryInt<sub, "sub ", 28>;
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let isCommutable = 1 in
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defm MUL : SIMDBinaryInt<mul, "mul ", 32>;
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let isCommutable = 1 in
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defm ADD : SIMDBinaryFP<fadd, "add ", 122>;
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defm SUB : SIMDBinaryFP<fsub, "sub ", 124>;
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defm DIV : SIMDBinaryFP<fdiv, "div ", 126>;
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let isCommutable = 1 in
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defm MUL : SIMDBinaryFP<fmul, "mul ", 128>;
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} // Defs = [ARGUMENTS]
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142
test/CodeGen/WebAssembly/simd.ll
Normal file
142
test/CodeGen/WebAssembly/simd.ll
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@ -0,0 +1,142 @@
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; RUN: llc < %s -asm-verbose=false -disable-wasm-fallthrough-return-opt -disable-wasm-explicit-locals -wasm-enable-unimplemented-simd -mattr=+simd128,+sign-ext | FileCheck %s --check-prefixes CHECK,SIMD128
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; RUN: llc < %s -asm-verbose=false -disable-wasm-fallthrough-return-opt -disable-wasm-explicit-locals -mattr=+simd128,+sign-ext | FileCheck %s --check-prefixes CHECK,SIMD128-VM
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; RUN: llc < %s -asm-verbose=false -disable-wasm-fallthrough-return-opt -disable-wasm-explicit-locals -mattr=-simd128,+sign-ext | FileCheck %s --check-prefixes CHECK,NO-SIMD128
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; Test that basic SIMD128 vector manipulation operations assemble as expected.
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target datalayout = "e-m:e-p:32:32-i64:64-n32:64-S128"
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target triple = "wasm32-unknown-unknown"
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; ==============================================================================
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; 16 x i8
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; ==============================================================================
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; CHECK-LABEL: extract_v16i8_s:{{$}}
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; NO-SIMD128-NOT: i8x16
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; SIMD128: .param v128{{$}}
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; SIMD128: .result i32{{$}}
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; SIMD128: i8x16.extract_lane_s $push0=, $0, 13{{$}}
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; SIMD128: return $pop0{{$}}
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define i32 @extract_v16i8_s(<16 x i8> %v) {
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%elem = extractelement <16 x i8> %v, i8 13
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%a = sext i8 %elem to i32
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ret i32 %a
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}
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; CHECK-LABEL: extract_v16i8_u:{{$}}
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; NO-SIMD128-NOT: i8x16
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; SIMD128: .param v128{{$}}
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; SIMD128: .result i32{{$}}
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; SIMD128: i8x16.extract_lane_u $push0=, $0, 13{{$}}
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; SIMD128: return $pop0{{$}}
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define i32 @extract_v16i8_u(<16 x i8> %v) {
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%elem = extractelement <16 x i8> %v, i8 13
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%a = zext i8 %elem to i32
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ret i32 %a
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}
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; CHECK-LABEL: extract_v16i8:{{$}}
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; NO-SIMD128-NOT: i8x16
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; SIMD128: .param v128{{$}}
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; SIMD128: .result i32{{$}}
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; SIMD128: i8x16.extract_lane_u $push0=, $0, 13{{$}}
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; SIMD128: return $pop0{{$}}
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define i8 @extract_v16i8(<16 x i8> %v) {
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%elem = extractelement <16 x i8> %v, i8 13
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ret i8 %elem
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}
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; ==============================================================================
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; 8 x i16
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; ==============================================================================
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; CHECK-LABEL: extract_v8i16_s:{{$}}
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; NO-SIMD128-NOT: i16x8
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; SIMD128: .param v128{{$}}
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; SIMD128: .result i32{{$}}
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; SIMD128: i16x8.extract_lane_s $push0=, $0, 5{{$}}
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; SIMD128: return $pop0{{$}}
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define i32 @extract_v8i16_s(<8 x i16> %v) {
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%elem = extractelement <8 x i16> %v, i16 5
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%a = sext i16 %elem to i32
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ret i32 %a
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}
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; CHECK-LABEL: extract_v8i16_u:{{$}}
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; NO-SIMD128-NOT: i16x8
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; SIMD128: .param v128{{$}}
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; SIMD128: .result i32{{$}}
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; SIMD128: i16x8.extract_lane_u $push0=, $0, 5{{$}}
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; SIMD128: return $pop0{{$}}
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define i32 @extract_v8i16_u(<8 x i16> %v) {
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%elem = extractelement <8 x i16> %v, i16 5
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%a = zext i16 %elem to i32
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ret i32 %a
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}
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; CHECK-LABEL: extract_v8i16:{{$}}
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; NO-SIMD128-NOT: i16x8
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; SIMD128: .param v128{{$}}
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; SIMD128: .result i32{{$}}
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; SIMD128: i16x8.extract_lane_u $push0=, $0, 5{{$}}
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; SIMD128: return $pop0{{$}}
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define i16 @extract_v8i16(<8 x i16> %v) {
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%elem = extractelement <8 x i16> %v, i16 5
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ret i16 %elem
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}
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; ==============================================================================
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; 4 x i32
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; ==============================================================================
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; CHECK-LABEL: extract_v4i32:{{$}}
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; NO-SIMD128-NOT: i32x4
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; SIMD128: .param v128{{$}}
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; SIMD128: .result i32{{$}}
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; SIMD128: i32x4.extract_lane $push0=, $0, 3{{$}}
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; SIMD128: return $pop0{{$}}
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define i32 @extract_v4i32(<4 x i32> %v) {
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%elem = extractelement <4 x i32> %v, i32 3
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ret i32 %elem
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}
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; ==============================================================================
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; 2 x i64
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; ==============================================================================
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; CHECK-LABEL: extract_v2i64:{{$}}
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; NO-SIMD128-NOT: i64x2
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; SIMD128-VM-NOT: i64x2
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; SIMD128: .param v128{{$}}
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; SIMD128: .result i64{{$}}
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; SIMD128: i64x2.extract_lane $push0=, $0, 1{{$}}
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; SIMD128: return $pop0{{$}}
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define i64 @extract_v2i64(<2 x i64> %v) {
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%elem = extractelement <2 x i64> %v, i64 1
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ret i64 %elem
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}
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; ==============================================================================
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; 4 x f32
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; ==============================================================================
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; CHECK-LABEL: extract_v4f32:{{$}}
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; NO-SIMD128-NOT: f32x4
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; SIMD128: .param v128{{$}}
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; SIMD128: .result f32{{$}}
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; SIMD128: f32x4.extract_lane $push0=, $0, 3{{$}}
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; SIMD128: return $pop0{{$}}
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define float @extract_v4f32(<4 x float> %v) {
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%elem = extractelement <4 x float> %v, i32 3
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ret float %elem
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}
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; ==============================================================================
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; 2 x f64
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; ==============================================================================
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; CHECK-LABEL: extract_v2f64:{{$}}
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; NO-SIMD128-NOT: f64x2
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; SIMD128-VM-NOT: f64x2
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; SIMD128: .param v128{{$}}
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; SIMD128: .result f64{{$}}
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; SIMD128: f64x2.extract_lane $push0=, $0, 1{{$}}
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; SIMD128: return $pop0{{$}}
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define double @extract_v2f64(<2 x double> %v) {
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%elem = extractelement <2 x double> %v, i32 1
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ret double %elem
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}
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