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[SystemZ] Support vector load/store alignment hints
Vector load/store instructions support an optional alignment field that the compiler can use to provide known alignment info to the hardware. If the field is used (and the information is correct), the hardware may be able (on some models) to perform faster memory accesses than otherwise. This patch adds support for alignment hints in the assembler and disassembler, and fills in known alignment during codegen. llvm-svn: 363806
This commit is contained in:
Ulrich Weigand
parent
395d3c6fd7
commit
07186d14a9
@ -80,6 +80,27 @@ static const MCSymbolRefExpr *getGlobalOffsetTable(MCContext &Context) {
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Context);
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}
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// MI is an instruction that accepts an optional alignment hint,
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// and which was already lowered to LoweredMI. If the alignment
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// of the original memory operand is known, update LoweredMI to
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// an instruction with the corresponding hint set.
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static void lowerAlignmentHint(const MachineInstr *MI, MCInst &LoweredMI,
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unsigned Opcode) {
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if (!MI->hasOneMemOperand())
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return;
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const MachineMemOperand *MMO = *MI->memoperands_begin();
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unsigned AlignmentHint = 0;
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if (MMO->getAlignment() >= 16)
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AlignmentHint = 4;
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else if (MMO->getAlignment() >= 8)
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AlignmentHint = 3;
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if (AlignmentHint == 0)
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return;
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LoweredMI.setOpcode(Opcode);
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LoweredMI.addOperand(MCOperand::createImm(AlignmentHint));
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}
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// MI loads the high part of a vector from memory. Return an instruction
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// that uses replicating vector load Opcode to do the same thing.
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static MCInst lowerSubvectorLoad(const MachineInstr *MI, unsigned Opcode) {
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@ -351,6 +372,26 @@ void SystemZAsmPrinter::EmitInstruction(const MachineInstr *MI) {
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.addReg(SystemZMC::getRegAsVR128(MI->getOperand(1).getReg()));
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break;
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case SystemZ::VL:
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Lower.lower(MI, LoweredMI);
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lowerAlignmentHint(MI, LoweredMI, SystemZ::VLAlign);
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break;
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case SystemZ::VST:
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Lower.lower(MI, LoweredMI);
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lowerAlignmentHint(MI, LoweredMI, SystemZ::VSTAlign);
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break;
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case SystemZ::VLM:
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Lower.lower(MI, LoweredMI);
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lowerAlignmentHint(MI, LoweredMI, SystemZ::VLMAlign);
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break;
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case SystemZ::VSTM:
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Lower.lower(MI, LoweredMI);
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lowerAlignmentHint(MI, LoweredMI, SystemZ::VSTMAlign);
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break;
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case SystemZ::VL32:
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LoweredMI = lowerSubvectorLoad(MI, SystemZ::VLREPF);
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break;
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@ -2425,11 +2425,16 @@ class LoadMultipleSSe<string mnemonic, bits<8> opcode, RegisterOperand cls>
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let mayLoad = 1;
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}
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class LoadMultipleVRSa<string mnemonic, bits<16> opcode>
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: InstVRSa<opcode, (outs VR128:$V1, VR128:$V3), (ins bdaddr12only:$BD2),
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mnemonic#"\t$V1, $V3, $BD2", []> {
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let M4 = 0;
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let mayLoad = 1;
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multiclass LoadMultipleVRSaAlign<string mnemonic, bits<16> opcode> {
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let mayLoad = 1 in {
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def Align : InstVRSa<opcode, (outs VR128:$V1, VR128:$V3),
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(ins bdaddr12only:$BD2, imm32zx4:$M4),
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mnemonic#"\t$V1, $V3, $BD2, $M4", []>;
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let M4 = 0 in
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def "" : InstVRSa<opcode, (outs VR128:$V1, VR128:$V3),
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(ins bdaddr12only:$BD2),
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mnemonic#"\t$V1, $V3, $BD2", []>;
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}
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}
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class StoreRILPC<string mnemonic, bits<12> opcode, SDPatternOperator operator,
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@ -2490,6 +2495,17 @@ class StoreVRX<string mnemonic, bits<16> opcode, SDPatternOperator operator,
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let AccessBytes = bytes;
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}
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multiclass StoreVRXAlign<string mnemonic, bits<16> opcode> {
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let mayStore = 1, AccessBytes = 16 in {
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def Align : InstVRX<opcode, (outs),
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(ins VR128:$V1, bdxaddr12only:$XBD2, imm32zx4:$M3),
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mnemonic#"\t$V1, $XBD2, $M3", []>;
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let M3 = 0 in
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def "" : InstVRX<opcode, (outs), (ins VR128:$V1, bdxaddr12only:$XBD2),
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mnemonic#"\t$V1, $XBD2", []>;
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}
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}
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class StoreLengthVRSb<string mnemonic, bits<16> opcode,
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SDPatternOperator operator, bits<5> bytes>
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: InstVRSb<opcode, (outs), (ins VR128:$V1, GR32:$R3, bdaddr12only:$BD2),
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@ -2542,11 +2558,16 @@ multiclass StoreMultipleRSPair<string mnemonic, bits<8> rsOpcode,
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}
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}
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class StoreMultipleVRSa<string mnemonic, bits<16> opcode>
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: InstVRSa<opcode, (outs), (ins VR128:$V1, VR128:$V3, bdaddr12only:$BD2),
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mnemonic#"\t$V1, $V3, $BD2", []> {
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let M4 = 0;
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let mayStore = 1;
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multiclass StoreMultipleVRSaAlign<string mnemonic, bits<16> opcode> {
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let mayStore = 1 in {
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def Align : InstVRSa<opcode, (outs), (ins VR128:$V1, VR128:$V3,
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bdaddr12only:$BD2, imm32zx4:$M4),
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mnemonic#"\t$V1, $V3, $BD2, $M4", []>;
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let M4 = 0 in
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def "" : InstVRSa<opcode, (outs), (ins VR128:$V1, VR128:$V3,
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bdaddr12only:$BD2),
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mnemonic#"\t$V1, $V3, $BD2", []>;
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}
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}
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// StoreSI* instructions are used to store an integer to memory, but the
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@ -2940,6 +2961,17 @@ class UnaryVRXGeneric<string mnemonic, bits<16> opcode>
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let mayLoad = 1;
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}
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multiclass UnaryVRXAlign<string mnemonic, bits<16> opcode> {
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let mayLoad = 1, AccessBytes = 16 in {
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def Align : InstVRX<opcode, (outs VR128:$V1),
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(ins bdxaddr12only:$XBD2, imm32zx4:$M3),
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mnemonic#"\t$V1, $XBD2, $M3", []>;
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let M3 = 0 in
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def "" : InstVRX<opcode, (outs VR128:$V1), (ins bdxaddr12only:$XBD2),
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mnemonic#"\t$V1, $XBD2", []>;
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}
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}
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class SideEffectBinaryRX<string mnemonic, bits<8> opcode,
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RegisterOperand cls>
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: InstRXa<opcode, (outs), (ins cls:$R1, bdxaddr12only:$XBD2),
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@ -103,7 +103,7 @@ let Predicates = [FeatureVector] in {
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let Predicates = [FeatureVector] in {
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// Load.
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def VL : UnaryVRX<"vl", 0xE706, null_frag, v128any, 16>;
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defm VL : UnaryVRXAlign<"vl", 0xE706>;
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// Load to block boundary. The number of loaded bytes is only known
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// at run time. The instruction is really polymorphic, but v128b matches
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@ -122,7 +122,7 @@ let Predicates = [FeatureVector] in {
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def VLL : BinaryVRSb<"vll", 0xE737, int_s390_vll, 0>;
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// Load multiple.
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def VLM : LoadMultipleVRSa<"vlm", 0xE736>;
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defm VLM : LoadMultipleVRSaAlign<"vlm", 0xE736>;
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// Load and replicate
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def VLREP : UnaryVRXGeneric<"vlrep", 0xE705>;
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@ -207,13 +207,13 @@ defm : ReplicatePeephole<VLREPG, v2f64, load, f64>;
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let Predicates = [FeatureVector] in {
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// Store.
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def VST : StoreVRX<"vst", 0xE70E, null_frag, v128any, 16>;
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defm VST : StoreVRXAlign<"vst", 0xE70E>;
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// Store with length. The number of stored bytes is only known at run time.
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def VSTL : StoreLengthVRSb<"vstl", 0xE73F, int_s390_vstl, 0>;
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// Store multiple.
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def VSTM : StoreMultipleVRSa<"vstm", 0xE73E>;
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defm VSTM : StoreMultipleVRSaAlign<"vstm", 0xE73E>;
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// Store element.
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def VSTEB : StoreBinaryVRX<"vsteb", 0xE708, z_vstei8, v128b, 1, imm32zx4>;
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@ -1191,8 +1191,8 @@ def : InstRW<[WLat2, VecXsPm, NormalGr], (instregex "VLEI(B|F|G|H)$")>;
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// Vector: Loads
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//===----------------------------------------------------------------------===//
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def : InstRW<[LSULatency, LSU, NormalGr], (instregex "VL(BB)?$")>;
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def : InstRW<[LSULatency, LSU, NormalGr], (instregex "VLL$")>;
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def : InstRW<[LSULatency, LSU, NormalGr], (instregex "VL(Align)?$")>;
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def : InstRW<[LSULatency, LSU, NormalGr], (instregex "VL(L|BB)$")>;
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def : InstRW<[LSULatency, LSU, NormalGr], (instregex "VL(32|64)$")>;
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def : InstRW<[LSULatency, LSU, NormalGr], (instregex "VLLEZ(B|F|G|H)?$")>;
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def : InstRW<[LSULatency, LSU, NormalGr], (instregex "VLREP(B|F|G|H)?$")>;
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@ -1200,16 +1200,17 @@ def : InstRW<[WLat2LSU, RegReadAdv, VecXsPm, LSU, NormalGr],
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(instregex "VLE(B|F|G|H)$")>;
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def : InstRW<[WLat6LSU, RegReadAdv, FXb, LSU, VecXsPm, Cracked],
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(instregex "VGE(F|G)$")>;
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def : InstRW<[WLat4LSU, WLat4LSU, LSU5, GroupAlone], (instregex "VLM$")>;
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def : InstRW<[WLat4LSU, WLat4LSU, LSU5, GroupAlone],
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(instregex "VLM(Align)?$")>;
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//===----------------------------------------------------------------------===//
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// Vector: Stores
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//===----------------------------------------------------------------------===//
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def : InstRW<[WLat1, FXb, LSU, NormalGr], (instregex "VST(L|32|64)?$")>;
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def : InstRW<[WLat1, FXb, LSU, NormalGr], (instregex "VST(Align|L|32|64)?$")>;
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def : InstRW<[WLat1, FXb, LSU, NormalGr], (instregex "VSTE(F|G)$")>;
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def : InstRW<[WLat1, FXb, LSU, VecXsPm, Cracked], (instregex "VSTE(B|H)$")>;
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def : InstRW<[WLat1, LSU2, FXb3, GroupAlone2], (instregex "VSTM$")>;
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def : InstRW<[WLat1, LSU2, FXb3, GroupAlone2], (instregex "VSTM(Align)?$")>;
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def : InstRW<[WLat1, FXb2, LSU, Cracked], (instregex "VSCE(F|G)$")>;
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//===----------------------------------------------------------------------===//
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@ -1209,8 +1209,8 @@ def : InstRW<[WLat2, VecXsPm, NormalGr], (instregex "VLEI(B|F|G|H)$")>;
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// Vector: Loads
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//===----------------------------------------------------------------------===//
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def : InstRW<[LSULatency, LSU, NormalGr], (instregex "VL(BB)?$")>;
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def : InstRW<[LSULatency, LSU, NormalGr], (instregex "VLL$")>;
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def : InstRW<[LSULatency, LSU, NormalGr], (instregex "VL(Align)?$")>;
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def : InstRW<[LSULatency, LSU, NormalGr], (instregex "VL(L|BB)$")>;
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def : InstRW<[LSULatency, LSU, NormalGr], (instregex "VL(32|64)$")>;
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def : InstRW<[LSULatency, LSU, NormalGr], (instregex "VLLEZ(B|F|G|H|LF)?$")>;
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def : InstRW<[LSULatency, LSU, NormalGr], (instregex "VLREP(B|F|G|H)?$")>;
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@ -1218,17 +1218,18 @@ def : InstRW<[WLat2LSU, RegReadAdv, VecXsPm, LSU, NormalGr],
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(instregex "VLE(B|F|G|H)$")>;
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def : InstRW<[WLat5LSU, RegReadAdv, FXb, LSU, VecXsPm, Cracked],
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(instregex "VGE(F|G)$")>;
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def : InstRW<[WLat4LSU, WLat4LSU, LSU5, GroupAlone], (instregex "VLM$")>;
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def : InstRW<[WLat4LSU, WLat4LSU, LSU5, GroupAlone],
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(instregex "VLM(Align)?$")>;
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def : InstRW<[LSULatency, LSU, NormalGr], (instregex "VLRL(R)?$")>;
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//===----------------------------------------------------------------------===//
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// Vector: Stores
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//===----------------------------------------------------------------------===//
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def : InstRW<[WLat1, FXb, LSU, NormalGr], (instregex "VST(L|32|64)?$")>;
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def : InstRW<[WLat1, FXb, LSU, NormalGr], (instregex "VST(Align|L|32|64)?$")>;
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def : InstRW<[WLat1, FXb, LSU, NormalGr], (instregex "VSTE(F|G)$")>;
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def : InstRW<[WLat1, FXb, LSU, VecXsPm, Cracked], (instregex "VSTE(B|H)$")>;
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def : InstRW<[WLat1, LSU2, FXb3, GroupAlone2], (instregex "VSTM$")>;
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def : InstRW<[WLat1, LSU2, FXb3, GroupAlone2], (instregex "VSTM(Align)?$")>;
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def : InstRW<[WLat1, FXb2, LSU, Cracked], (instregex "VSCE(F|G)$")>;
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def : InstRW<[WLat1, FXb, LSU, NormalGr], (instregex "VSTRL(R)?$")>;
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@ -15,8 +15,8 @@ define void @f1(<16 x i8> *%ptr) {
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; CHECK-DAG: std %f13,
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; CHECK-DAG: std %f14,
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; CHECK-DAG: std %f15,
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; CHECK: vst {{%v[0-9]+}}, 160(%r15)
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; CHECK: vl {{%v[0-9]+}}, 160(%r15)
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; CHECK: vst {{%v[0-9]+}}, 160(%r15), 3
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; CHECK: vl {{%v[0-9]+}}, 160(%r15), 3
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; CHECK-DAG: ld %f8,
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; CHECK-DAG: ld %f9,
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; CHECK-DAG: ld %f10,
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@ -5,7 +5,7 @@
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; Test v16i8 loads.
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define <16 x i8> @f1(<16 x i8> *%ptr) {
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; CHECK-LABEL: f1:
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; CHECK: vl %v24, 0(%r2)
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; CHECK: vl %v24, 0(%r2), 3
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; CHECK: br %r14
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%ret = load <16 x i8>, <16 x i8> *%ptr
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ret <16 x i8> %ret
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@ -14,7 +14,7 @@ define <16 x i8> @f1(<16 x i8> *%ptr) {
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; Test v8i16 loads.
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define <8 x i16> @f2(<8 x i16> *%ptr) {
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; CHECK-LABEL: f2:
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; CHECK: vl %v24, 0(%r2)
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; CHECK: vl %v24, 0(%r2), 3
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; CHECK: br %r14
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%ret = load <8 x i16>, <8 x i16> *%ptr
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ret <8 x i16> %ret
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@ -23,7 +23,7 @@ define <8 x i16> @f2(<8 x i16> *%ptr) {
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; Test v4i32 loads.
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define <4 x i32> @f3(<4 x i32> *%ptr) {
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; CHECK-LABEL: f3:
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; CHECK: vl %v24, 0(%r2)
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; CHECK: vl %v24, 0(%r2), 3
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; CHECK: br %r14
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%ret = load <4 x i32>, <4 x i32> *%ptr
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ret <4 x i32> %ret
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@ -32,7 +32,7 @@ define <4 x i32> @f3(<4 x i32> *%ptr) {
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; Test v2i64 loads.
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define <2 x i64> @f4(<2 x i64> *%ptr) {
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; CHECK-LABEL: f4:
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; CHECK: vl %v24, 0(%r2)
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; CHECK: vl %v24, 0(%r2), 3
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; CHECK: br %r14
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%ret = load <2 x i64>, <2 x i64> *%ptr
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ret <2 x i64> %ret
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@ -41,7 +41,7 @@ define <2 x i64> @f4(<2 x i64> *%ptr) {
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; Test v4f32 loads.
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define <4 x float> @f5(<4 x float> *%ptr) {
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; CHECK-LABEL: f5:
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; CHECK: vl %v24, 0(%r2)
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; CHECK: vl %v24, 0(%r2), 3
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; CHECK: br %r14
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%ret = load <4 x float>, <4 x float> *%ptr
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ret <4 x float> %ret
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@ -50,7 +50,7 @@ define <4 x float> @f5(<4 x float> *%ptr) {
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; Test v2f64 loads.
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define <2 x double> @f6(<2 x double> *%ptr) {
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; CHECK-LABEL: f6:
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; CHECK: vl %v24, 0(%r2)
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; CHECK: vl %v24, 0(%r2), 3
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; CHECK: br %r14
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%ret = load <2 x double>, <2 x double> *%ptr
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ret <2 x double> %ret
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@ -59,7 +59,7 @@ define <2 x double> @f6(<2 x double> *%ptr) {
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; Test the highest aligned in-range offset.
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define <16 x i8> @f7(<16 x i8> *%base) {
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; CHECK-LABEL: f7:
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; CHECK: vl %v24, 4080(%r2)
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; CHECK: vl %v24, 4080(%r2), 3
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; CHECK: br %r14
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%ptr = getelementptr <16 x i8>, <16 x i8> *%base, i64 255
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%ret = load <16 x i8>, <16 x i8> *%ptr
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@ -81,7 +81,7 @@ define <16 x i8> @f8(i8 *%base) {
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define <16 x i8> @f9(<16 x i8> *%base) {
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; CHECK-LABEL: f9:
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; CHECK: aghi %r2, 4096
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; CHECK: vl %v24, 0(%r2)
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; CHECK: vl %v24, 0(%r2), 3
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; CHECK: br %r14
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%ptr = getelementptr <16 x i8>, <16 x i8> *%base, i64 256
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%ret = load <16 x i8>, <16 x i8> *%ptr
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@ -92,7 +92,7 @@ define <16 x i8> @f9(<16 x i8> *%base) {
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define <16 x i8> @f10(<16 x i8> *%base) {
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; CHECK-LABEL: f10:
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; CHECK: aghi %r2, -16
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; CHECK: vl %v24, 0(%r2)
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; CHECK: vl %v24, 0(%r2), 3
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; CHECK: br %r14
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%ptr = getelementptr <16 x i8>, <16 x i8> *%base, i64 -1
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%ret = load <16 x i8>, <16 x i8> *%ptr
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@ -172,3 +172,13 @@ define <2 x float> @f18(<2 x float> *%ptr) {
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%ret = load <2 x float>, <2 x float> *%ptr
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ret <2 x float> %ret
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}
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; Test quadword-aligned loads.
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define <16 x i8> @f19(<16 x i8> *%ptr) {
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; CHECK-LABEL: f19:
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||||
; CHECK: vl %v24, 0(%r2), 4
|
||||
; CHECK: br %r14
|
||||
%ret = load <16 x i8>, <16 x i8> *%ptr, align 16
|
||||
ret <16 x i8> %ret
|
||||
}
|
||||
|
||||
|
||||
@ -5,7 +5,7 @@
|
||||
; Test v16i8 stores.
|
||||
define void @f1(<16 x i8> %val, <16 x i8> *%ptr) {
|
||||
; CHECK-LABEL: f1:
|
||||
; CHECK: vst %v24, 0(%r2)
|
||||
; CHECK: vst %v24, 0(%r2), 3
|
||||
; CHECK: br %r14
|
||||
store <16 x i8> %val, <16 x i8> *%ptr
|
||||
ret void
|
||||
@ -14,7 +14,7 @@ define void @f1(<16 x i8> %val, <16 x i8> *%ptr) {
|
||||
; Test v8i16 stores.
|
||||
define void @f2(<8 x i16> %val, <8 x i16> *%ptr) {
|
||||
; CHECK-LABEL: f2:
|
||||
; CHECK: vst %v24, 0(%r2)
|
||||
; CHECK: vst %v24, 0(%r2), 3
|
||||
; CHECK: br %r14
|
||||
store <8 x i16> %val, <8 x i16> *%ptr
|
||||
ret void
|
||||
@ -23,7 +23,7 @@ define void @f2(<8 x i16> %val, <8 x i16> *%ptr) {
|
||||
; Test v4i32 stores.
|
||||
define void @f3(<4 x i32> %val, <4 x i32> *%ptr) {
|
||||
; CHECK-LABEL: f3:
|
||||
; CHECK: vst %v24, 0(%r2)
|
||||
; CHECK: vst %v24, 0(%r2), 3
|
||||
; CHECK: br %r14
|
||||
store <4 x i32> %val, <4 x i32> *%ptr
|
||||
ret void
|
||||
@ -32,7 +32,7 @@ define void @f3(<4 x i32> %val, <4 x i32> *%ptr) {
|
||||
; Test v2i64 stores.
|
||||
define void @f4(<2 x i64> %val, <2 x i64> *%ptr) {
|
||||
; CHECK-LABEL: f4:
|
||||
; CHECK: vst %v24, 0(%r2)
|
||||
; CHECK: vst %v24, 0(%r2), 3
|
||||
; CHECK: br %r14
|
||||
store <2 x i64> %val, <2 x i64> *%ptr
|
||||
ret void
|
||||
@ -41,7 +41,7 @@ define void @f4(<2 x i64> %val, <2 x i64> *%ptr) {
|
||||
; Test v4f32 stores.
|
||||
define void @f5(<4 x float> %val, <4 x float> *%ptr) {
|
||||
; CHECK-LABEL: f5:
|
||||
; CHECK: vst %v24, 0(%r2)
|
||||
; CHECK: vst %v24, 0(%r2), 3
|
||||
; CHECK: br %r14
|
||||
store <4 x float> %val, <4 x float> *%ptr
|
||||
ret void
|
||||
@ -50,7 +50,7 @@ define void @f5(<4 x float> %val, <4 x float> *%ptr) {
|
||||
; Test v2f64 stores.
|
||||
define void @f6(<2 x double> %val, <2 x double> *%ptr) {
|
||||
; CHECK-LABEL: f6:
|
||||
; CHECK: vst %v24, 0(%r2)
|
||||
; CHECK: vst %v24, 0(%r2), 3
|
||||
; CHECK: br %r14
|
||||
store <2 x double> %val, <2 x double> *%ptr
|
||||
ret void
|
||||
@ -59,7 +59,7 @@ define void @f6(<2 x double> %val, <2 x double> *%ptr) {
|
||||
; Test the highest aligned in-range offset.
|
||||
define void @f7(<16 x i8> %val, <16 x i8> *%base) {
|
||||
; CHECK-LABEL: f7:
|
||||
; CHECK: vst %v24, 4080(%r2)
|
||||
; CHECK: vst %v24, 4080(%r2), 3
|
||||
; CHECK: br %r14
|
||||
%ptr = getelementptr <16 x i8>, <16 x i8> *%base, i64 255
|
||||
store <16 x i8> %val, <16 x i8> *%ptr
|
||||
@ -81,7 +81,7 @@ define void @f8(<16 x i8> %val, i8 *%base) {
|
||||
define void @f9(<16 x i8> %val, <16 x i8> *%base) {
|
||||
; CHECK-LABEL: f9:
|
||||
; CHECK: aghi %r2, 4096
|
||||
; CHECK: vst %v24, 0(%r2)
|
||||
; CHECK: vst %v24, 0(%r2), 3
|
||||
; CHECK: br %r14
|
||||
%ptr = getelementptr <16 x i8>, <16 x i8> *%base, i64 256
|
||||
store <16 x i8> %val, <16 x i8> *%ptr
|
||||
@ -92,7 +92,7 @@ define void @f9(<16 x i8> %val, <16 x i8> *%base) {
|
||||
define void @f10(<16 x i8> %val, <16 x i8> *%base) {
|
||||
; CHECK-LABEL: f10:
|
||||
; CHECK: aghi %r2, -16
|
||||
; CHECK: vst %v24, 0(%r2)
|
||||
; CHECK: vst %v24, 0(%r2), 3
|
||||
; CHECK: br %r14
|
||||
%ptr = getelementptr <16 x i8>, <16 x i8> *%base, i64 -1
|
||||
store <16 x i8> %val, <16 x i8> *%ptr
|
||||
@ -172,3 +172,13 @@ define void @f18(<2 x float> %val, <2 x float> *%ptr) {
|
||||
store <2 x float> %val, <2 x float> *%ptr
|
||||
ret void
|
||||
}
|
||||
|
||||
; Test quadword-aligned stores.
|
||||
define void @f19(<16 x i8> %val, <16 x i8> *%ptr) {
|
||||
; CHECK-LABEL: f19:
|
||||
; CHECK: vst %v24, 0(%r2), 4
|
||||
; CHECK: br %r14
|
||||
store <16 x i8> %val, <16 x i8> *%ptr, align 16
|
||||
ret void
|
||||
}
|
||||
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
@ -2363,6 +2363,9 @@
|
||||
# CHECK: vl %v0, 0
|
||||
0xe7 0x00 0x00 0x00 0x00 0x06
|
||||
|
||||
# CHECK: vl %v0, 0, 4
|
||||
0xe7 0x00 0x00 0x00 0x40 0x06
|
||||
|
||||
# CHECK: vl %v17, 2475(%r7,%r8)
|
||||
0xe7 0x17 0x89 0xab 0x08 0x06
|
||||
|
||||
@ -2633,6 +2636,9 @@
|
||||
# CHECK: vlm %v0, %v0, 0
|
||||
0xe7 0x00 0x00 0x00 0x00 0x36
|
||||
|
||||
# CHECK: vlm %v0, %v0, 0, 4
|
||||
0xe7 0x00 0x00 0x00 0x40 0x36
|
||||
|
||||
# CHECK: vlm %v12, %v18, 1110(%r3)
|
||||
0xe7 0xc2 0x34 0x56 0x04 0x36
|
||||
|
||||
@ -4118,6 +4124,9 @@
|
||||
# CHECK: vst %v0, 0
|
||||
0xe7 0x00 0x00 0x00 0x00 0x0E
|
||||
|
||||
# CHECK: vst %v0, 0, 4
|
||||
0xe7 0x00 0x00 0x00 0x40 0x0E
|
||||
|
||||
# CHECK: vst %v17, 2475(%r7,%r8)
|
||||
0xe7 0x17 0x89 0xab 0x08 0x0E
|
||||
|
||||
@ -4172,6 +4181,9 @@
|
||||
# CHECK: vstm %v0, %v0, 0
|
||||
0xe7 0x00 0x00 0x00 0x00 0x3e
|
||||
|
||||
# CHECK: vstm %v0, %v0, 0, 4
|
||||
0xe7 0x00 0x00 0x00 0x40 0x3e
|
||||
|
||||
# CHECK: vstm %v12, %v18, 1110(%r3)
|
||||
0xe7 0xc2 0x34 0x56 0x04 0x3e
|
||||
|
||||
|
||||
@ -1686,10 +1686,16 @@
|
||||
#CHECK: vl %v0, 4096
|
||||
#CHECK: error: invalid use of vector addressing
|
||||
#CHECK: vl %v0, 0(%v1,%r2)
|
||||
#CHECK: error: invalid operand
|
||||
#CHECK: vl %v0, 0, -1
|
||||
#CHECK: error: invalid operand
|
||||
#CHECK: vl %v0, 0, 16
|
||||
|
||||
vl %v0, -1
|
||||
vl %v0, 4096
|
||||
vl %v0, 0(%v1,%r2)
|
||||
vl %v0, 0, -1
|
||||
vl %v0, 0, 16
|
||||
|
||||
#CHECK: error: invalid operand
|
||||
#CHECK: vlbb %v0, 0, -1
|
||||
@ -2013,9 +2019,15 @@
|
||||
#CHECK: vlm %v0, %v0, -1
|
||||
#CHECK: error: invalid operand
|
||||
#CHECK: vlm %v0, %v0, 4096
|
||||
#CHECK: error: invalid operand
|
||||
#CHECK: vlm %v0, %v0, 0, -1
|
||||
#CHECK: error: invalid operand
|
||||
#CHECK: vlm %v0, %v0, 0, 16
|
||||
|
||||
vlm %v0, %v0, -1
|
||||
vlm %v0, %v0, 4096
|
||||
vlm %v0, %v0, 0, -1
|
||||
vlm %v0, %v0, 0, 16
|
||||
|
||||
#CHECK: error: invalid operand
|
||||
#CHECK: vlrep %v0, 0, -1
|
||||
@ -2380,10 +2392,16 @@
|
||||
#CHECK: vst %v0, 4096
|
||||
#CHECK: error: invalid use of vector addressing
|
||||
#CHECK: vst %v0, 0(%v1,%r2)
|
||||
#CHECK: error: invalid operand
|
||||
#CHECK: vst %v0, 0, -1
|
||||
#CHECK: error: invalid operand
|
||||
#CHECK: vst %v0, 0, 16
|
||||
|
||||
vst %v0, -1
|
||||
vst %v0, 4096
|
||||
vst %v0, 0(%v1,%r2)
|
||||
vst %v0, 0, -1
|
||||
vst %v0, 0, 16
|
||||
|
||||
#CHECK: error: invalid operand
|
||||
#CHECK: vsteb %v0, 0, -1
|
||||
@ -2468,9 +2486,15 @@
|
||||
#CHECK: vstm %v0, %v0, -1
|
||||
#CHECK: error: invalid operand
|
||||
#CHECK: vstm %v0, %v0, 4096
|
||||
#CHECK: error: invalid operand
|
||||
#CHECK: vstm %v0, %v0, 0, -1
|
||||
#CHECK: error: invalid operand
|
||||
#CHECK: vstm %v0, %v0, 0, 16
|
||||
|
||||
vstm %v0, %v0, -1
|
||||
vstm %v0, %v0, 4096
|
||||
vstm %v0, %v0, 0, -1
|
||||
vstm %v0, %v0, 0, 16
|
||||
|
||||
#CHECK: error: invalid operand
|
||||
#CHECK: vstrc %v0, %v0, %v0, %v0, 0, -1
|
||||
|
||||
@ -3215,17 +3215,19 @@
|
||||
#CHECK: vl %v0, 4095 # encoding: [0xe7,0x00,0x0f,0xff,0x00,0x06]
|
||||
#CHECK: vl %v0, 0(%r15) # encoding: [0xe7,0x00,0xf0,0x00,0x00,0x06]
|
||||
#CHECK: vl %v0, 0(%r15,%r1) # encoding: [0xe7,0x0f,0x10,0x00,0x00,0x06]
|
||||
#CHECK: vl %v0, 0(%r15,%r1), 4 # encoding: [0xe7,0x0f,0x10,0x00,0x40,0x06]
|
||||
#CHECK: vl %v15, 0 # encoding: [0xe7,0xf0,0x00,0x00,0x00,0x06]
|
||||
#CHECK: vl %v31, 0 # encoding: [0xe7,0xf0,0x00,0x00,0x08,0x06]
|
||||
#CHECK: vl %v18, 1383(%r3,%r4) # encoding: [0xe7,0x23,0x45,0x67,0x08,0x06]
|
||||
#CHECK: vl %v18, 1383(%r3,%r4), 3 # encoding: [0xe7,0x23,0x45,0x67,0x38,0x06]
|
||||
|
||||
vl %v0, 0
|
||||
vl %v0, 4095
|
||||
vl %v0, 0(%r15)
|
||||
vl %v0, 0(%r15,%r1)
|
||||
vl %v0, 0(%r15,%r1), 4
|
||||
vl %v15, 0
|
||||
vl %v31, 0
|
||||
vl %v18, 0x567(%r3,%r4)
|
||||
vl %v18, 0x567(%r3,%r4), 3
|
||||
|
||||
#CHECK: vlbb %v0, 0, 0 # encoding: [0xe7,0x00,0x00,0x00,0x00,0x07]
|
||||
#CHECK: vlbb %v0, 0, 15 # encoding: [0xe7,0x00,0x00,0x00,0xf0,0x07]
|
||||
@ -3702,16 +3704,18 @@
|
||||
#CHECK: vlm %v0, %v0, 0 # encoding: [0xe7,0x00,0x00,0x00,0x00,0x36]
|
||||
#CHECK: vlm %v0, %v0, 4095 # encoding: [0xe7,0x00,0x0f,0xff,0x00,0x36]
|
||||
#CHECK: vlm %v0, %v0, 0(%r15) # encoding: [0xe7,0x00,0xf0,0x00,0x00,0x36]
|
||||
#CHECK: vlm %v0, %v0, 0(%r15), 4 # encoding: [0xe7,0x00,0xf0,0x00,0x40,0x36]
|
||||
#CHECK: vlm %v0, %v31, 0 # encoding: [0xe7,0x0f,0x00,0x00,0x04,0x36]
|
||||
#CHECK: vlm %v31, %v0, 0 # encoding: [0xe7,0xf0,0x00,0x00,0x08,0x36]
|
||||
#CHECK: vlm %v14, %v17, 1074(%r5) # encoding: [0xe7,0xe1,0x54,0x32,0x04,0x36]
|
||||
#CHECK: vlm %v14, %v17, 1074(%r5), 3 # encoding: [0xe7,0xe1,0x54,0x32,0x34,0x36]
|
||||
|
||||
vlm %v0, %v0, 0
|
||||
vlm %v0, %v0, 4095
|
||||
vlm %v0, %v0, 0(%r15)
|
||||
vlm %v0, %v0, 0(%r15), 4
|
||||
vlm %v0, %v31, 0
|
||||
vlm %v31, %v0, 0
|
||||
vlm %v14, %v17, 1074(%r5)
|
||||
vlm %v14, %v17, 1074(%r5), 3
|
||||
|
||||
#CHECK: vlp %v0, %v0, 0 # encoding: [0xe7,0x00,0x00,0x00,0x00,0xdf]
|
||||
#CHECK: vlp %v0, %v0, 15 # encoding: [0xe7,0x00,0x00,0x00,0xf0,0xdf]
|
||||
@ -6081,17 +6085,19 @@
|
||||
#CHECK: vst %v0, 4095 # encoding: [0xe7,0x00,0x0f,0xff,0x00,0x0e]
|
||||
#CHECK: vst %v0, 0(%r15) # encoding: [0xe7,0x00,0xf0,0x00,0x00,0x0e]
|
||||
#CHECK: vst %v0, 0(%r15,%r1) # encoding: [0xe7,0x0f,0x10,0x00,0x00,0x0e]
|
||||
#CHECK: vst %v0, 0(%r15,%r1), 4 # encoding: [0xe7,0x0f,0x10,0x00,0x40,0x0e]
|
||||
#CHECK: vst %v15, 0 # encoding: [0xe7,0xf0,0x00,0x00,0x00,0x0e]
|
||||
#CHECK: vst %v31, 0 # encoding: [0xe7,0xf0,0x00,0x00,0x08,0x0e]
|
||||
#CHECK: vst %v18, 1383(%r3,%r4) # encoding: [0xe7,0x23,0x45,0x67,0x08,0x0e]
|
||||
#CHECK: vst %v18, 1383(%r3,%r4), 3 # encoding: [0xe7,0x23,0x45,0x67,0x38,0x0e]
|
||||
|
||||
vst %v0, 0
|
||||
vst %v0, 4095
|
||||
vst %v0, 0(%r15)
|
||||
vst %v0, 0(%r15,%r1)
|
||||
vst %v0, 0(%r15,%r1), 4
|
||||
vst %v15, 0
|
||||
vst %v31, 0
|
||||
vst %v18, 0x567(%r3,%r4)
|
||||
vst %v18, 0x567(%r3,%r4), 3
|
||||
|
||||
#CHECK: vsteb %v0, 0, 0 # encoding: [0xe7,0x00,0x00,0x00,0x00,0x08]
|
||||
#CHECK: vsteb %v0, 0, 15 # encoding: [0xe7,0x00,0x00,0x00,0xf0,0x08]
|
||||
@ -6184,16 +6190,18 @@
|
||||
#CHECK: vstm %v0, %v0, 0 # encoding: [0xe7,0x00,0x00,0x00,0x00,0x3e]
|
||||
#CHECK: vstm %v0, %v0, 4095 # encoding: [0xe7,0x00,0x0f,0xff,0x00,0x3e]
|
||||
#CHECK: vstm %v0, %v0, 0(%r15) # encoding: [0xe7,0x00,0xf0,0x00,0x00,0x3e]
|
||||
#CHECK: vstm %v0, %v0, 0(%r15), 4 # encoding: [0xe7,0x00,0xf0,0x00,0x40,0x3e]
|
||||
#CHECK: vstm %v0, %v31, 0 # encoding: [0xe7,0x0f,0x00,0x00,0x04,0x3e]
|
||||
#CHECK: vstm %v31, %v0, 0 # encoding: [0xe7,0xf0,0x00,0x00,0x08,0x3e]
|
||||
#CHECK: vstm %v14, %v17, 1074(%r5) # encoding: [0xe7,0xe1,0x54,0x32,0x04,0x3e]
|
||||
#CHECK: vstm %v14, %v17, 1074(%r5), 3 # encoding: [0xe7,0xe1,0x54,0x32,0x34,0x3e]
|
||||
|
||||
vstm %v0, %v0, 0
|
||||
vstm %v0, %v0, 4095
|
||||
vstm %v0, %v0, 0(%r15)
|
||||
vstm %v0, %v0, 0(%r15), 4
|
||||
vstm %v0, %v31, 0
|
||||
vstm %v31, %v0, 0
|
||||
vstm %v14, %v17, 1074(%r5)
|
||||
vstm %v14, %v17, 1074(%r5), 3
|
||||
|
||||
#CHECK: vstrc %v0, %v0, %v0, %v0, 0, 0 # encoding: [0xe7,0x00,0x00,0x00,0x00,0x8a]
|
||||
#CHECK: vstrc %v0, %v0, %v0, %v0, 15, 0 # encoding: [0xe7,0x00,0x0f,0x00,0x00,0x8a]
|
||||
|
||||
Loading…
x
Reference in New Issue
Block a user