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[AArch64] - Generate pointer authentication instructions
- Generate pointer authentication instructions - The functions instrumented depend on function attribtues: all (all functions instrumentent) non-leaf (only those that spill LR) none - Function epilogues sign the LR before spilling to the stack and authenticate the LR once restored - If the target is v8.3a or greater than can use the combined authenticate and return instruction Differential revision: https://reviews.llvm.org/D49793 llvm-svn: 340018
This commit is contained in:
Luke Cheeseman
parent
c1e80e5c3f
commit
079a490c8b
@ -98,6 +98,7 @@
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#include "AArch64Subtarget.h"
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#include "AArch64TargetMachine.h"
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#include "MCTargetDesc/AArch64AddressingModes.h"
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#include "llvm/ADT/ScopeExit.h"
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#include "llvm/ADT/SmallVector.h"
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#include "llvm/ADT/Statistic.h"
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#include "llvm/CodeGen/LivePhysRegs.h"
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@ -279,6 +280,31 @@ MachineBasicBlock::iterator AArch64FrameLowering::eliminateCallFramePseudoInstr(
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return MBB.erase(I);
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}
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static bool ShouldSignReturnAddress(MachineFunction &MF) {
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// The function should be signed in the following situations:
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// - sign-return-address=all
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// - sign-return-address=non-leaf and the functions spills the LR
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const Function &F = MF.getFunction();
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if (!F.hasFnAttribute("sign-return-address"))
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return false;
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StringRef Scope = F.getFnAttribute("sign-return-address").getValueAsString();
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if (Scope.equals("none"))
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return false;
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if (Scope.equals("all"))
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return true;
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assert(Scope.equals("non-leaf") && "Expected all, none or non-leaf");
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for (const auto &Info : MF.getFrameInfo().getCalleeSavedInfo())
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if (Info.getReg() == AArch64::LR)
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return true;
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return false;
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}
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void AArch64FrameLowering::emitCalleeSavedFrameMoves(
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MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI) const {
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MachineFunction &MF = *MBB.getParent();
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@ -568,6 +594,11 @@ void AArch64FrameLowering::emitPrologue(MachineFunction &MF,
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// to determine the end of the prologue.
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DebugLoc DL;
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if (ShouldSignReturnAddress(MF)) {
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BuildMI(MBB, MBBI, DL, TII->get(AArch64::PACIASP))
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.setMIFlag(MachineInstr::FrameSetup);
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}
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// All calls are tail calls in GHC calling conv, and functions have no
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// prologue/epilogue.
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if (MF.getFunction().getCallingConv() == CallingConv::GHC)
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@ -832,6 +863,32 @@ void AArch64FrameLowering::emitPrologue(MachineFunction &MF,
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}
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}
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static void InsertReturnAddressAuth(MachineFunction &MF,
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MachineBasicBlock &MBB) {
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if (!ShouldSignReturnAddress(MF))
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return;
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const AArch64Subtarget &Subtarget = MF.getSubtarget<AArch64Subtarget>();
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const TargetInstrInfo *TII = Subtarget.getInstrInfo();
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MachineBasicBlock::iterator MBBI = MBB.getFirstTerminator();
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DebugLoc DL;
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if (MBBI != MBB.end())
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DL = MBBI->getDebugLoc();
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// The AUTIASP instruction assembles to a hint instruction before v8.3a so
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// this instruction can safely used for any v8a architecture.
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// From v8.3a onwards there are optimised authenticate LR and return
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// instructions, namely RETA{A,B}, that can be used instead.
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if (Subtarget.hasV8_3aOps() && MBBI != MBB.end() &&
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MBBI->getOpcode() == AArch64::RET_ReallyLR) {
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BuildMI(MBB, MBBI, DL, TII->get(AArch64::RETAA)).copyImplicitOps(*MBBI);
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MBB.erase(MBBI);
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} else {
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BuildMI(MBB, MBBI, DL, TII->get(AArch64::AUTIASP))
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.setMIFlag(MachineInstr::FrameDestroy);
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}
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}
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void AArch64FrameLowering::emitEpilogue(MachineFunction &MF,
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MachineBasicBlock &MBB) const {
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MachineBasicBlock::iterator MBBI = MBB.getLastNonDebugInstr();
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@ -899,6 +956,8 @@ void AArch64FrameLowering::emitEpilogue(MachineFunction &MF,
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// AArch64TargetLowering::LowerCall figures out ArgumentPopSize and keeps
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// it as the 2nd argument of AArch64ISD::TC_RETURN.
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auto Cleanup = make_scope_exit([&] { InsertReturnAddressAuth(MF, MBB); });
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bool IsWin64 =
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Subtarget.isCallingConvWin64(MF.getFunction().getCallingConv());
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unsigned FixedObject = IsWin64 ? alignTo(AFI->getVarArgsGPRSize(), 16) : 0;
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86
test/CodeGen/AArch64/sign-return-address.ll
Normal file
86
test/CodeGen/AArch64/sign-return-address.ll
Normal file
@ -0,0 +1,86 @@
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; RUN: llc -mtriple=aarch64-none-eabi < %s | FileCheck %s
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; CHECK-LABEL: @leaf
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; CHECK-NOT: paci{{[a,b]}}sp
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; CHECK-NOT: auti{{[a,b]}}sp
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define i32 @leaf(i32 %x) {
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ret i32 %x
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}
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; CHECK-LABEL: @leaf_sign_none
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; CHECK-NOT: paci{{[a,b]}}sp
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; CHECK-NOT: auti{{[a,b]}}sp
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define i32 @leaf_sign_none(i32 %x) "sign-return-address"="none" {
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ret i32 %x
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}
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; CHECK-LABEL: @leaf_sign_non_leaf
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; CHECK-NOT: paci{{[a,b]}}sp
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; CHECK-NOT: auti{{[a,b]}}sp
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define i32 @leaf_sign_non_leaf(i32 %x) "sign-return-address"="non-leaf" {
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ret i32 %x
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}
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; CHECK-LABEL: @leaf_sign_all
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; CHECK: paciasp
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; CHECK: autiasp
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; CHECK-NEXT: ret
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define i32 @leaf_sign_all(i32 %x) "sign-return-address"="all" {
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ret i32 %x
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}
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; CHECK: @leaf_clobbers_lr
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; CHECK: paciasp
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; CHECK-NEXT: str x30, [sp, #-16]!
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; CHECK: ldr x30, [sp], #16
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; CHECK-NEXT: autiasp
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; CHECK-NEXT: ret
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define i64 @leaf_clobbers_lr(i64 %x) "sign-return-address"="non-leaf" {
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call void asm sideeffect "mov x30, $0", "r,~{lr}"(i64 %x) #1
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ret i64 %x
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}
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declare i32 @foo(i32)
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; CHECK: @non_leaf_sign_all
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; CHECK: paciasp
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; CHECK: autiasp
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; CHECK-NEXT: ret
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define i32 @non_leaf_sign_all(i32 %x) "sign-return-address"="all" {
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%call = call i32 @foo(i32 %x)
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ret i32 %call
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}
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; CHECK: @non_leaf_sign_non_leaf
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; CHECK: paciasp
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; CHECK-NEXT: str x30, [sp, #-16]!
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; CHECK: ldr x30, [sp], #16
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; CHECK-NEXT: autiasp
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; CHECK-NEXT: ret
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define i32 @non_leaf_sign_non_leaf(i32 %x) "sign-return-address"="non-leaf" {
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%call = call i32 @foo(i32 %x)
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ret i32 %call
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}
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; CHECK-LABEL: @leaf_sign_all_v83
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; CHECK: paciasp
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; CHECK-NOT: ret
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; CHECK-NEXT: retaa
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; CHECK-NOT: ret
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define i32 @leaf_sign_all_v83(i32 %x) "sign-return-address"="all" "target-features"="+v8.3a" {
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ret i32 %x
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}
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declare fastcc i64 @bar(i64)
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; CHECK-LABEL: @spill_lr_and_tail_call
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; CHECK: paciasp
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; CHECK-NEXT: str x30, [sp, #-16]!
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; CHECK: ldr x30, [sp], #16
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; CHECK-NEXT: autiasp
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; CHECK-NEXT: b bar
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define fastcc void @spill_lr_and_tail_call(i64 %x) "sign-return-address"="all" {
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call void asm sideeffect "mov x30, $0", "r,~{lr}"(i64 %x) #1
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tail call fastcc i64 @bar(i64 %x)
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ret void
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}
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