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[PowerPC] Implementation of 128-bit Binary Vector Mod and Sign Extend builtins

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This patch implements 128-bit Binary Vector Mod and Sign Extend builtins for PowerPC10.

Differential: https://reviews.llvm.org/D87394#inline-815858
This commit is contained in:
Albion Fung 2020-09-23 01:17:59 -05:00
parent 8657118818
commit 07ca45046e
7 changed files with 128 additions and 8 deletions
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14
include/llvm/IR/IntrinsicsPowerPC.td
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@ -801,6 +801,20 @@ let TargetPrefix = "ppc" in { // All PPC intrinsics start with "llvm.ppc.".
Intrinsic<[llvm_v4i32_ty], [llvm_v16i8_ty, llvm_v4i32_ty],
[IntrNoMem]>;
// Vector Sign Extension Instructions
def int_ppc_altivec_vextsb2w : GCCBuiltin<"__builtin_altivec_vextsb2w">,
Intrinsic<[llvm_v4i32_ty], [llvm_v16i8_ty], [IntrNoMem]>;
def int_ppc_altivec_vextsb2d : GCCBuiltin<"__builtin_altivec_vextsb2d">,
Intrinsic<[llvm_v2i64_ty], [llvm_v16i8_ty], [IntrNoMem]>;
def int_ppc_altivec_vextsh2w : GCCBuiltin<"__builtin_altivec_vextsh2w">,
Intrinsic<[llvm_v4i32_ty], [llvm_v8i16_ty], [IntrNoMem]>;
def int_ppc_altivec_vextsh2d : GCCBuiltin<"__builtin_altivec_vextsh2d">,
Intrinsic<[llvm_v2i64_ty], [llvm_v8i16_ty], [IntrNoMem]>;
def int_ppc_altivec_vextsw2d : GCCBuiltin<"__builtin_altivec_vextsw2d">,
Intrinsic<[llvm_v2i64_ty], [llvm_v4i32_ty], [IntrNoMem]>;
def int_ppc_altivec_vextsd2q : GCCBuiltin<"__builtin_altivec_vextsd2q">,
Intrinsic<[llvm_v1i128_ty], [llvm_v2i64_ty], [IntrNoMem]>;
// Other multiplies.
def int_ppc_altivec_vmladduhm : GCCBuiltin<"__builtin_altivec_vmladduhm">,
Intrinsic<[llvm_v8i16_ty], [llvm_v8i16_ty, llvm_v8i16_ty,

2
lib/Target/PowerPC/PPCISelLowering.cpp
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@ -888,6 +888,8 @@ PPCTargetLowering::PPCTargetLowering(const PPCTargetMachine &TM,
setOperationAction(ISD::SREM, MVT::v2i64, Legal);
setOperationAction(ISD::UREM, MVT::v4i32, Legal);
setOperationAction(ISD::SREM, MVT::v4i32, Legal);
setOperationAction(ISD::UREM, MVT::v1i128, Legal);
setOperationAction(ISD::SREM, MVT::v1i128, Legal);
setOperationAction(ISD::UDIV, MVT::v1i128, Legal);
setOperationAction(ISD::SDIV, MVT::v1i128, Legal);
}

15
lib/Target/PowerPC/PPCInstrAltivec.td
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@ -1449,11 +1449,16 @@ def VCTZD : VX_VT5_EO5_VB5<1538, 31, "vctzd",
[(set v2i64:$vD, (cttz v2i64:$vB))]>;
// Vector Extend Sign
def VEXTSB2W : VX_VT5_EO5_VB5<1538, 16, "vextsb2w", []>;
def VEXTSH2W : VX_VT5_EO5_VB5<1538, 17, "vextsh2w", []>;
def VEXTSB2D : VX_VT5_EO5_VB5<1538, 24, "vextsb2d", []>;
def VEXTSH2D : VX_VT5_EO5_VB5<1538, 25, "vextsh2d", []>;
def VEXTSW2D : VX_VT5_EO5_VB5<1538, 26, "vextsw2d", []>;
def VEXTSB2W : VX_VT5_EO5_VB5<1538, 16, "vextsb2w",
[(set v4i32:$vD, (int_ppc_altivec_vextsb2w v16i8:$vB))]>;
def VEXTSH2W : VX_VT5_EO5_VB5<1538, 17, "vextsh2w",
[(set v4i32:$vD, (int_ppc_altivec_vextsh2w v8i16:$vB))]>;
def VEXTSB2D : VX_VT5_EO5_VB5<1538, 24, "vextsb2d",
[(set v2i64:$vD, (int_ppc_altivec_vextsb2d v16i8:$vB))]>;
def VEXTSH2D : VX_VT5_EO5_VB5<1538, 25, "vextsh2d",
[(set v2i64:$vD, (int_ppc_altivec_vextsh2d v8i16:$vB))]>;
def VEXTSW2D : VX_VT5_EO5_VB5<1538, 26, "vextsw2d",
[(set v2i64:$vD, (int_ppc_altivec_vextsw2d v4i32:$vB))]>;
let isCodeGenOnly = 1 in {
def VEXTSB2Ws : VX_VT5_EO5_VB5s<1538, 16, "vextsb2w", []>;
def VEXTSH2Ws : VX_VT5_EO5_VB5s<1538, 17, "vextsh2w", []>;

9
lib/Target/PowerPC/PPCInstrPrefix.td
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@ -1449,11 +1449,14 @@ let Predicates = [IsISA3_1] in {
def VCMPGTSQ_rec : VCMPo <903, "vcmpgtsq. $vD, $vA, $vB" , v1i128>;
def VCMPGTUQ_rec : VCMPo <647, "vcmpgtuq. $vD, $vA, $vB" , v1i128>;
def VMODSQ : VXForm_1<1803, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB),
"vmodsq $vD, $vA, $vB", IIC_VecGeneral, []>;
"vmodsq $vD, $vA, $vB", IIC_VecGeneral,
[(set v1i128:$vD, (srem v1i128:$vA, v1i128:$vB))]>;
def VMODUQ : VXForm_1<1547, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB),
"vmoduq $vD, $vA, $vB", IIC_VecGeneral, []>;
"vmoduq $vD, $vA, $vB", IIC_VecGeneral,
[(set v1i128:$vD, (urem v1i128:$vA, v1i128:$vB))]>;
def VEXTSD2Q : VXForm_RD5_XO5_RS5<1538, 27, (outs vrrc:$vD), (ins vrrc:$vB),
"vextsd2q $vD, $vB", IIC_VecGeneral, []>;
"vextsd2q $vD, $vB", IIC_VecGeneral,
[(set v1i128:$vD, (int_ppc_altivec_vextsd2q v2i64:$vB))]>;
def VCMPUQ : VXForm_BF3_VAB5<257, (outs crrc:$BF), (ins vrrc:$vA, vrrc:$vB),
"vcmpuq $BF, $vA, $vB", IIC_VecGeneral, []>;
def VCMPSQ : VXForm_BF3_VAB5<321, (outs crrc:$BF), (ins vrrc:$vA, vrrc:$vB),

22
test/CodeGen/PowerPC/p10-vector-modulo.ll
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@ -10,6 +10,28 @@
; The vector modulo instructions operate on signed and unsigned words
; and doublewords.
; The vector modulo instructions operate on signed and unsigned words,
; doublewords and 128-bit values.
define <1 x i128> @test_vmodsq(<1 x i128> %x, <1 x i128> %y) nounwind readnone {
; CHECK-LABEL: test_vmodsq:
; CHECK: # %bb.0:
; CHECK-NEXT: vmodsq v2, v2, v3
; CHECK-NEXT: blr
%tmp = srem <1 x i128> %x, %y
ret <1 x i128> %tmp
}
define <1 x i128> @test_vmoduq(<1 x i128> %x, <1 x i128> %y) nounwind readnone {
; CHECK-LABEL: test_vmoduq:
; CHECK: # %bb.0:
; CHECK-NEXT: vmoduq v2, v2, v3
; CHECK-NEXT: blr
%tmp = urem <1 x i128> %x, %y
ret <1 x i128> %tmp
}
define <2 x i64> @test_vmodud(<2 x i64> %a, <2 x i64> %b) {
; CHECK-LABEL: test_vmodud:
; CHECK: # %bb.0: # %entry

17
test/CodeGen/PowerPC/p10-vector-sign-extend.ll Normal file
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@ -0,0 +1,17 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \
; RUN: -mcpu=pwr10 -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr < %s | \
; RUN: FileCheck %s
; This test case aims to test vector sign extend builtins.
declare <1 x i128> @llvm.ppc.altivec.vextsd2q(<2 x i64>) nounwind readnone
define <1 x i128> @test_vextsd2q(<2 x i64> %x) nounwind readnone {
; CHECK-LABEL: test_vextsd2q:
; CHECK: # %bb.0:
; CHECK-NEXT: vextsd2q v2, v2
; CHECK-NEXT: blr
%tmp = tail call <1 x i128> @llvm.ppc.altivec.vextsd2q(<2 x i64> %x)
ret <1 x i128> %tmp
}

57
test/CodeGen/PowerPC/p9-vector-sign-extend.ll Normal file
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@ -0,0 +1,57 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \
; RUN: -mcpu=pwr10 -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr < %s | \
; RUN: FileCheck %s
; This test case aims to test vector sign extend builtins.
declare <4 x i32> @llvm.ppc.altivec.vextsb2w(<16 x i8>) nounwind readnone
declare <2 x i64> @llvm.ppc.altivec.vextsb2d(<16 x i8>) nounwind readnone
declare <4 x i32> @llvm.ppc.altivec.vextsh2w(<8 x i16>) nounwind readnone
declare <2 x i64> @llvm.ppc.altivec.vextsh2d(<8 x i16>) nounwind readnone
declare <2 x i64> @llvm.ppc.altivec.vextsw2d(<4 x i32>) nounwind readnone
define <4 x i32> @test_vextsb2w(<16 x i8> %x) nounwind readnone {
; CHECK-LABEL: test_vextsb2w:
; CHECK: # %bb.0:
; CHECK-NEXT: vextsb2w v2, v2
; CHECK-NEXT: blr
%tmp = tail call <4 x i32> @llvm.ppc.altivec.vextsb2w(<16 x i8> %x)
ret <4 x i32> %tmp
}
define <2 x i64> @test_vextsb2d(<16 x i8> %x) nounwind readnone {
; CHECK-LABEL: test_vextsb2d:
; CHECK: # %bb.0:
; CHECK-NEXT: vextsb2d v2, v2
; CHECK-NEXT: blr
%tmp = tail call <2 x i64> @llvm.ppc.altivec.vextsb2d(<16 x i8> %x)
ret <2 x i64> %tmp
}
define <4 x i32> @test_vextsh2w(<8 x i16> %x) nounwind readnone {
; CHECK-LABEL: test_vextsh2w:
; CHECK: # %bb.0:
; CHECK-NEXT: vextsh2w v2, v2
; CHECK-NEXT: blr
%tmp = tail call <4 x i32> @llvm.ppc.altivec.vextsh2w(<8 x i16> %x)
ret <4 x i32> %tmp
}
define <2 x i64> @test_vextsh2d(<8 x i16> %x) nounwind readnone {
; CHECK-LABEL: test_vextsh2d:
; CHECK: # %bb.0:
; CHECK-NEXT: vextsh2d v2, v2
; CHECK-NEXT: blr
%tmp = tail call <2 x i64> @llvm.ppc.altivec.vextsh2d(<8 x i16> %x)
ret <2 x i64> %tmp
}
define <2 x i64> @test_vextsw2d(<4 x i32> %x) nounwind readnone {
; CHECK-LABEL: test_vextsw2d:
; CHECK: # %bb.0:
; CHECK-NEXT: vextsw2d v2, v2
; CHECK-NEXT: blr
%tmp = tail call <2 x i64> @llvm.ppc.altivec.vextsw2d(<4 x i32> %x)
ret <2 x i64> %tmp
}