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[RISCV] Add intrinsics for vfwmacc, vfwnmacc, vfwmsac, vfwnmsac instructions
This patch defines vfwmacc, vfwnmacc, vfwmsc, vfwnmsac intrinsics and lower to V instructions. We work with @rogfer01 from BSC to come out this patch. Authored-by: Roger Ferrer Ibanez <rofirrim@gmail.com> Co-Authored-by: ShihPo Hung <shihpo.hung@sifive.com> Differential Revision: https://reviews.llvm.org/D93693
This commit is contained in:
ShihPo Hung
parent
baa62a1798
commit
07cf8b0588
@ -561,6 +561,11 @@ let TargetPrefix = "riscv" in {
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defm vfmsub : RISCVTernaryAAXA;
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defm vfnmsub : RISCVTernaryAAXA;
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defm vfwmacc : RISCVTernaryWide;
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defm vfwnmacc : RISCVTernaryWide;
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defm vfwmsac : RISCVTernaryWide;
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defm vfwnmsac : RISCVTernaryWide;
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defm vfmin : RISCVBinaryAAX;
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defm vfmax : RISCVBinaryAAX;
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@ -898,10 +898,11 @@ multiclass VPseudoTernaryW_VV {
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defm _VV : VPseudoTernary<m.wvrclass, m.vrclass, m.vrclass, m, constraint>;
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}
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multiclass VPseudoTernaryW_VX {
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multiclass VPseudoTernaryW_VX<bit IsFloat> {
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defvar constraint = "@earlyclobber $rd";
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foreach m = MxList.m in
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defm _VX : VPseudoTernary<m.wvrclass, GPR, m.vrclass, m, constraint>;
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defm !if(IsFloat, "_VF", "_VX") : VPseudoTernary<m.wvrclass,
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!if(IsFloat, FPR32, GPR), m.vrclass, m, constraint>;
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}
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multiclass VPseudoTernaryV_VI<Operand ImmType = simm5, string Constraint = ""> {
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@ -919,9 +920,9 @@ multiclass VPseudoTernaryV_VX_VI<Operand ImmType = simm5, string Constraint = ""
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defm "" : VPseudoTernaryV_VI<ImmType, Constraint>;
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}
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multiclass VPseudoTernaryW_VV_VX {
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multiclass VPseudoTernaryW_VV_VX<bit IsFloat = false> {
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defm "" : VPseudoTernaryW_VV;
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defm "" : VPseudoTernaryW_VX;
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defm "" : VPseudoTernaryW_VX<IsFloat>;
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}
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multiclass VPseudoBinaryM_VV_VX_VI {
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@ -1631,10 +1632,11 @@ multiclass VPatTernaryW_VX<string intrinsic, string instruction,
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foreach vtiToWti = vtilist in {
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defvar vti = vtiToWti.Vti;
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defvar wti = vtiToWti.Wti;
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defm : VPatTernary<intrinsic, instruction, "VX",
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wti.Vector, XLenVT, vti.Vector,
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vti.Mask, vti.SEW, vti.LMul,
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wti.RegClass, vti.ScalarRegClass, vti.RegClass>;
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defm : VPatTernary<intrinsic, instruction,
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!if(!eq(vti.Scalar, XLenVT), "VX", "VF"),
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wti.Vector, vti.Scalar, vti.Vector,
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vti.Mask, vti.SEW, vti.LMul,
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wti.RegClass, vti.ScalarRegClass, vti.RegClass>;
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}
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}
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@ -1864,7 +1866,7 @@ defm PseudoVNMSUB : VPseudoTernaryV_VV_VX_AAXA;
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defm PseudoVWMACCU : VPseudoTernaryW_VV_VX;
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defm PseudoVWMACC : VPseudoTernaryW_VV_VX;
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defm PseudoVWMACCSU : VPseudoTernaryW_VV_VX;
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defm PseudoVWMACCUS : VPseudoTernaryW_VX;
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defm PseudoVWMACCUS : VPseudoTernaryW_VX</*IsFloat*/false>;
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//===----------------------------------------------------------------------===//
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// 12.15. Vector Integer Merge Instructions
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@ -1962,6 +1964,14 @@ defm PseudoVFNMADD : VPseudoTernaryV_VV_VX_AAXA</*IsFloat*/true>;
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defm PseudoVFMSUB : VPseudoTernaryV_VV_VX_AAXA</*IsFloat*/true>;
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defm PseudoVFNMSUB : VPseudoTernaryV_VV_VX_AAXA</*IsFloat*/true>;
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//===----------------------------------------------------------------------===//
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// 14.7. Vector Widening Floating-Point Fused Multiply-Add Instructions
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//===----------------------------------------------------------------------===//
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defm PseudoVFWMACC : VPseudoTernaryW_VV_VX</*IsFloat*/true>;
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defm PseudoVFWNMACC : VPseudoTernaryW_VV_VX</*IsFloat*/true>;
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defm PseudoVFWMSAC : VPseudoTernaryW_VV_VX</*IsFloat*/true>;
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defm PseudoVFWNMSAC : VPseudoTernaryW_VV_VX</*IsFloat*/true>;
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//===----------------------------------------------------------------------===//
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// 14.9. Vector Floating-Point Min/Max Instructions
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//===----------------------------------------------------------------------===//
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@ -2373,6 +2383,14 @@ defm "" : VPatTernaryV_VV_VX_AAXA<"int_riscv_vfnmadd", "PseudoVFNMADD", AllFloat
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defm "" : VPatTernaryV_VV_VX_AAXA<"int_riscv_vfmsub", "PseudoVFMSUB", AllFloatVectors>;
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defm "" : VPatTernaryV_VV_VX_AAXA<"int_riscv_vfnmsub", "PseudoVFNMSUB", AllFloatVectors>;
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//===----------------------------------------------------------------------===//
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// 14.7. Vector Widening Floating-Point Fused Multiply-Add Instructions
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//===----------------------------------------------------------------------===//
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defm "" : VPatTernaryW_VV_VX<"int_riscv_vfwmacc", "PseudoVFWMACC", AllWidenableFloatVectors>;
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defm "" : VPatTernaryW_VV_VX<"int_riscv_vfwnmacc", "PseudoVFWNMACC", AllWidenableFloatVectors>;
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defm "" : VPatTernaryW_VV_VX<"int_riscv_vfwmsac", "PseudoVFWMSAC", AllWidenableFloatVectors>;
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defm "" : VPatTernaryW_VV_VX<"int_riscv_vfwnmsac", "PseudoVFWNMSAC", AllWidenableFloatVectors>;
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//===----------------------------------------------------------------------===//
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// 14.9. Vector Floating-Point Min/Max Instructions
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//===----------------------------------------------------------------------===//
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482
test/CodeGen/RISCV/rvv/vfwmacc-rv32.ll
Normal file
482
test/CodeGen/RISCV/rvv/vfwmacc-rv32.ll
Normal file
@ -0,0 +1,482 @@
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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -mtriple=riscv32 -mattr=+experimental-v,+f,+experimental-zfh -verify-machineinstrs \
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; RUN: --riscv-no-aliases < %s | FileCheck %s
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declare <vscale x 1 x float> @llvm.riscv.vfwmacc.nxv1f32.nxv1f16(
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<vscale x 1 x float>,
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<vscale x 1 x half>,
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<vscale x 1 x half>,
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i32);
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define <vscale x 1 x float> @intrinsic_vfwmacc_vv_nxv1f32_nxv1f16_nxv1f16(<vscale x 1 x float> %0, <vscale x 1 x half> %1, <vscale x 1 x half> %2, i32 %3) nounwind {
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; CHECK-LABEL: intrinsic_vfwmacc_vv_nxv1f32_nxv1f16_nxv1f16:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: vsetvli a0, a0, e16,mf4,ta,mu
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; CHECK-NEXT: vfwmacc.vv v16, v17, v18
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; CHECK-NEXT: jalr zero, 0(ra)
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entry:
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%a = call <vscale x 1 x float> @llvm.riscv.vfwmacc.nxv1f32.nxv1f16(
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<vscale x 1 x float> %0,
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<vscale x 1 x half> %1,
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<vscale x 1 x half> %2,
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i32 %3)
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ret <vscale x 1 x float> %a
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}
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declare <vscale x 1 x float> @llvm.riscv.vfwmacc.mask.nxv1f32.nxv1f16(
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<vscale x 1 x float>,
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<vscale x 1 x half>,
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<vscale x 1 x half>,
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<vscale x 1 x i1>,
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i32);
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define <vscale x 1 x float> @intrinsic_vfwmacc_mask_vv_nxv1f32_nxv1f16_nxv1f16(<vscale x 1 x float> %0, <vscale x 1 x half> %1, <vscale x 1 x half> %2, <vscale x 1 x i1> %3, i32 %4) nounwind {
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; CHECK-LABEL: intrinsic_vfwmacc_mask_vv_nxv1f32_nxv1f16_nxv1f16:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: vsetvli a0, a0, e16,mf4,ta,mu
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; CHECK-NEXT: vfwmacc.vv v16, v17, v18, v0.t
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; CHECK-NEXT: jalr zero, 0(ra)
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entry:
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%a = call <vscale x 1 x float> @llvm.riscv.vfwmacc.mask.nxv1f32.nxv1f16(
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<vscale x 1 x float> %0,
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<vscale x 1 x half> %1,
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<vscale x 1 x half> %2,
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<vscale x 1 x i1> %3,
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i32 %4)
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ret <vscale x 1 x float> %a
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}
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declare <vscale x 2 x float> @llvm.riscv.vfwmacc.nxv2f32.nxv2f16(
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<vscale x 2 x float>,
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<vscale x 2 x half>,
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<vscale x 2 x half>,
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i32);
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define <vscale x 2 x float> @intrinsic_vfwmacc_vv_nxv2f32_nxv2f16_nxv2f16(<vscale x 2 x float> %0, <vscale x 2 x half> %1, <vscale x 2 x half> %2, i32 %3) nounwind {
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; CHECK-LABEL: intrinsic_vfwmacc_vv_nxv2f32_nxv2f16_nxv2f16:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: vsetvli a0, a0, e16,mf2,ta,mu
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; CHECK-NEXT: vfwmacc.vv v16, v17, v18
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; CHECK-NEXT: jalr zero, 0(ra)
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entry:
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%a = call <vscale x 2 x float> @llvm.riscv.vfwmacc.nxv2f32.nxv2f16(
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<vscale x 2 x float> %0,
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<vscale x 2 x half> %1,
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<vscale x 2 x half> %2,
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i32 %3)
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ret <vscale x 2 x float> %a
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}
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declare <vscale x 2 x float> @llvm.riscv.vfwmacc.mask.nxv2f32.nxv2f16(
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<vscale x 2 x float>,
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<vscale x 2 x half>,
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<vscale x 2 x half>,
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<vscale x 2 x i1>,
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i32);
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define <vscale x 2 x float> @intrinsic_vfwmacc_mask_vv_nxv2f32_nxv2f16_nxv2f16(<vscale x 2 x float> %0, <vscale x 2 x half> %1, <vscale x 2 x half> %2, <vscale x 2 x i1> %3, i32 %4) nounwind {
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; CHECK-LABEL: intrinsic_vfwmacc_mask_vv_nxv2f32_nxv2f16_nxv2f16:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: vsetvli a0, a0, e16,mf2,ta,mu
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; CHECK-NEXT: vfwmacc.vv v16, v17, v18, v0.t
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; CHECK-NEXT: jalr zero, 0(ra)
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entry:
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%a = call <vscale x 2 x float> @llvm.riscv.vfwmacc.mask.nxv2f32.nxv2f16(
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<vscale x 2 x float> %0,
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<vscale x 2 x half> %1,
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<vscale x 2 x half> %2,
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<vscale x 2 x i1> %3,
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i32 %4)
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ret <vscale x 2 x float> %a
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}
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declare <vscale x 4 x float> @llvm.riscv.vfwmacc.nxv4f32.nxv4f16(
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<vscale x 4 x float>,
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<vscale x 4 x half>,
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<vscale x 4 x half>,
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i32);
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define <vscale x 4 x float> @intrinsic_vfwmacc_vv_nxv4f32_nxv4f16_nxv4f16(<vscale x 4 x float> %0, <vscale x 4 x half> %1, <vscale x 4 x half> %2, i32 %3) nounwind {
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; CHECK-LABEL: intrinsic_vfwmacc_vv_nxv4f32_nxv4f16_nxv4f16:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: vsetvli a0, a0, e16,m1,ta,mu
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; CHECK-NEXT: vfwmacc.vv v16, v18, v19
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; CHECK-NEXT: jalr zero, 0(ra)
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entry:
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%a = call <vscale x 4 x float> @llvm.riscv.vfwmacc.nxv4f32.nxv4f16(
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<vscale x 4 x float> %0,
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<vscale x 4 x half> %1,
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<vscale x 4 x half> %2,
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i32 %3)
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ret <vscale x 4 x float> %a
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}
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declare <vscale x 4 x float> @llvm.riscv.vfwmacc.mask.nxv4f32.nxv4f16(
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<vscale x 4 x float>,
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<vscale x 4 x half>,
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<vscale x 4 x half>,
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<vscale x 4 x i1>,
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i32);
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define <vscale x 4 x float> @intrinsic_vfwmacc_mask_vv_nxv4f32_nxv4f16_nxv4f16(<vscale x 4 x float> %0, <vscale x 4 x half> %1, <vscale x 4 x half> %2, <vscale x 4 x i1> %3, i32 %4) nounwind {
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; CHECK-LABEL: intrinsic_vfwmacc_mask_vv_nxv4f32_nxv4f16_nxv4f16:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: vsetvli a0, a0, e16,m1,ta,mu
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; CHECK-NEXT: vfwmacc.vv v16, v18, v19, v0.t
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; CHECK-NEXT: jalr zero, 0(ra)
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entry:
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%a = call <vscale x 4 x float> @llvm.riscv.vfwmacc.mask.nxv4f32.nxv4f16(
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<vscale x 4 x float> %0,
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<vscale x 4 x half> %1,
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<vscale x 4 x half> %2,
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<vscale x 4 x i1> %3,
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i32 %4)
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ret <vscale x 4 x float> %a
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}
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declare <vscale x 8 x float> @llvm.riscv.vfwmacc.nxv8f32.nxv8f16(
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<vscale x 8 x float>,
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<vscale x 8 x half>,
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<vscale x 8 x half>,
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i32);
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define <vscale x 8 x float> @intrinsic_vfwmacc_vv_nxv8f32_nxv8f16_nxv8f16(<vscale x 8 x float> %0, <vscale x 8 x half> %1, <vscale x 8 x half> %2, i32 %3) nounwind {
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; CHECK-LABEL: intrinsic_vfwmacc_vv_nxv8f32_nxv8f16_nxv8f16:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: vsetvli a0, a0, e16,m2,ta,mu
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; CHECK-NEXT: vfwmacc.vv v16, v20, v22
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; CHECK-NEXT: jalr zero, 0(ra)
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entry:
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%a = call <vscale x 8 x float> @llvm.riscv.vfwmacc.nxv8f32.nxv8f16(
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<vscale x 8 x float> %0,
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<vscale x 8 x half> %1,
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<vscale x 8 x half> %2,
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i32 %3)
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ret <vscale x 8 x float> %a
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}
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declare <vscale x 8 x float> @llvm.riscv.vfwmacc.mask.nxv8f32.nxv8f16(
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<vscale x 8 x float>,
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<vscale x 8 x half>,
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<vscale x 8 x half>,
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<vscale x 8 x i1>,
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i32);
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define <vscale x 8 x float> @intrinsic_vfwmacc_mask_vv_nxv8f32_nxv8f16_nxv8f16(<vscale x 8 x float> %0, <vscale x 8 x half> %1, <vscale x 8 x half> %2, <vscale x 8 x i1> %3, i32 %4) nounwind {
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; CHECK-LABEL: intrinsic_vfwmacc_mask_vv_nxv8f32_nxv8f16_nxv8f16:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: vsetvli a0, a0, e16,m2,ta,mu
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; CHECK-NEXT: vfwmacc.vv v16, v20, v22, v0.t
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; CHECK-NEXT: jalr zero, 0(ra)
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entry:
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%a = call <vscale x 8 x float> @llvm.riscv.vfwmacc.mask.nxv8f32.nxv8f16(
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<vscale x 8 x float> %0,
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<vscale x 8 x half> %1,
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<vscale x 8 x half> %2,
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<vscale x 8 x i1> %3,
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i32 %4)
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ret <vscale x 8 x float> %a
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}
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declare <vscale x 16 x float> @llvm.riscv.vfwmacc.nxv16f32.nxv16f16(
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<vscale x 16 x float>,
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<vscale x 16 x half>,
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<vscale x 16 x half>,
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i32);
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define <vscale x 16 x float> @intrinsic_vfwmacc_vv_nxv16f32_nxv16f16_nxv16f16(<vscale x 16 x float> %0, <vscale x 16 x half> %1, <vscale x 16 x half> %2, i32 %3) nounwind {
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; CHECK-LABEL: intrinsic_vfwmacc_vv_nxv16f32_nxv16f16_nxv16f16:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: vsetvli a3, zero, e16,m4,ta,mu
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; CHECK-NEXT: vle16.v v28, (a1)
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; CHECK-NEXT: vle16.v v8, (a0)
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; CHECK-NEXT: vsetvli a0, a2, e16,m4,ta,mu
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; CHECK-NEXT: vfwmacc.vv v16, v8, v28
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; CHECK-NEXT: jalr zero, 0(ra)
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entry:
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%a = call <vscale x 16 x float> @llvm.riscv.vfwmacc.nxv16f32.nxv16f16(
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<vscale x 16 x float> %0,
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<vscale x 16 x half> %1,
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<vscale x 16 x half> %2,
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i32 %3)
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ret <vscale x 16 x float> %a
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}
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declare <vscale x 16 x float> @llvm.riscv.vfwmacc.mask.nxv16f32.nxv16f16(
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<vscale x 16 x float>,
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<vscale x 16 x half>,
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<vscale x 16 x half>,
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<vscale x 16 x i1>,
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i32);
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define <vscale x 16 x float> @intrinsic_vfwmacc_mask_vv_nxv16f32_nxv16f16_nxv16f16(<vscale x 16 x float> %0, <vscale x 16 x half> %1, <vscale x 16 x half> %2, <vscale x 16 x i1> %3, i32 %4) nounwind {
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; CHECK-LABEL: intrinsic_vfwmacc_mask_vv_nxv16f32_nxv16f16_nxv16f16:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: vsetvli a3, zero, e16,m4,ta,mu
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; CHECK-NEXT: vle16.v v28, (a1)
|
||||
; CHECK-NEXT: vle16.v v8, (a0)
|
||||
; CHECK-NEXT: vsetvli a0, a2, e16,m4,ta,mu
|
||||
; CHECK-NEXT: vfwmacc.vv v16, v8, v28, v0.t
|
||||
; CHECK-NEXT: jalr zero, 0(ra)
|
||||
entry:
|
||||
%a = call <vscale x 16 x float> @llvm.riscv.vfwmacc.mask.nxv16f32.nxv16f16(
|
||||
<vscale x 16 x float> %0,
|
||||
<vscale x 16 x half> %1,
|
||||
<vscale x 16 x half> %2,
|
||||
<vscale x 16 x i1> %3,
|
||||
i32 %4)
|
||||
|
||||
ret <vscale x 16 x float> %a
|
||||
}
|
||||
|
||||
declare <vscale x 1 x float> @llvm.riscv.vfwmacc.nxv1f32.f16(
|
||||
<vscale x 1 x float>,
|
||||
half,
|
||||
<vscale x 1 x half>,
|
||||
i32);
|
||||
|
||||
define <vscale x 1 x float> @intrinsic_vfwmacc_vf_nxv1f32_f16_nxv1f16(<vscale x 1 x float> %0, half %1, <vscale x 1 x half> %2, i32 %3) nounwind {
|
||||
; CHECK-LABEL: intrinsic_vfwmacc_vf_nxv1f32_f16_nxv1f16:
|
||||
; CHECK: # %bb.0: # %entry
|
||||
; CHECK-NEXT: fmv.h.x ft0, a0
|
||||
; CHECK-NEXT: vsetvli a0, a1, e16,mf4,ta,mu
|
||||
; CHECK-NEXT: vfwmacc.vf v16, ft0, v17
|
||||
; CHECK-NEXT: jalr zero, 0(ra)
|
||||
entry:
|
||||
%a = call <vscale x 1 x float> @llvm.riscv.vfwmacc.nxv1f32.f16(
|
||||
<vscale x 1 x float> %0,
|
||||
half %1,
|
||||
<vscale x 1 x half> %2,
|
||||
i32 %3)
|
||||
|
||||
ret <vscale x 1 x float> %a
|
||||
}
|
||||
|
||||
declare <vscale x 1 x float> @llvm.riscv.vfwmacc.mask.nxv1f32.f16(
|
||||
<vscale x 1 x float>,
|
||||
half,
|
||||
<vscale x 1 x half>,
|
||||
<vscale x 1 x i1>,
|
||||
i32);
|
||||
|
||||
define <vscale x 1 x float> @intrinsic_vfwmacc_mask_vf_nxv1f32_f16_nxv1f16(<vscale x 1 x float> %0, half %1, <vscale x 1 x half> %2, <vscale x 1 x i1> %3, i32 %4) nounwind {
|
||||
; CHECK-LABEL: intrinsic_vfwmacc_mask_vf_nxv1f32_f16_nxv1f16:
|
||||
; CHECK: # %bb.0: # %entry
|
||||
; CHECK-NEXT: fmv.h.x ft0, a0
|
||||
; CHECK-NEXT: vsetvli a0, a1, e16,mf4,ta,mu
|
||||
; CHECK-NEXT: vfwmacc.vf v16, ft0, v17, v0.t
|
||||
; CHECK-NEXT: jalr zero, 0(ra)
|
||||
entry:
|
||||
%a = call <vscale x 1 x float> @llvm.riscv.vfwmacc.mask.nxv1f32.f16(
|
||||
<vscale x 1 x float> %0,
|
||||
half %1,
|
||||
<vscale x 1 x half> %2,
|
||||
<vscale x 1 x i1> %3,
|
||||
i32 %4)
|
||||
|
||||
ret <vscale x 1 x float> %a
|
||||
}
|
||||
|
||||
declare <vscale x 2 x float> @llvm.riscv.vfwmacc.nxv2f32.f16(
|
||||
<vscale x 2 x float>,
|
||||
half,
|
||||
<vscale x 2 x half>,
|
||||
i32);
|
||||
|
||||
define <vscale x 2 x float> @intrinsic_vfwmacc_vf_nxv2f32_f16_nxv2f16(<vscale x 2 x float> %0, half %1, <vscale x 2 x half> %2, i32 %3) nounwind {
|
||||
; CHECK-LABEL: intrinsic_vfwmacc_vf_nxv2f32_f16_nxv2f16:
|
||||
; CHECK: # %bb.0: # %entry
|
||||
; CHECK-NEXT: fmv.h.x ft0, a0
|
||||
; CHECK-NEXT: vsetvli a0, a1, e16,mf2,ta,mu
|
||||
; CHECK-NEXT: vfwmacc.vf v16, ft0, v17
|
||||
; CHECK-NEXT: jalr zero, 0(ra)
|
||||
entry:
|
||||
%a = call <vscale x 2 x float> @llvm.riscv.vfwmacc.nxv2f32.f16(
|
||||
<vscale x 2 x float> %0,
|
||||
half %1,
|
||||
<vscale x 2 x half> %2,
|
||||
i32 %3)
|
||||
|
||||
ret <vscale x 2 x float> %a
|
||||
}
|
||||
|
||||
declare <vscale x 2 x float> @llvm.riscv.vfwmacc.mask.nxv2f32.f16(
|
||||
<vscale x 2 x float>,
|
||||
half,
|
||||
<vscale x 2 x half>,
|
||||
<vscale x 2 x i1>,
|
||||
i32);
|
||||
|
||||
define <vscale x 2 x float> @intrinsic_vfwmacc_mask_vf_nxv2f32_f16_nxv2f16(<vscale x 2 x float> %0, half %1, <vscale x 2 x half> %2, <vscale x 2 x i1> %3, i32 %4) nounwind {
|
||||
; CHECK-LABEL: intrinsic_vfwmacc_mask_vf_nxv2f32_f16_nxv2f16:
|
||||
; CHECK: # %bb.0: # %entry
|
||||
; CHECK-NEXT: fmv.h.x ft0, a0
|
||||
; CHECK-NEXT: vsetvli a0, a1, e16,mf2,ta,mu
|
||||
; CHECK-NEXT: vfwmacc.vf v16, ft0, v17, v0.t
|
||||
; CHECK-NEXT: jalr zero, 0(ra)
|
||||
entry:
|
||||
%a = call <vscale x 2 x float> @llvm.riscv.vfwmacc.mask.nxv2f32.f16(
|
||||
<vscale x 2 x float> %0,
|
||||
half %1,
|
||||
<vscale x 2 x half> %2,
|
||||
<vscale x 2 x i1> %3,
|
||||
i32 %4)
|
||||
|
||||
ret <vscale x 2 x float> %a
|
||||
}
|
||||
|
||||
declare <vscale x 4 x float> @llvm.riscv.vfwmacc.nxv4f32.f16(
|
||||
<vscale x 4 x float>,
|
||||
half,
|
||||
<vscale x 4 x half>,
|
||||
i32);
|
||||
|
||||
define <vscale x 4 x float> @intrinsic_vfwmacc_vf_nxv4f32_f16_nxv4f16(<vscale x 4 x float> %0, half %1, <vscale x 4 x half> %2, i32 %3) nounwind {
|
||||
; CHECK-LABEL: intrinsic_vfwmacc_vf_nxv4f32_f16_nxv4f16:
|
||||
; CHECK: # %bb.0: # %entry
|
||||
; CHECK-NEXT: fmv.h.x ft0, a0
|
||||
; CHECK-NEXT: vsetvli a0, a1, e16,m1,ta,mu
|
||||
; CHECK-NEXT: vfwmacc.vf v16, ft0, v18
|
||||
; CHECK-NEXT: jalr zero, 0(ra)
|
||||
entry:
|
||||
%a = call <vscale x 4 x float> @llvm.riscv.vfwmacc.nxv4f32.f16(
|
||||
<vscale x 4 x float> %0,
|
||||
half %1,
|
||||
<vscale x 4 x half> %2,
|
||||
i32 %3)
|
||||
|
||||
ret <vscale x 4 x float> %a
|
||||
}
|
||||
|
||||
declare <vscale x 4 x float> @llvm.riscv.vfwmacc.mask.nxv4f32.f16(
|
||||
<vscale x 4 x float>,
|
||||
half,
|
||||
<vscale x 4 x half>,
|
||||
<vscale x 4 x i1>,
|
||||
i32);
|
||||
|
||||
define <vscale x 4 x float> @intrinsic_vfwmacc_mask_vf_nxv4f32_f16_nxv4f16(<vscale x 4 x float> %0, half %1, <vscale x 4 x half> %2, <vscale x 4 x i1> %3, i32 %4) nounwind {
|
||||
; CHECK-LABEL: intrinsic_vfwmacc_mask_vf_nxv4f32_f16_nxv4f16:
|
||||
; CHECK: # %bb.0: # %entry
|
||||
; CHECK-NEXT: fmv.h.x ft0, a0
|
||||
; CHECK-NEXT: vsetvli a0, a1, e16,m1,ta,mu
|
||||
; CHECK-NEXT: vfwmacc.vf v16, ft0, v18, v0.t
|
||||
; CHECK-NEXT: jalr zero, 0(ra)
|
||||
entry:
|
||||
%a = call <vscale x 4 x float> @llvm.riscv.vfwmacc.mask.nxv4f32.f16(
|
||||
<vscale x 4 x float> %0,
|
||||
half %1,
|
||||
<vscale x 4 x half> %2,
|
||||
<vscale x 4 x i1> %3,
|
||||
i32 %4)
|
||||
|
||||
ret <vscale x 4 x float> %a
|
||||
}
|
||||
|
||||
declare <vscale x 8 x float> @llvm.riscv.vfwmacc.nxv8f32.f16(
|
||||
<vscale x 8 x float>,
|
||||
half,
|
||||
<vscale x 8 x half>,
|
||||
i32);
|
||||
|
||||
define <vscale x 8 x float> @intrinsic_vfwmacc_vf_nxv8f32_f16_nxv8f16(<vscale x 8 x float> %0, half %1, <vscale x 8 x half> %2, i32 %3) nounwind {
|
||||
; CHECK-LABEL: intrinsic_vfwmacc_vf_nxv8f32_f16_nxv8f16:
|
||||
; CHECK: # %bb.0: # %entry
|
||||
; CHECK-NEXT: fmv.h.x ft0, a0
|
||||
; CHECK-NEXT: vsetvli a0, a1, e16,m2,ta,mu
|
||||
; CHECK-NEXT: vfwmacc.vf v16, ft0, v20
|
||||
; CHECK-NEXT: jalr zero, 0(ra)
|
||||
entry:
|
||||
%a = call <vscale x 8 x float> @llvm.riscv.vfwmacc.nxv8f32.f16(
|
||||
<vscale x 8 x float> %0,
|
||||
half %1,
|
||||
<vscale x 8 x half> %2,
|
||||
i32 %3)
|
||||
|
||||
ret <vscale x 8 x float> %a
|
||||
}
|
||||
|
||||
declare <vscale x 8 x float> @llvm.riscv.vfwmacc.mask.nxv8f32.f16(
|
||||
<vscale x 8 x float>,
|
||||
half,
|
||||
<vscale x 8 x half>,
|
||||
<vscale x 8 x i1>,
|
||||
i32);
|
||||
|
||||
define <vscale x 8 x float> @intrinsic_vfwmacc_mask_vf_nxv8f32_f16_nxv8f16(<vscale x 8 x float> %0, half %1, <vscale x 8 x half> %2, <vscale x 8 x i1> %3, i32 %4) nounwind {
|
||||
; CHECK-LABEL: intrinsic_vfwmacc_mask_vf_nxv8f32_f16_nxv8f16:
|
||||
; CHECK: # %bb.0: # %entry
|
||||
; CHECK-NEXT: fmv.h.x ft0, a0
|
||||
; CHECK-NEXT: vsetvli a0, a1, e16,m2,ta,mu
|
||||
; CHECK-NEXT: vfwmacc.vf v16, ft0, v20, v0.t
|
||||
; CHECK-NEXT: jalr zero, 0(ra)
|
||||
entry:
|
||||
%a = call <vscale x 8 x float> @llvm.riscv.vfwmacc.mask.nxv8f32.f16(
|
||||
<vscale x 8 x float> %0,
|
||||
half %1,
|
||||
<vscale x 8 x half> %2,
|
||||
<vscale x 8 x i1> %3,
|
||||
i32 %4)
|
||||
|
||||
ret <vscale x 8 x float> %a
|
||||
}
|
||||
|
||||
declare <vscale x 16 x float> @llvm.riscv.vfwmacc.nxv16f32.f16(
|
||||
<vscale x 16 x float>,
|
||||
half,
|
||||
<vscale x 16 x half>,
|
||||
i32);
|
||||
|
||||
define <vscale x 16 x float> @intrinsic_vfwmacc_vf_nxv16f32_f16_nxv16f16(<vscale x 16 x float> %0, half %1, <vscale x 16 x half> %2, i32 %3) nounwind {
|
||||
; CHECK-LABEL: intrinsic_vfwmacc_vf_nxv16f32_f16_nxv16f16:
|
||||
; CHECK: # %bb.0: # %entry
|
||||
; CHECK-NEXT: vsetvli a3, zero, e16,m4,ta,mu
|
||||
; CHECK-NEXT: vle16.v v28, (a1)
|
||||
; CHECK-NEXT: fmv.h.x ft0, a0
|
||||
; CHECK-NEXT: vsetvli a0, a2, e16,m4,ta,mu
|
||||
; CHECK-NEXT: vfwmacc.vf v16, ft0, v28
|
||||
; CHECK-NEXT: jalr zero, 0(ra)
|
||||
entry:
|
||||
%a = call <vscale x 16 x float> @llvm.riscv.vfwmacc.nxv16f32.f16(
|
||||
<vscale x 16 x float> %0,
|
||||
half %1,
|
||||
<vscale x 16 x half> %2,
|
||||
i32 %3)
|
||||
|
||||
ret <vscale x 16 x float> %a
|
||||
}
|
||||
|
||||
declare <vscale x 16 x float> @llvm.riscv.vfwmacc.mask.nxv16f32.f16(
|
||||
<vscale x 16 x float>,
|
||||
half,
|
||||
<vscale x 16 x half>,
|
||||
<vscale x 16 x i1>,
|
||||
i32);
|
||||
|
||||
define <vscale x 16 x float> @intrinsic_vfwmacc_mask_vf_nxv16f32_f16_nxv16f16(<vscale x 16 x float> %0, half %1, <vscale x 16 x half> %2, <vscale x 16 x i1> %3, i32 %4) nounwind {
|
||||
; CHECK-LABEL: intrinsic_vfwmacc_mask_vf_nxv16f32_f16_nxv16f16:
|
||||
; CHECK: # %bb.0: # %entry
|
||||
; CHECK-NEXT: vsetvli a3, zero, e16,m4,ta,mu
|
||||
; CHECK-NEXT: vle16.v v28, (a1)
|
||||
; CHECK-NEXT: fmv.h.x ft0, a0
|
||||
; CHECK-NEXT: vsetvli a0, a2, e16,m4,ta,mu
|
||||
; CHECK-NEXT: vfwmacc.vf v16, ft0, v28, v0.t
|
||||
; CHECK-NEXT: jalr zero, 0(ra)
|
||||
entry:
|
||||
%a = call <vscale x 16 x float> @llvm.riscv.vfwmacc.mask.nxv16f32.f16(
|
||||
<vscale x 16 x float> %0,
|
||||
half %1,
|
||||
<vscale x 16 x half> %2,
|
||||
<vscale x 16 x i1> %3,
|
||||
i32 %4)
|
||||
|
||||
ret <vscale x 16 x float> %a
|
||||
}
|
||||
868
test/CodeGen/RISCV/rvv/vfwmacc-rv64.ll
Normal file
868
test/CodeGen/RISCV/rvv/vfwmacc-rv64.ll
Normal file
@ -0,0 +1,868 @@
|
||||
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
|
||||
; RUN: llc -mtriple=riscv64 -mattr=+experimental-v,+d,+experimental-zfh -verify-machineinstrs \
|
||||
; RUN: --riscv-no-aliases < %s | FileCheck %s
|
||||
declare <vscale x 1 x float> @llvm.riscv.vfwmacc.nxv1f32.nxv1f16(
|
||||
<vscale x 1 x float>,
|
||||
<vscale x 1 x half>,
|
||||
<vscale x 1 x half>,
|
||||
i64);
|
||||
|
||||
define <vscale x 1 x float> @intrinsic_vfwmacc_vv_nxv1f32_nxv1f16_nxv1f16(<vscale x 1 x float> %0, <vscale x 1 x half> %1, <vscale x 1 x half> %2, i64 %3) nounwind {
|
||||
; CHECK-LABEL: intrinsic_vfwmacc_vv_nxv1f32_nxv1f16_nxv1f16:
|
||||
; CHECK: # %bb.0: # %entry
|
||||
; CHECK-NEXT: vsetvli a0, a0, e16,mf4,ta,mu
|
||||
; CHECK-NEXT: vfwmacc.vv v16, v17, v18
|
||||
; CHECK-NEXT: jalr zero, 0(ra)
|
||||
entry:
|
||||
%a = call <vscale x 1 x float> @llvm.riscv.vfwmacc.nxv1f32.nxv1f16(
|
||||
<vscale x 1 x float> %0,
|
||||
<vscale x 1 x half> %1,
|
||||
<vscale x 1 x half> %2,
|
||||
i64 %3)
|
||||
|
||||
ret <vscale x 1 x float> %a
|
||||
}
|
||||
|
||||
declare <vscale x 1 x float> @llvm.riscv.vfwmacc.mask.nxv1f32.nxv1f16(
|
||||
<vscale x 1 x float>,
|
||||
<vscale x 1 x half>,
|
||||
<vscale x 1 x half>,
|
||||
<vscale x 1 x i1>,
|
||||
i64);
|
||||
|
||||
define <vscale x 1 x float> @intrinsic_vfwmacc_mask_vv_nxv1f32_nxv1f16_nxv1f16(<vscale x 1 x float> %0, <vscale x 1 x half> %1, <vscale x 1 x half> %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
|
||||
; CHECK-LABEL: intrinsic_vfwmacc_mask_vv_nxv1f32_nxv1f16_nxv1f16:
|
||||
; CHECK: # %bb.0: # %entry
|
||||
; CHECK-NEXT: vsetvli a0, a0, e16,mf4,ta,mu
|
||||
; CHECK-NEXT: vfwmacc.vv v16, v17, v18, v0.t
|
||||
; CHECK-NEXT: jalr zero, 0(ra)
|
||||
entry:
|
||||
%a = call <vscale x 1 x float> @llvm.riscv.vfwmacc.mask.nxv1f32.nxv1f16(
|
||||
<vscale x 1 x float> %0,
|
||||
<vscale x 1 x half> %1,
|
||||
<vscale x 1 x half> %2,
|
||||
<vscale x 1 x i1> %3,
|
||||
i64 %4)
|
||||
|
||||
ret <vscale x 1 x float> %a
|
||||
}
|
||||
|
||||
declare <vscale x 2 x float> @llvm.riscv.vfwmacc.nxv2f32.nxv2f16(
|
||||
<vscale x 2 x float>,
|
||||
<vscale x 2 x half>,
|
||||
<vscale x 2 x half>,
|
||||
i64);
|
||||
|
||||
define <vscale x 2 x float> @intrinsic_vfwmacc_vv_nxv2f32_nxv2f16_nxv2f16(<vscale x 2 x float> %0, <vscale x 2 x half> %1, <vscale x 2 x half> %2, i64 %3) nounwind {
|
||||
; CHECK-LABEL: intrinsic_vfwmacc_vv_nxv2f32_nxv2f16_nxv2f16:
|
||||
; CHECK: # %bb.0: # %entry
|
||||
; CHECK-NEXT: vsetvli a0, a0, e16,mf2,ta,mu
|
||||
; CHECK-NEXT: vfwmacc.vv v16, v17, v18
|
||||
; CHECK-NEXT: jalr zero, 0(ra)
|
||||
entry:
|
||||
%a = call <vscale x 2 x float> @llvm.riscv.vfwmacc.nxv2f32.nxv2f16(
|
||||
<vscale x 2 x float> %0,
|
||||
<vscale x 2 x half> %1,
|
||||
<vscale x 2 x half> %2,
|
||||
i64 %3)
|
||||
|
||||
ret <vscale x 2 x float> %a
|
||||
}
|
||||
|
||||
declare <vscale x 2 x float> @llvm.riscv.vfwmacc.mask.nxv2f32.nxv2f16(
|
||||
<vscale x 2 x float>,
|
||||
<vscale x 2 x half>,
|
||||
<vscale x 2 x half>,
|
||||
<vscale x 2 x i1>,
|
||||
i64);
|
||||
|
||||
define <vscale x 2 x float> @intrinsic_vfwmacc_mask_vv_nxv2f32_nxv2f16_nxv2f16(<vscale x 2 x float> %0, <vscale x 2 x half> %1, <vscale x 2 x half> %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
|
||||
; CHECK-LABEL: intrinsic_vfwmacc_mask_vv_nxv2f32_nxv2f16_nxv2f16:
|
||||
; CHECK: # %bb.0: # %entry
|
||||
; CHECK-NEXT: vsetvli a0, a0, e16,mf2,ta,mu
|
||||
; CHECK-NEXT: vfwmacc.vv v16, v17, v18, v0.t
|
||||
; CHECK-NEXT: jalr zero, 0(ra)
|
||||
entry:
|
||||
%a = call <vscale x 2 x float> @llvm.riscv.vfwmacc.mask.nxv2f32.nxv2f16(
|
||||
<vscale x 2 x float> %0,
|
||||
<vscale x 2 x half> %1,
|
||||
<vscale x 2 x half> %2,
|
||||
<vscale x 2 x i1> %3,
|
||||
i64 %4)
|
||||
|
||||
ret <vscale x 2 x float> %a
|
||||
}
|
||||
|
||||
declare <vscale x 4 x float> @llvm.riscv.vfwmacc.nxv4f32.nxv4f16(
|
||||
<vscale x 4 x float>,
|
||||
<vscale x 4 x half>,
|
||||
<vscale x 4 x half>,
|
||||
i64);
|
||||
|
||||
define <vscale x 4 x float> @intrinsic_vfwmacc_vv_nxv4f32_nxv4f16_nxv4f16(<vscale x 4 x float> %0, <vscale x 4 x half> %1, <vscale x 4 x half> %2, i64 %3) nounwind {
|
||||
; CHECK-LABEL: intrinsic_vfwmacc_vv_nxv4f32_nxv4f16_nxv4f16:
|
||||
; CHECK: # %bb.0: # %entry
|
||||
; CHECK-NEXT: vsetvli a0, a0, e16,m1,ta,mu
|
||||
; CHECK-NEXT: vfwmacc.vv v16, v18, v19
|
||||
; CHECK-NEXT: jalr zero, 0(ra)
|
||||
entry:
|
||||
%a = call <vscale x 4 x float> @llvm.riscv.vfwmacc.nxv4f32.nxv4f16(
|
||||
<vscale x 4 x float> %0,
|
||||
<vscale x 4 x half> %1,
|
||||
<vscale x 4 x half> %2,
|
||||
i64 %3)
|
||||
|
||||
ret <vscale x 4 x float> %a
|
||||
}
|
||||
|
||||
declare <vscale x 4 x float> @llvm.riscv.vfwmacc.mask.nxv4f32.nxv4f16(
|
||||
<vscale x 4 x float>,
|
||||
<vscale x 4 x half>,
|
||||
<vscale x 4 x half>,
|
||||
<vscale x 4 x i1>,
|
||||
i64);
|
||||
|
||||
define <vscale x 4 x float> @intrinsic_vfwmacc_mask_vv_nxv4f32_nxv4f16_nxv4f16(<vscale x 4 x float> %0, <vscale x 4 x half> %1, <vscale x 4 x half> %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
|
||||
; CHECK-LABEL: intrinsic_vfwmacc_mask_vv_nxv4f32_nxv4f16_nxv4f16:
|
||||
; CHECK: # %bb.0: # %entry
|
||||
; CHECK-NEXT: vsetvli a0, a0, e16,m1,ta,mu
|
||||
; CHECK-NEXT: vfwmacc.vv v16, v18, v19, v0.t
|
||||
; CHECK-NEXT: jalr zero, 0(ra)
|
||||
entry:
|
||||
%a = call <vscale x 4 x float> @llvm.riscv.vfwmacc.mask.nxv4f32.nxv4f16(
|
||||
<vscale x 4 x float> %0,
|
||||
<vscale x 4 x half> %1,
|
||||
<vscale x 4 x half> %2,
|
||||
<vscale x 4 x i1> %3,
|
||||
i64 %4)
|
||||
|
||||
ret <vscale x 4 x float> %a
|
||||
}
|
||||
|
||||
declare <vscale x 8 x float> @llvm.riscv.vfwmacc.nxv8f32.nxv8f16(
|
||||
<vscale x 8 x float>,
|
||||
<vscale x 8 x half>,
|
||||
<vscale x 8 x half>,
|
||||
i64);
|
||||
|
||||
define <vscale x 8 x float> @intrinsic_vfwmacc_vv_nxv8f32_nxv8f16_nxv8f16(<vscale x 8 x float> %0, <vscale x 8 x half> %1, <vscale x 8 x half> %2, i64 %3) nounwind {
|
||||
; CHECK-LABEL: intrinsic_vfwmacc_vv_nxv8f32_nxv8f16_nxv8f16:
|
||||
; CHECK: # %bb.0: # %entry
|
||||
; CHECK-NEXT: vsetvli a0, a0, e16,m2,ta,mu
|
||||
; CHECK-NEXT: vfwmacc.vv v16, v20, v22
|
||||
; CHECK-NEXT: jalr zero, 0(ra)
|
||||
entry:
|
||||
%a = call <vscale x 8 x float> @llvm.riscv.vfwmacc.nxv8f32.nxv8f16(
|
||||
<vscale x 8 x float> %0,
|
||||
<vscale x 8 x half> %1,
|
||||
<vscale x 8 x half> %2,
|
||||
i64 %3)
|
||||
|
||||
ret <vscale x 8 x float> %a
|
||||
}
|
||||
|
||||
declare <vscale x 8 x float> @llvm.riscv.vfwmacc.mask.nxv8f32.nxv8f16(
|
||||
<vscale x 8 x float>,
|
||||
<vscale x 8 x half>,
|
||||
<vscale x 8 x half>,
|
||||
<vscale x 8 x i1>,
|
||||
i64);
|
||||
|
||||
define <vscale x 8 x float> @intrinsic_vfwmacc_mask_vv_nxv8f32_nxv8f16_nxv8f16(<vscale x 8 x float> %0, <vscale x 8 x half> %1, <vscale x 8 x half> %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
|
||||
; CHECK-LABEL: intrinsic_vfwmacc_mask_vv_nxv8f32_nxv8f16_nxv8f16:
|
||||
; CHECK: # %bb.0: # %entry
|
||||
; CHECK-NEXT: vsetvli a0, a0, e16,m2,ta,mu
|
||||
; CHECK-NEXT: vfwmacc.vv v16, v20, v22, v0.t
|
||||
; CHECK-NEXT: jalr zero, 0(ra)
|
||||
entry:
|
||||
%a = call <vscale x 8 x float> @llvm.riscv.vfwmacc.mask.nxv8f32.nxv8f16(
|
||||
<vscale x 8 x float> %0,
|
||||
<vscale x 8 x half> %1,
|
||||
<vscale x 8 x half> %2,
|
||||
<vscale x 8 x i1> %3,
|
||||
i64 %4)
|
||||
|
||||
ret <vscale x 8 x float> %a
|
||||
}
|
||||
|
||||
declare <vscale x 16 x float> @llvm.riscv.vfwmacc.nxv16f32.nxv16f16(
|
||||
<vscale x 16 x float>,
|
||||
<vscale x 16 x half>,
|
||||
<vscale x 16 x half>,
|
||||
i64);
|
||||
|
||||
define <vscale x 16 x float> @intrinsic_vfwmacc_vv_nxv16f32_nxv16f16_nxv16f16(<vscale x 16 x float> %0, <vscale x 16 x half> %1, <vscale x 16 x half> %2, i64 %3) nounwind {
|
||||
; CHECK-LABEL: intrinsic_vfwmacc_vv_nxv16f32_nxv16f16_nxv16f16:
|
||||
; CHECK: # %bb.0: # %entry
|
||||
; CHECK-NEXT: vsetvli a3, zero, e16,m4,ta,mu
|
||||
; CHECK-NEXT: vle16.v v28, (a1)
|
||||
; CHECK-NEXT: vle16.v v8, (a0)
|
||||
; CHECK-NEXT: vsetvli a0, a2, e16,m4,ta,mu
|
||||
; CHECK-NEXT: vfwmacc.vv v16, v8, v28
|
||||
; CHECK-NEXT: jalr zero, 0(ra)
|
||||
entry:
|
||||
%a = call <vscale x 16 x float> @llvm.riscv.vfwmacc.nxv16f32.nxv16f16(
|
||||
<vscale x 16 x float> %0,
|
||||
<vscale x 16 x half> %1,
|
||||
<vscale x 16 x half> %2,
|
||||
i64 %3)
|
||||
|
||||
ret <vscale x 16 x float> %a
|
||||
}
|
||||
|
||||
declare <vscale x 16 x float> @llvm.riscv.vfwmacc.mask.nxv16f32.nxv16f16(
|
||||
<vscale x 16 x float>,
|
||||
<vscale x 16 x half>,
|
||||
<vscale x 16 x half>,
|
||||
<vscale x 16 x i1>,
|
||||
i64);
|
||||
|
||||
define <vscale x 16 x float> @intrinsic_vfwmacc_mask_vv_nxv16f32_nxv16f16_nxv16f16(<vscale x 16 x float> %0, <vscale x 16 x half> %1, <vscale x 16 x half> %2, <vscale x 16 x i1> %3, i64 %4) nounwind {
|
||||
; CHECK-LABEL: intrinsic_vfwmacc_mask_vv_nxv16f32_nxv16f16_nxv16f16:
|
||||
; CHECK: # %bb.0: # %entry
|
||||
; CHECK-NEXT: vsetvli a3, zero, e16,m4,ta,mu
|
||||
; CHECK-NEXT: vle16.v v28, (a1)
|
||||
; CHECK-NEXT: vle16.v v8, (a0)
|
||||
; CHECK-NEXT: vsetvli a0, a2, e16,m4,ta,mu
|
||||
; CHECK-NEXT: vfwmacc.vv v16, v8, v28, v0.t
|
||||
; CHECK-NEXT: jalr zero, 0(ra)
|
||||
entry:
|
||||
%a = call <vscale x 16 x float> @llvm.riscv.vfwmacc.mask.nxv16f32.nxv16f16(
|
||||
<vscale x 16 x float> %0,
|
||||
<vscale x 16 x half> %1,
|
||||
<vscale x 16 x half> %2,
|
||||
<vscale x 16 x i1> %3,
|
||||
i64 %4)
|
||||
|
||||
ret <vscale x 16 x float> %a
|
||||
}
|
||||
|
||||
declare <vscale x 1 x double> @llvm.riscv.vfwmacc.nxv1f64.nxv1f32(
|
||||
<vscale x 1 x double>,
|
||||
<vscale x 1 x float>,
|
||||
<vscale x 1 x float>,
|
||||
i64);
|
||||
|
||||
define <vscale x 1 x double> @intrinsic_vfwmacc_vv_nxv1f64_nxv1f32_nxv1f32(<vscale x 1 x double> %0, <vscale x 1 x float> %1, <vscale x 1 x float> %2, i64 %3) nounwind {
|
||||
; CHECK-LABEL: intrinsic_vfwmacc_vv_nxv1f64_nxv1f32_nxv1f32:
|
||||
; CHECK: # %bb.0: # %entry
|
||||
; CHECK-NEXT: vsetvli a0, a0, e32,mf2,ta,mu
|
||||
; CHECK-NEXT: vfwmacc.vv v16, v17, v18
|
||||
; CHECK-NEXT: jalr zero, 0(ra)
|
||||
entry:
|
||||
%a = call <vscale x 1 x double> @llvm.riscv.vfwmacc.nxv1f64.nxv1f32(
|
||||
<vscale x 1 x double> %0,
|
||||
<vscale x 1 x float> %1,
|
||||
<vscale x 1 x float> %2,
|
||||
i64 %3)
|
||||
|
||||
ret <vscale x 1 x double> %a
|
||||
}
|
||||
|
||||
declare <vscale x 1 x double> @llvm.riscv.vfwmacc.mask.nxv1f64.nxv1f32(
|
||||
<vscale x 1 x double>,
|
||||
<vscale x 1 x float>,
|
||||
<vscale x 1 x float>,
|
||||
<vscale x 1 x i1>,
|
||||
i64);
|
||||
|
||||
define <vscale x 1 x double> @intrinsic_vfwmacc_mask_vv_nxv1f64_nxv1f32_nxv1f32(<vscale x 1 x double> %0, <vscale x 1 x float> %1, <vscale x 1 x float> %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
|
||||
; CHECK-LABEL: intrinsic_vfwmacc_mask_vv_nxv1f64_nxv1f32_nxv1f32:
|
||||
; CHECK: # %bb.0: # %entry
|
||||
; CHECK-NEXT: vsetvli a0, a0, e32,mf2,ta,mu
|
||||
; CHECK-NEXT: vfwmacc.vv v16, v17, v18, v0.t
|
||||
; CHECK-NEXT: jalr zero, 0(ra)
|
||||
entry:
|
||||
%a = call <vscale x 1 x double> @llvm.riscv.vfwmacc.mask.nxv1f64.nxv1f32(
|
||||
<vscale x 1 x double> %0,
|
||||
<vscale x 1 x float> %1,
|
||||
<vscale x 1 x float> %2,
|
||||
<vscale x 1 x i1> %3,
|
||||
i64 %4)
|
||||
|
||||
ret <vscale x 1 x double> %a
|
||||
}
|
||||
|
||||
declare <vscale x 2 x double> @llvm.riscv.vfwmacc.nxv2f64.nxv2f32(
|
||||
<vscale x 2 x double>,
|
||||
<vscale x 2 x float>,
|
||||
<vscale x 2 x float>,
|
||||
i64);
|
||||
|
||||
define <vscale x 2 x double> @intrinsic_vfwmacc_vv_nxv2f64_nxv2f32_nxv2f32(<vscale x 2 x double> %0, <vscale x 2 x float> %1, <vscale x 2 x float> %2, i64 %3) nounwind {
|
||||
; CHECK-LABEL: intrinsic_vfwmacc_vv_nxv2f64_nxv2f32_nxv2f32:
|
||||
; CHECK: # %bb.0: # %entry
|
||||
; CHECK-NEXT: vsetvli a0, a0, e32,m1,ta,mu
|
||||
; CHECK-NEXT: vfwmacc.vv v16, v18, v19
|
||||
; CHECK-NEXT: jalr zero, 0(ra)
|
||||
entry:
|
||||
%a = call <vscale x 2 x double> @llvm.riscv.vfwmacc.nxv2f64.nxv2f32(
|
||||
<vscale x 2 x double> %0,
|
||||
<vscale x 2 x float> %1,
|
||||
<vscale x 2 x float> %2,
|
||||
i64 %3)
|
||||
|
||||
ret <vscale x 2 x double> %a
|
||||
}
|
||||
|
||||
declare <vscale x 2 x double> @llvm.riscv.vfwmacc.mask.nxv2f64.nxv2f32(
|
||||
<vscale x 2 x double>,
|
||||
<vscale x 2 x float>,
|
||||
<vscale x 2 x float>,
|
||||
<vscale x 2 x i1>,
|
||||
i64);
|
||||
|
||||
define <vscale x 2 x double> @intrinsic_vfwmacc_mask_vv_nxv2f64_nxv2f32_nxv2f32(<vscale x 2 x double> %0, <vscale x 2 x float> %1, <vscale x 2 x float> %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
|
||||
; CHECK-LABEL: intrinsic_vfwmacc_mask_vv_nxv2f64_nxv2f32_nxv2f32:
|
||||
; CHECK: # %bb.0: # %entry
|
||||
; CHECK-NEXT: vsetvli a0, a0, e32,m1,ta,mu
|
||||
; CHECK-NEXT: vfwmacc.vv v16, v18, v19, v0.t
|
||||
; CHECK-NEXT: jalr zero, 0(ra)
|
||||
entry:
|
||||
%a = call <vscale x 2 x double> @llvm.riscv.vfwmacc.mask.nxv2f64.nxv2f32(
|
||||
<vscale x 2 x double> %0,
|
||||
<vscale x 2 x float> %1,
|
||||
<vscale x 2 x float> %2,
|
||||
<vscale x 2 x i1> %3,
|
||||
i64 %4)
|
||||
|
||||
ret <vscale x 2 x double> %a
|
||||
}
|
||||
|
||||
declare <vscale x 4 x double> @llvm.riscv.vfwmacc.nxv4f64.nxv4f32(
|
||||
<vscale x 4 x double>,
|
||||
<vscale x 4 x float>,
|
||||
<vscale x 4 x float>,
|
||||
i64);
|
||||
|
||||
define <vscale x 4 x double> @intrinsic_vfwmacc_vv_nxv4f64_nxv4f32_nxv4f32(<vscale x 4 x double> %0, <vscale x 4 x float> %1, <vscale x 4 x float> %2, i64 %3) nounwind {
|
||||
; CHECK-LABEL: intrinsic_vfwmacc_vv_nxv4f64_nxv4f32_nxv4f32:
|
||||
; CHECK: # %bb.0: # %entry
|
||||
; CHECK-NEXT: vsetvli a0, a0, e32,m2,ta,mu
|
||||
; CHECK-NEXT: vfwmacc.vv v16, v20, v22
|
||||
; CHECK-NEXT: jalr zero, 0(ra)
|
||||
entry:
|
||||
%a = call <vscale x 4 x double> @llvm.riscv.vfwmacc.nxv4f64.nxv4f32(
|
||||
<vscale x 4 x double> %0,
|
||||
<vscale x 4 x float> %1,
|
||||
<vscale x 4 x float> %2,
|
||||
i64 %3)
|
||||
|
||||
ret <vscale x 4 x double> %a
|
||||
}
|
||||
|
||||
declare <vscale x 4 x double> @llvm.riscv.vfwmacc.mask.nxv4f64.nxv4f32(
|
||||
<vscale x 4 x double>,
|
||||
<vscale x 4 x float>,
|
||||
<vscale x 4 x float>,
|
||||
<vscale x 4 x i1>,
|
||||
i64);
|
||||
|
||||
define <vscale x 4 x double> @intrinsic_vfwmacc_mask_vv_nxv4f64_nxv4f32_nxv4f32(<vscale x 4 x double> %0, <vscale x 4 x float> %1, <vscale x 4 x float> %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
|
||||
; CHECK-LABEL: intrinsic_vfwmacc_mask_vv_nxv4f64_nxv4f32_nxv4f32:
|
||||
; CHECK: # %bb.0: # %entry
|
||||
; CHECK-NEXT: vsetvli a0, a0, e32,m2,ta,mu
|
||||
; CHECK-NEXT: vfwmacc.vv v16, v20, v22, v0.t
|
||||
; CHECK-NEXT: jalr zero, 0(ra)
|
||||
entry:
|
||||
%a = call <vscale x 4 x double> @llvm.riscv.vfwmacc.mask.nxv4f64.nxv4f32(
|
||||
<vscale x 4 x double> %0,
|
||||
<vscale x 4 x float> %1,
|
||||
<vscale x 4 x float> %2,
|
||||
<vscale x 4 x i1> %3,
|
||||
i64 %4)
|
||||
|
||||
ret <vscale x 4 x double> %a
|
||||
}
|
||||
|
||||
declare <vscale x 8 x double> @llvm.riscv.vfwmacc.nxv8f64.nxv8f32(
|
||||
<vscale x 8 x double>,
|
||||
<vscale x 8 x float>,
|
||||
<vscale x 8 x float>,
|
||||
i64);
|
||||
|
||||
define <vscale x 8 x double> @intrinsic_vfwmacc_vv_nxv8f64_nxv8f32_nxv8f32(<vscale x 8 x double> %0, <vscale x 8 x float> %1, <vscale x 8 x float> %2, i64 %3) nounwind {
|
||||
; CHECK-LABEL: intrinsic_vfwmacc_vv_nxv8f64_nxv8f32_nxv8f32:
|
||||
; CHECK: # %bb.0: # %entry
|
||||
; CHECK-NEXT: vsetvli a3, zero, e32,m4,ta,mu
|
||||
; CHECK-NEXT: vle32.v v28, (a1)
|
||||
; CHECK-NEXT: vle32.v v8, (a0)
|
||||
; CHECK-NEXT: vsetvli a0, a2, e32,m4,ta,mu
|
||||
; CHECK-NEXT: vfwmacc.vv v16, v8, v28
|
||||
; CHECK-NEXT: jalr zero, 0(ra)
|
||||
entry:
|
||||
%a = call <vscale x 8 x double> @llvm.riscv.vfwmacc.nxv8f64.nxv8f32(
|
||||
<vscale x 8 x double> %0,
|
||||
<vscale x 8 x float> %1,
|
||||
<vscale x 8 x float> %2,
|
||||
i64 %3)
|
||||
|
||||
ret <vscale x 8 x double> %a
|
||||
}
|
||||
|
||||
declare <vscale x 8 x double> @llvm.riscv.vfwmacc.mask.nxv8f64.nxv8f32(
|
||||
<vscale x 8 x double>,
|
||||
<vscale x 8 x float>,
|
||||
<vscale x 8 x float>,
|
||||
<vscale x 8 x i1>,
|
||||
i64);
|
||||
|
||||
define <vscale x 8 x double> @intrinsic_vfwmacc_mask_vv_nxv8f64_nxv8f32_nxv8f32(<vscale x 8 x double> %0, <vscale x 8 x float> %1, <vscale x 8 x float> %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
|
||||
; CHECK-LABEL: intrinsic_vfwmacc_mask_vv_nxv8f64_nxv8f32_nxv8f32:
|
||||
; CHECK: # %bb.0: # %entry
|
||||
; CHECK-NEXT: vsetvli a3, zero, e32,m4,ta,mu
|
||||
; CHECK-NEXT: vle32.v v28, (a1)
|
||||
; CHECK-NEXT: vle32.v v8, (a0)
|
||||
; CHECK-NEXT: vsetvli a0, a2, e32,m4,ta,mu
|
||||
; CHECK-NEXT: vfwmacc.vv v16, v8, v28, v0.t
|
||||
; CHECK-NEXT: jalr zero, 0(ra)
|
||||
entry:
|
||||
%a = call <vscale x 8 x double> @llvm.riscv.vfwmacc.mask.nxv8f64.nxv8f32(
|
||||
<vscale x 8 x double> %0,
|
||||
<vscale x 8 x float> %1,
|
||||
<vscale x 8 x float> %2,
|
||||
<vscale x 8 x i1> %3,
|
||||
i64 %4)
|
||||
|
||||
ret <vscale x 8 x double> %a
|
||||
}
|
||||
|
||||
declare <vscale x 1 x float> @llvm.riscv.vfwmacc.nxv1f32.f16(
|
||||
<vscale x 1 x float>,
|
||||
half,
|
||||
<vscale x 1 x half>,
|
||||
i64);
|
||||
|
||||
define <vscale x 1 x float> @intrinsic_vfwmacc_vf_nxv1f32_f16_nxv1f16(<vscale x 1 x float> %0, half %1, <vscale x 1 x half> %2, i64 %3) nounwind {
|
||||
; CHECK-LABEL: intrinsic_vfwmacc_vf_nxv1f32_f16_nxv1f16:
|
||||
; CHECK: # %bb.0: # %entry
|
||||
; CHECK-NEXT: fmv.h.x ft0, a0
|
||||
; CHECK-NEXT: vsetvli a0, a1, e16,mf4,ta,mu
|
||||
; CHECK-NEXT: vfwmacc.vf v16, ft0, v17
|
||||
; CHECK-NEXT: jalr zero, 0(ra)
|
||||
entry:
|
||||
%a = call <vscale x 1 x float> @llvm.riscv.vfwmacc.nxv1f32.f16(
|
||||
<vscale x 1 x float> %0,
|
||||
half %1,
|
||||
<vscale x 1 x half> %2,
|
||||
i64 %3)
|
||||
|
||||
ret <vscale x 1 x float> %a
|
||||
}
|
||||
|
||||
declare <vscale x 1 x float> @llvm.riscv.vfwmacc.mask.nxv1f32.f16(
|
||||
<vscale x 1 x float>,
|
||||
half,
|
||||
<vscale x 1 x half>,
|
||||
<vscale x 1 x i1>,
|
||||
i64);
|
||||
|
||||
define <vscale x 1 x float> @intrinsic_vfwmacc_mask_vf_nxv1f32_f16_nxv1f16(<vscale x 1 x float> %0, half %1, <vscale x 1 x half> %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
|
||||
; CHECK-LABEL: intrinsic_vfwmacc_mask_vf_nxv1f32_f16_nxv1f16:
|
||||
; CHECK: # %bb.0: # %entry
|
||||
; CHECK-NEXT: fmv.h.x ft0, a0
|
||||
; CHECK-NEXT: vsetvli a0, a1, e16,mf4,ta,mu
|
||||
; CHECK-NEXT: vfwmacc.vf v16, ft0, v17, v0.t
|
||||
; CHECK-NEXT: jalr zero, 0(ra)
|
||||
entry:
|
||||
%a = call <vscale x 1 x float> @llvm.riscv.vfwmacc.mask.nxv1f32.f16(
|
||||
<vscale x 1 x float> %0,
|
||||
half %1,
|
||||
<vscale x 1 x half> %2,
|
||||
<vscale x 1 x i1> %3,
|
||||
i64 %4)
|
||||
|
||||
ret <vscale x 1 x float> %a
|
||||
}
|
||||
|
||||
declare <vscale x 2 x float> @llvm.riscv.vfwmacc.nxv2f32.f16(
|
||||
<vscale x 2 x float>,
|
||||
half,
|
||||
<vscale x 2 x half>,
|
||||
i64);
|
||||
|
||||
define <vscale x 2 x float> @intrinsic_vfwmacc_vf_nxv2f32_f16_nxv2f16(<vscale x 2 x float> %0, half %1, <vscale x 2 x half> %2, i64 %3) nounwind {
|
||||
; CHECK-LABEL: intrinsic_vfwmacc_vf_nxv2f32_f16_nxv2f16:
|
||||
; CHECK: # %bb.0: # %entry
|
||||
; CHECK-NEXT: fmv.h.x ft0, a0
|
||||
; CHECK-NEXT: vsetvli a0, a1, e16,mf2,ta,mu
|
||||
; CHECK-NEXT: vfwmacc.vf v16, ft0, v17
|
||||
; CHECK-NEXT: jalr zero, 0(ra)
|
||||
entry:
|
||||
%a = call <vscale x 2 x float> @llvm.riscv.vfwmacc.nxv2f32.f16(
|
||||
<vscale x 2 x float> %0,
|
||||
half %1,
|
||||
<vscale x 2 x half> %2,
|
||||
i64 %3)
|
||||
|
||||
ret <vscale x 2 x float> %a
|
||||
}
|
||||
|
||||
declare <vscale x 2 x float> @llvm.riscv.vfwmacc.mask.nxv2f32.f16(
|
||||
<vscale x 2 x float>,
|
||||
half,
|
||||
<vscale x 2 x half>,
|
||||
<vscale x 2 x i1>,
|
||||
i64);
|
||||
|
||||
define <vscale x 2 x float> @intrinsic_vfwmacc_mask_vf_nxv2f32_f16_nxv2f16(<vscale x 2 x float> %0, half %1, <vscale x 2 x half> %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
|
||||
; CHECK-LABEL: intrinsic_vfwmacc_mask_vf_nxv2f32_f16_nxv2f16:
|
||||
; CHECK: # %bb.0: # %entry
|
||||
; CHECK-NEXT: fmv.h.x ft0, a0
|
||||
; CHECK-NEXT: vsetvli a0, a1, e16,mf2,ta,mu
|
||||
; CHECK-NEXT: vfwmacc.vf v16, ft0, v17, v0.t
|
||||
; CHECK-NEXT: jalr zero, 0(ra)
|
||||
entry:
|
||||
%a = call <vscale x 2 x float> @llvm.riscv.vfwmacc.mask.nxv2f32.f16(
|
||||
<vscale x 2 x float> %0,
|
||||
half %1,
|
||||
<vscale x 2 x half> %2,
|
||||
<vscale x 2 x i1> %3,
|
||||
i64 %4)
|
||||
|
||||
ret <vscale x 2 x float> %a
|
||||
}
|
||||
|
||||
declare <vscale x 4 x float> @llvm.riscv.vfwmacc.nxv4f32.f16(
|
||||
<vscale x 4 x float>,
|
||||
half,
|
||||
<vscale x 4 x half>,
|
||||
i64);
|
||||
|
||||
define <vscale x 4 x float> @intrinsic_vfwmacc_vf_nxv4f32_f16_nxv4f16(<vscale x 4 x float> %0, half %1, <vscale x 4 x half> %2, i64 %3) nounwind {
|
||||
; CHECK-LABEL: intrinsic_vfwmacc_vf_nxv4f32_f16_nxv4f16:
|
||||
; CHECK: # %bb.0: # %entry
|
||||
; CHECK-NEXT: fmv.h.x ft0, a0
|
||||
; CHECK-NEXT: vsetvli a0, a1, e16,m1,ta,mu
|
||||
; CHECK-NEXT: vfwmacc.vf v16, ft0, v18
|
||||
; CHECK-NEXT: jalr zero, 0(ra)
|
||||
entry:
|
||||
%a = call <vscale x 4 x float> @llvm.riscv.vfwmacc.nxv4f32.f16(
|
||||
<vscale x 4 x float> %0,
|
||||
half %1,
|
||||
<vscale x 4 x half> %2,
|
||||
i64 %3)
|
||||
|
||||
ret <vscale x 4 x float> %a
|
||||
}
|
||||
|
||||
declare <vscale x 4 x float> @llvm.riscv.vfwmacc.mask.nxv4f32.f16(
|
||||
<vscale x 4 x float>,
|
||||
half,
|
||||
<vscale x 4 x half>,
|
||||
<vscale x 4 x i1>,
|
||||
i64);
|
||||
|
||||
define <vscale x 4 x float> @intrinsic_vfwmacc_mask_vf_nxv4f32_f16_nxv4f16(<vscale x 4 x float> %0, half %1, <vscale x 4 x half> %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
|
||||
; CHECK-LABEL: intrinsic_vfwmacc_mask_vf_nxv4f32_f16_nxv4f16:
|
||||
; CHECK: # %bb.0: # %entry
|
||||
; CHECK-NEXT: fmv.h.x ft0, a0
|
||||
; CHECK-NEXT: vsetvli a0, a1, e16,m1,ta,mu
|
||||
; CHECK-NEXT: vfwmacc.vf v16, ft0, v18, v0.t
|
||||
; CHECK-NEXT: jalr zero, 0(ra)
|
||||
entry:
|
||||
%a = call <vscale x 4 x float> @llvm.riscv.vfwmacc.mask.nxv4f32.f16(
|
||||
<vscale x 4 x float> %0,
|
||||
half %1,
|
||||
<vscale x 4 x half> %2,
|
||||
<vscale x 4 x i1> %3,
|
||||
i64 %4)
|
||||
|
||||
ret <vscale x 4 x float> %a
|
||||
}
|
||||
|
||||
declare <vscale x 8 x float> @llvm.riscv.vfwmacc.nxv8f32.f16(
|
||||
<vscale x 8 x float>,
|
||||
half,
|
||||
<vscale x 8 x half>,
|
||||
i64);
|
||||
|
||||
define <vscale x 8 x float> @intrinsic_vfwmacc_vf_nxv8f32_f16_nxv8f16(<vscale x 8 x float> %0, half %1, <vscale x 8 x half> %2, i64 %3) nounwind {
|
||||
; CHECK-LABEL: intrinsic_vfwmacc_vf_nxv8f32_f16_nxv8f16:
|
||||
; CHECK: # %bb.0: # %entry
|
||||
; CHECK-NEXT: fmv.h.x ft0, a0
|
||||
; CHECK-NEXT: vsetvli a0, a1, e16,m2,ta,mu
|
||||
; CHECK-NEXT: vfwmacc.vf v16, ft0, v20
|
||||
; CHECK-NEXT: jalr zero, 0(ra)
|
||||
entry:
|
||||
%a = call <vscale x 8 x float> @llvm.riscv.vfwmacc.nxv8f32.f16(
|
||||
<vscale x 8 x float> %0,
|
||||
half %1,
|
||||
<vscale x 8 x half> %2,
|
||||
i64 %3)
|
||||
|
||||
ret <vscale x 8 x float> %a
|
||||
}
|
||||
|
||||
declare <vscale x 8 x float> @llvm.riscv.vfwmacc.mask.nxv8f32.f16(
|
||||
<vscale x 8 x float>,
|
||||
half,
|
||||
<vscale x 8 x half>,
|
||||
<vscale x 8 x i1>,
|
||||
i64);
|
||||
|
||||
define <vscale x 8 x float> @intrinsic_vfwmacc_mask_vf_nxv8f32_f16_nxv8f16(<vscale x 8 x float> %0, half %1, <vscale x 8 x half> %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
|
||||
; CHECK-LABEL: intrinsic_vfwmacc_mask_vf_nxv8f32_f16_nxv8f16:
|
||||
; CHECK: # %bb.0: # %entry
|
||||
; CHECK-NEXT: fmv.h.x ft0, a0
|
||||
; CHECK-NEXT: vsetvli a0, a1, e16,m2,ta,mu
|
||||
; CHECK-NEXT: vfwmacc.vf v16, ft0, v20, v0.t
|
||||
; CHECK-NEXT: jalr zero, 0(ra)
|
||||
entry:
|
||||
%a = call <vscale x 8 x float> @llvm.riscv.vfwmacc.mask.nxv8f32.f16(
|
||||
<vscale x 8 x float> %0,
|
||||
half %1,
|
||||
<vscale x 8 x half> %2,
|
||||
<vscale x 8 x i1> %3,
|
||||
i64 %4)
|
||||
|
||||
ret <vscale x 8 x float> %a
|
||||
}
|
||||
|
||||
declare <vscale x 16 x float> @llvm.riscv.vfwmacc.nxv16f32.f16(
|
||||
<vscale x 16 x float>,
|
||||
half,
|
||||
<vscale x 16 x half>,
|
||||
i64);
|
||||
|
||||
define <vscale x 16 x float> @intrinsic_vfwmacc_vf_nxv16f32_f16_nxv16f16(<vscale x 16 x float> %0, half %1, <vscale x 16 x half> %2, i64 %3) nounwind {
|
||||
; CHECK-LABEL: intrinsic_vfwmacc_vf_nxv16f32_f16_nxv16f16:
|
||||
; CHECK: # %bb.0: # %entry
|
||||
; CHECK-NEXT: vsetvli a3, zero, e16,m4,ta,mu
|
||||
; CHECK-NEXT: vle16.v v28, (a1)
|
||||
; CHECK-NEXT: fmv.h.x ft0, a0
|
||||
; CHECK-NEXT: vsetvli a0, a2, e16,m4,ta,mu
|
||||
; CHECK-NEXT: vfwmacc.vf v16, ft0, v28
|
||||
; CHECK-NEXT: jalr zero, 0(ra)
|
||||
entry:
|
||||
%a = call <vscale x 16 x float> @llvm.riscv.vfwmacc.nxv16f32.f16(
|
||||
<vscale x 16 x float> %0,
|
||||
half %1,
|
||||
<vscale x 16 x half> %2,
|
||||
i64 %3)
|
||||
|
||||
ret <vscale x 16 x float> %a
|
||||
}
|
||||
|
||||
declare <vscale x 16 x float> @llvm.riscv.vfwmacc.mask.nxv16f32.f16(
|
||||
<vscale x 16 x float>,
|
||||
half,
|
||||
<vscale x 16 x half>,
|
||||
<vscale x 16 x i1>,
|
||||
i64);
|
||||
|
||||
define <vscale x 16 x float> @intrinsic_vfwmacc_mask_vf_nxv16f32_f16_nxv16f16(<vscale x 16 x float> %0, half %1, <vscale x 16 x half> %2, <vscale x 16 x i1> %3, i64 %4) nounwind {
|
||||
; CHECK-LABEL: intrinsic_vfwmacc_mask_vf_nxv16f32_f16_nxv16f16:
|
||||
; CHECK: # %bb.0: # %entry
|
||||
; CHECK-NEXT: vsetvli a3, zero, e16,m4,ta,mu
|
||||
; CHECK-NEXT: vle16.v v28, (a1)
|
||||
; CHECK-NEXT: fmv.h.x ft0, a0
|
||||
; CHECK-NEXT: vsetvli a0, a2, e16,m4,ta,mu
|
||||
; CHECK-NEXT: vfwmacc.vf v16, ft0, v28, v0.t
|
||||
; CHECK-NEXT: jalr zero, 0(ra)
|
||||
entry:
|
||||
%a = call <vscale x 16 x float> @llvm.riscv.vfwmacc.mask.nxv16f32.f16(
|
||||
<vscale x 16 x float> %0,
|
||||
half %1,
|
||||
<vscale x 16 x half> %2,
|
||||
<vscale x 16 x i1> %3,
|
||||
i64 %4)
|
||||
|
||||
ret <vscale x 16 x float> %a
|
||||
}
|
||||
|
||||
declare <vscale x 1 x double> @llvm.riscv.vfwmacc.nxv1f64.f32(
|
||||
<vscale x 1 x double>,
|
||||
float,
|
||||
<vscale x 1 x float>,
|
||||
i64);
|
||||
|
||||
define <vscale x 1 x double> @intrinsic_vfwmacc_vf_nxv1f64_f32_nxv1f32(<vscale x 1 x double> %0, float %1, <vscale x 1 x float> %2, i64 %3) nounwind {
|
||||
; CHECK-LABEL: intrinsic_vfwmacc_vf_nxv1f64_f32_nxv1f32:
|
||||
; CHECK: # %bb.0: # %entry
|
||||
; CHECK-NEXT: fmv.w.x ft0, a0
|
||||
; CHECK-NEXT: vsetvli a0, a1, e32,mf2,ta,mu
|
||||
; CHECK-NEXT: vfwmacc.vf v16, ft0, v17
|
||||
; CHECK-NEXT: jalr zero, 0(ra)
|
||||
entry:
|
||||
%a = call <vscale x 1 x double> @llvm.riscv.vfwmacc.nxv1f64.f32(
|
||||
<vscale x 1 x double> %0,
|
||||
float %1,
|
||||
<vscale x 1 x float> %2,
|
||||
i64 %3)
|
||||
|
||||
ret <vscale x 1 x double> %a
|
||||
}
|
||||
|
||||
declare <vscale x 1 x double> @llvm.riscv.vfwmacc.mask.nxv1f64.f32(
|
||||
<vscale x 1 x double>,
|
||||
float,
|
||||
<vscale x 1 x float>,
|
||||
<vscale x 1 x i1>,
|
||||
i64);
|
||||
|
||||
define <vscale x 1 x double> @intrinsic_vfwmacc_mask_vf_nxv1f64_f32_nxv1f32(<vscale x 1 x double> %0, float %1, <vscale x 1 x float> %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
|
||||
; CHECK-LABEL: intrinsic_vfwmacc_mask_vf_nxv1f64_f32_nxv1f32:
|
||||
; CHECK: # %bb.0: # %entry
|
||||
; CHECK-NEXT: fmv.w.x ft0, a0
|
||||
; CHECK-NEXT: vsetvli a0, a1, e32,mf2,ta,mu
|
||||
; CHECK-NEXT: vfwmacc.vf v16, ft0, v17, v0.t
|
||||
; CHECK-NEXT: jalr zero, 0(ra)
|
||||
entry:
|
||||
%a = call <vscale x 1 x double> @llvm.riscv.vfwmacc.mask.nxv1f64.f32(
|
||||
<vscale x 1 x double> %0,
|
||||
float %1,
|
||||
<vscale x 1 x float> %2,
|
||||
<vscale x 1 x i1> %3,
|
||||
i64 %4)
|
||||
|
||||
ret <vscale x 1 x double> %a
|
||||
}
|
||||
|
||||
declare <vscale x 2 x double> @llvm.riscv.vfwmacc.nxv2f64.f32(
|
||||
<vscale x 2 x double>,
|
||||
float,
|
||||
<vscale x 2 x float>,
|
||||
i64);
|
||||
|
||||
define <vscale x 2 x double> @intrinsic_vfwmacc_vf_nxv2f64_f32_nxv2f32(<vscale x 2 x double> %0, float %1, <vscale x 2 x float> %2, i64 %3) nounwind {
|
||||
; CHECK-LABEL: intrinsic_vfwmacc_vf_nxv2f64_f32_nxv2f32:
|
||||
; CHECK: # %bb.0: # %entry
|
||||
; CHECK-NEXT: fmv.w.x ft0, a0
|
||||
; CHECK-NEXT: vsetvli a0, a1, e32,m1,ta,mu
|
||||
; CHECK-NEXT: vfwmacc.vf v16, ft0, v18
|
||||
; CHECK-NEXT: jalr zero, 0(ra)
|
||||
entry:
|
||||
%a = call <vscale x 2 x double> @llvm.riscv.vfwmacc.nxv2f64.f32(
|
||||
<vscale x 2 x double> %0,
|
||||
float %1,
|
||||
<vscale x 2 x float> %2,
|
||||
i64 %3)
|
||||
|
||||
ret <vscale x 2 x double> %a
|
||||
}
|
||||
|
||||
declare <vscale x 2 x double> @llvm.riscv.vfwmacc.mask.nxv2f64.f32(
|
||||
<vscale x 2 x double>,
|
||||
float,
|
||||
<vscale x 2 x float>,
|
||||
<vscale x 2 x i1>,
|
||||
i64);
|
||||
|
||||
define <vscale x 2 x double> @intrinsic_vfwmacc_mask_vf_nxv2f64_f32_nxv2f32(<vscale x 2 x double> %0, float %1, <vscale x 2 x float> %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
|
||||
; CHECK-LABEL: intrinsic_vfwmacc_mask_vf_nxv2f64_f32_nxv2f32:
|
||||
; CHECK: # %bb.0: # %entry
|
||||
; CHECK-NEXT: fmv.w.x ft0, a0
|
||||
; CHECK-NEXT: vsetvli a0, a1, e32,m1,ta,mu
|
||||
; CHECK-NEXT: vfwmacc.vf v16, ft0, v18, v0.t
|
||||
; CHECK-NEXT: jalr zero, 0(ra)
|
||||
entry:
|
||||
%a = call <vscale x 2 x double> @llvm.riscv.vfwmacc.mask.nxv2f64.f32(
|
||||
<vscale x 2 x double> %0,
|
||||
float %1,
|
||||
<vscale x 2 x float> %2,
|
||||
<vscale x 2 x i1> %3,
|
||||
i64 %4)
|
||||
|
||||
ret <vscale x 2 x double> %a
|
||||
}
|
||||
|
||||
declare <vscale x 4 x double> @llvm.riscv.vfwmacc.nxv4f64.f32(
|
||||
<vscale x 4 x double>,
|
||||
float,
|
||||
<vscale x 4 x float>,
|
||||
i64);
|
||||
|
||||
define <vscale x 4 x double> @intrinsic_vfwmacc_vf_nxv4f64_f32_nxv4f32(<vscale x 4 x double> %0, float %1, <vscale x 4 x float> %2, i64 %3) nounwind {
|
||||
; CHECK-LABEL: intrinsic_vfwmacc_vf_nxv4f64_f32_nxv4f32:
|
||||
; CHECK: # %bb.0: # %entry
|
||||
; CHECK-NEXT: fmv.w.x ft0, a0
|
||||
; CHECK-NEXT: vsetvli a0, a1, e32,m2,ta,mu
|
||||
; CHECK-NEXT: vfwmacc.vf v16, ft0, v20
|
||||
; CHECK-NEXT: jalr zero, 0(ra)
|
||||
entry:
|
||||
%a = call <vscale x 4 x double> @llvm.riscv.vfwmacc.nxv4f64.f32(
|
||||
<vscale x 4 x double> %0,
|
||||
float %1,
|
||||
<vscale x 4 x float> %2,
|
||||
i64 %3)
|
||||
|
||||
ret <vscale x 4 x double> %a
|
||||
}
|
||||
|
||||
declare <vscale x 4 x double> @llvm.riscv.vfwmacc.mask.nxv4f64.f32(
|
||||
<vscale x 4 x double>,
|
||||
float,
|
||||
<vscale x 4 x float>,
|
||||
<vscale x 4 x i1>,
|
||||
i64);
|
||||
|
||||
define <vscale x 4 x double> @intrinsic_vfwmacc_mask_vf_nxv4f64_f32_nxv4f32(<vscale x 4 x double> %0, float %1, <vscale x 4 x float> %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
|
||||
; CHECK-LABEL: intrinsic_vfwmacc_mask_vf_nxv4f64_f32_nxv4f32:
|
||||
; CHECK: # %bb.0: # %entry
|
||||
; CHECK-NEXT: fmv.w.x ft0, a0
|
||||
; CHECK-NEXT: vsetvli a0, a1, e32,m2,ta,mu
|
||||
; CHECK-NEXT: vfwmacc.vf v16, ft0, v20, v0.t
|
||||
; CHECK-NEXT: jalr zero, 0(ra)
|
||||
entry:
|
||||
%a = call <vscale x 4 x double> @llvm.riscv.vfwmacc.mask.nxv4f64.f32(
|
||||
<vscale x 4 x double> %0,
|
||||
float %1,
|
||||
<vscale x 4 x float> %2,
|
||||
<vscale x 4 x i1> %3,
|
||||
i64 %4)
|
||||
|
||||
ret <vscale x 4 x double> %a
|
||||
}
|
||||
|
||||
declare <vscale x 8 x double> @llvm.riscv.vfwmacc.nxv8f64.f32(
|
||||
<vscale x 8 x double>,
|
||||
float,
|
||||
<vscale x 8 x float>,
|
||||
i64);
|
||||
|
||||
define <vscale x 8 x double> @intrinsic_vfwmacc_vf_nxv8f64_f32_nxv8f32(<vscale x 8 x double> %0, float %1, <vscale x 8 x float> %2, i64 %3) nounwind {
|
||||
; CHECK-LABEL: intrinsic_vfwmacc_vf_nxv8f64_f32_nxv8f32:
|
||||
; CHECK: # %bb.0: # %entry
|
||||
; CHECK-NEXT: vsetvli a3, zero, e32,m4,ta,mu
|
||||
; CHECK-NEXT: vle32.v v28, (a1)
|
||||
; CHECK-NEXT: fmv.w.x ft0, a0
|
||||
; CHECK-NEXT: vsetvli a0, a2, e32,m4,ta,mu
|
||||
; CHECK-NEXT: vfwmacc.vf v16, ft0, v28
|
||||
; CHECK-NEXT: jalr zero, 0(ra)
|
||||
entry:
|
||||
%a = call <vscale x 8 x double> @llvm.riscv.vfwmacc.nxv8f64.f32(
|
||||
<vscale x 8 x double> %0,
|
||||
float %1,
|
||||
<vscale x 8 x float> %2,
|
||||
i64 %3)
|
||||
|
||||
ret <vscale x 8 x double> %a
|
||||
}
|
||||
|
||||
declare <vscale x 8 x double> @llvm.riscv.vfwmacc.mask.nxv8f64.f32(
|
||||
<vscale x 8 x double>,
|
||||
float,
|
||||
<vscale x 8 x float>,
|
||||
<vscale x 8 x i1>,
|
||||
i64);
|
||||
|
||||
define <vscale x 8 x double> @intrinsic_vfwmacc_mask_vf_nxv8f64_f32_nxv8f32(<vscale x 8 x double> %0, float %1, <vscale x 8 x float> %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
|
||||
; CHECK-LABEL: intrinsic_vfwmacc_mask_vf_nxv8f64_f32_nxv8f32:
|
||||
; CHECK: # %bb.0: # %entry
|
||||
; CHECK-NEXT: vsetvli a3, zero, e32,m4,ta,mu
|
||||
; CHECK-NEXT: vle32.v v28, (a1)
|
||||
; CHECK-NEXT: fmv.w.x ft0, a0
|
||||
; CHECK-NEXT: vsetvli a0, a2, e32,m4,ta,mu
|
||||
; CHECK-NEXT: vfwmacc.vf v16, ft0, v28, v0.t
|
||||
; CHECK-NEXT: jalr zero, 0(ra)
|
||||
entry:
|
||||
%a = call <vscale x 8 x double> @llvm.riscv.vfwmacc.mask.nxv8f64.f32(
|
||||
<vscale x 8 x double> %0,
|
||||
float %1,
|
||||
<vscale x 8 x float> %2,
|
||||
<vscale x 8 x i1> %3,
|
||||
i64 %4)
|
||||
|
||||
ret <vscale x 8 x double> %a
|
||||
}
|
||||
482
test/CodeGen/RISCV/rvv/vfwmsac-rv32.ll
Normal file
482
test/CodeGen/RISCV/rvv/vfwmsac-rv32.ll
Normal file
@ -0,0 +1,482 @@
|
||||
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
|
||||
; RUN: llc -mtriple=riscv32 -mattr=+experimental-v,+f,+experimental-zfh -verify-machineinstrs \
|
||||
; RUN: --riscv-no-aliases < %s | FileCheck %s
|
||||
declare <vscale x 1 x float> @llvm.riscv.vfwmsac.nxv1f32.nxv1f16(
|
||||
<vscale x 1 x float>,
|
||||
<vscale x 1 x half>,
|
||||
<vscale x 1 x half>,
|
||||
i32);
|
||||
|
||||
define <vscale x 1 x float> @intrinsic_vfwmsac_vv_nxv1f32_nxv1f16_nxv1f16(<vscale x 1 x float> %0, <vscale x 1 x half> %1, <vscale x 1 x half> %2, i32 %3) nounwind {
|
||||
; CHECK-LABEL: intrinsic_vfwmsac_vv_nxv1f32_nxv1f16_nxv1f16:
|
||||
; CHECK: # %bb.0: # %entry
|
||||
; CHECK-NEXT: vsetvli a0, a0, e16,mf4,ta,mu
|
||||
; CHECK-NEXT: vfwmsac.vv v16, v17, v18
|
||||
; CHECK-NEXT: jalr zero, 0(ra)
|
||||
entry:
|
||||
%a = call <vscale x 1 x float> @llvm.riscv.vfwmsac.nxv1f32.nxv1f16(
|
||||
<vscale x 1 x float> %0,
|
||||
<vscale x 1 x half> %1,
|
||||
<vscale x 1 x half> %2,
|
||||
i32 %3)
|
||||
|
||||
ret <vscale x 1 x float> %a
|
||||
}
|
||||
|
||||
declare <vscale x 1 x float> @llvm.riscv.vfwmsac.mask.nxv1f32.nxv1f16(
|
||||
<vscale x 1 x float>,
|
||||
<vscale x 1 x half>,
|
||||
<vscale x 1 x half>,
|
||||
<vscale x 1 x i1>,
|
||||
i32);
|
||||
|
||||
define <vscale x 1 x float> @intrinsic_vfwmsac_mask_vv_nxv1f32_nxv1f16_nxv1f16(<vscale x 1 x float> %0, <vscale x 1 x half> %1, <vscale x 1 x half> %2, <vscale x 1 x i1> %3, i32 %4) nounwind {
|
||||
; CHECK-LABEL: intrinsic_vfwmsac_mask_vv_nxv1f32_nxv1f16_nxv1f16:
|
||||
; CHECK: # %bb.0: # %entry
|
||||
; CHECK-NEXT: vsetvli a0, a0, e16,mf4,ta,mu
|
||||
; CHECK-NEXT: vfwmsac.vv v16, v17, v18, v0.t
|
||||
; CHECK-NEXT: jalr zero, 0(ra)
|
||||
entry:
|
||||
%a = call <vscale x 1 x float> @llvm.riscv.vfwmsac.mask.nxv1f32.nxv1f16(
|
||||
<vscale x 1 x float> %0,
|
||||
<vscale x 1 x half> %1,
|
||||
<vscale x 1 x half> %2,
|
||||
<vscale x 1 x i1> %3,
|
||||
i32 %4)
|
||||
|
||||
ret <vscale x 1 x float> %a
|
||||
}
|
||||
|
||||
declare <vscale x 2 x float> @llvm.riscv.vfwmsac.nxv2f32.nxv2f16(
|
||||
<vscale x 2 x float>,
|
||||
<vscale x 2 x half>,
|
||||
<vscale x 2 x half>,
|
||||
i32);
|
||||
|
||||
define <vscale x 2 x float> @intrinsic_vfwmsac_vv_nxv2f32_nxv2f16_nxv2f16(<vscale x 2 x float> %0, <vscale x 2 x half> %1, <vscale x 2 x half> %2, i32 %3) nounwind {
|
||||
; CHECK-LABEL: intrinsic_vfwmsac_vv_nxv2f32_nxv2f16_nxv2f16:
|
||||
; CHECK: # %bb.0: # %entry
|
||||
; CHECK-NEXT: vsetvli a0, a0, e16,mf2,ta,mu
|
||||
; CHECK-NEXT: vfwmsac.vv v16, v17, v18
|
||||
; CHECK-NEXT: jalr zero, 0(ra)
|
||||
entry:
|
||||
%a = call <vscale x 2 x float> @llvm.riscv.vfwmsac.nxv2f32.nxv2f16(
|
||||
<vscale x 2 x float> %0,
|
||||
<vscale x 2 x half> %1,
|
||||
<vscale x 2 x half> %2,
|
||||
i32 %3)
|
||||
|
||||
ret <vscale x 2 x float> %a
|
||||
}
|
||||
|
||||
declare <vscale x 2 x float> @llvm.riscv.vfwmsac.mask.nxv2f32.nxv2f16(
|
||||
<vscale x 2 x float>,
|
||||
<vscale x 2 x half>,
|
||||
<vscale x 2 x half>,
|
||||
<vscale x 2 x i1>,
|
||||
i32);
|
||||
|
||||
define <vscale x 2 x float> @intrinsic_vfwmsac_mask_vv_nxv2f32_nxv2f16_nxv2f16(<vscale x 2 x float> %0, <vscale x 2 x half> %1, <vscale x 2 x half> %2, <vscale x 2 x i1> %3, i32 %4) nounwind {
|
||||
; CHECK-LABEL: intrinsic_vfwmsac_mask_vv_nxv2f32_nxv2f16_nxv2f16:
|
||||
; CHECK: # %bb.0: # %entry
|
||||
; CHECK-NEXT: vsetvli a0, a0, e16,mf2,ta,mu
|
||||
; CHECK-NEXT: vfwmsac.vv v16, v17, v18, v0.t
|
||||
; CHECK-NEXT: jalr zero, 0(ra)
|
||||
entry:
|
||||
%a = call <vscale x 2 x float> @llvm.riscv.vfwmsac.mask.nxv2f32.nxv2f16(
|
||||
<vscale x 2 x float> %0,
|
||||
<vscale x 2 x half> %1,
|
||||
<vscale x 2 x half> %2,
|
||||
<vscale x 2 x i1> %3,
|
||||
i32 %4)
|
||||
|
||||
ret <vscale x 2 x float> %a
|
||||
}
|
||||
|
||||
declare <vscale x 4 x float> @llvm.riscv.vfwmsac.nxv4f32.nxv4f16(
|
||||
<vscale x 4 x float>,
|
||||
<vscale x 4 x half>,
|
||||
<vscale x 4 x half>,
|
||||
i32);
|
||||
|
||||
define <vscale x 4 x float> @intrinsic_vfwmsac_vv_nxv4f32_nxv4f16_nxv4f16(<vscale x 4 x float> %0, <vscale x 4 x half> %1, <vscale x 4 x half> %2, i32 %3) nounwind {
|
||||
; CHECK-LABEL: intrinsic_vfwmsac_vv_nxv4f32_nxv4f16_nxv4f16:
|
||||
; CHECK: # %bb.0: # %entry
|
||||
; CHECK-NEXT: vsetvli a0, a0, e16,m1,ta,mu
|
||||
; CHECK-NEXT: vfwmsac.vv v16, v18, v19
|
||||
; CHECK-NEXT: jalr zero, 0(ra)
|
||||
entry:
|
||||
%a = call <vscale x 4 x float> @llvm.riscv.vfwmsac.nxv4f32.nxv4f16(
|
||||
<vscale x 4 x float> %0,
|
||||
<vscale x 4 x half> %1,
|
||||
<vscale x 4 x half> %2,
|
||||
i32 %3)
|
||||
|
||||
ret <vscale x 4 x float> %a
|
||||
}
|
||||
|
||||
declare <vscale x 4 x float> @llvm.riscv.vfwmsac.mask.nxv4f32.nxv4f16(
|
||||
<vscale x 4 x float>,
|
||||
<vscale x 4 x half>,
|
||||
<vscale x 4 x half>,
|
||||
<vscale x 4 x i1>,
|
||||
i32);
|
||||
|
||||
define <vscale x 4 x float> @intrinsic_vfwmsac_mask_vv_nxv4f32_nxv4f16_nxv4f16(<vscale x 4 x float> %0, <vscale x 4 x half> %1, <vscale x 4 x half> %2, <vscale x 4 x i1> %3, i32 %4) nounwind {
|
||||
; CHECK-LABEL: intrinsic_vfwmsac_mask_vv_nxv4f32_nxv4f16_nxv4f16:
|
||||
; CHECK: # %bb.0: # %entry
|
||||
; CHECK-NEXT: vsetvli a0, a0, e16,m1,ta,mu
|
||||
; CHECK-NEXT: vfwmsac.vv v16, v18, v19, v0.t
|
||||
; CHECK-NEXT: jalr zero, 0(ra)
|
||||
entry:
|
||||
%a = call <vscale x 4 x float> @llvm.riscv.vfwmsac.mask.nxv4f32.nxv4f16(
|
||||
<vscale x 4 x float> %0,
|
||||
<vscale x 4 x half> %1,
|
||||
<vscale x 4 x half> %2,
|
||||
<vscale x 4 x i1> %3,
|
||||
i32 %4)
|
||||
|
||||
ret <vscale x 4 x float> %a
|
||||
}
|
||||
|
||||
declare <vscale x 8 x float> @llvm.riscv.vfwmsac.nxv8f32.nxv8f16(
|
||||
<vscale x 8 x float>,
|
||||
<vscale x 8 x half>,
|
||||
<vscale x 8 x half>,
|
||||
i32);
|
||||
|
||||
define <vscale x 8 x float> @intrinsic_vfwmsac_vv_nxv8f32_nxv8f16_nxv8f16(<vscale x 8 x float> %0, <vscale x 8 x half> %1, <vscale x 8 x half> %2, i32 %3) nounwind {
|
||||
; CHECK-LABEL: intrinsic_vfwmsac_vv_nxv8f32_nxv8f16_nxv8f16:
|
||||
; CHECK: # %bb.0: # %entry
|
||||
; CHECK-NEXT: vsetvli a0, a0, e16,m2,ta,mu
|
||||
; CHECK-NEXT: vfwmsac.vv v16, v20, v22
|
||||
; CHECK-NEXT: jalr zero, 0(ra)
|
||||
entry:
|
||||
%a = call <vscale x 8 x float> @llvm.riscv.vfwmsac.nxv8f32.nxv8f16(
|
||||
<vscale x 8 x float> %0,
|
||||
<vscale x 8 x half> %1,
|
||||
<vscale x 8 x half> %2,
|
||||
i32 %3)
|
||||
|
||||
ret <vscale x 8 x float> %a
|
||||
}
|
||||
|
||||
declare <vscale x 8 x float> @llvm.riscv.vfwmsac.mask.nxv8f32.nxv8f16(
|
||||
<vscale x 8 x float>,
|
||||
<vscale x 8 x half>,
|
||||
<vscale x 8 x half>,
|
||||
<vscale x 8 x i1>,
|
||||
i32);
|
||||
|
||||
define <vscale x 8 x float> @intrinsic_vfwmsac_mask_vv_nxv8f32_nxv8f16_nxv8f16(<vscale x 8 x float> %0, <vscale x 8 x half> %1, <vscale x 8 x half> %2, <vscale x 8 x i1> %3, i32 %4) nounwind {
|
||||
; CHECK-LABEL: intrinsic_vfwmsac_mask_vv_nxv8f32_nxv8f16_nxv8f16:
|
||||
; CHECK: # %bb.0: # %entry
|
||||
; CHECK-NEXT: vsetvli a0, a0, e16,m2,ta,mu
|
||||
; CHECK-NEXT: vfwmsac.vv v16, v20, v22, v0.t
|
||||
; CHECK-NEXT: jalr zero, 0(ra)
|
||||
entry:
|
||||
%a = call <vscale x 8 x float> @llvm.riscv.vfwmsac.mask.nxv8f32.nxv8f16(
|
||||
<vscale x 8 x float> %0,
|
||||
<vscale x 8 x half> %1,
|
||||
<vscale x 8 x half> %2,
|
||||
<vscale x 8 x i1> %3,
|
||||
i32 %4)
|
||||
|
||||
ret <vscale x 8 x float> %a
|
||||
}
|
||||
|
||||
declare <vscale x 16 x float> @llvm.riscv.vfwmsac.nxv16f32.nxv16f16(
|
||||
<vscale x 16 x float>,
|
||||
<vscale x 16 x half>,
|
||||
<vscale x 16 x half>,
|
||||
i32);
|
||||
|
||||
define <vscale x 16 x float> @intrinsic_vfwmsac_vv_nxv16f32_nxv16f16_nxv16f16(<vscale x 16 x float> %0, <vscale x 16 x half> %1, <vscale x 16 x half> %2, i32 %3) nounwind {
|
||||
; CHECK-LABEL: intrinsic_vfwmsac_vv_nxv16f32_nxv16f16_nxv16f16:
|
||||
; CHECK: # %bb.0: # %entry
|
||||
; CHECK-NEXT: vsetvli a3, zero, e16,m4,ta,mu
|
||||
; CHECK-NEXT: vle16.v v28, (a1)
|
||||
; CHECK-NEXT: vle16.v v8, (a0)
|
||||
; CHECK-NEXT: vsetvli a0, a2, e16,m4,ta,mu
|
||||
; CHECK-NEXT: vfwmsac.vv v16, v8, v28
|
||||
; CHECK-NEXT: jalr zero, 0(ra)
|
||||
entry:
|
||||
%a = call <vscale x 16 x float> @llvm.riscv.vfwmsac.nxv16f32.nxv16f16(
|
||||
<vscale x 16 x float> %0,
|
||||
<vscale x 16 x half> %1,
|
||||
<vscale x 16 x half> %2,
|
||||
i32 %3)
|
||||
|
||||
ret <vscale x 16 x float> %a
|
||||
}
|
||||
|
||||
declare <vscale x 16 x float> @llvm.riscv.vfwmsac.mask.nxv16f32.nxv16f16(
|
||||
<vscale x 16 x float>,
|
||||
<vscale x 16 x half>,
|
||||
<vscale x 16 x half>,
|
||||
<vscale x 16 x i1>,
|
||||
i32);
|
||||
|
||||
define <vscale x 16 x float> @intrinsic_vfwmsac_mask_vv_nxv16f32_nxv16f16_nxv16f16(<vscale x 16 x float> %0, <vscale x 16 x half> %1, <vscale x 16 x half> %2, <vscale x 16 x i1> %3, i32 %4) nounwind {
|
||||
; CHECK-LABEL: intrinsic_vfwmsac_mask_vv_nxv16f32_nxv16f16_nxv16f16:
|
||||
; CHECK: # %bb.0: # %entry
|
||||
; CHECK-NEXT: vsetvli a3, zero, e16,m4,ta,mu
|
||||
; CHECK-NEXT: vle16.v v28, (a1)
|
||||
; CHECK-NEXT: vle16.v v8, (a0)
|
||||
; CHECK-NEXT: vsetvli a0, a2, e16,m4,ta,mu
|
||||
; CHECK-NEXT: vfwmsac.vv v16, v8, v28, v0.t
|
||||
; CHECK-NEXT: jalr zero, 0(ra)
|
||||
entry:
|
||||
%a = call <vscale x 16 x float> @llvm.riscv.vfwmsac.mask.nxv16f32.nxv16f16(
|
||||
<vscale x 16 x float> %0,
|
||||
<vscale x 16 x half> %1,
|
||||
<vscale x 16 x half> %2,
|
||||
<vscale x 16 x i1> %3,
|
||||
i32 %4)
|
||||
|
||||
ret <vscale x 16 x float> %a
|
||||
}
|
||||
|
||||
declare <vscale x 1 x float> @llvm.riscv.vfwmsac.nxv1f32.f16(
|
||||
<vscale x 1 x float>,
|
||||
half,
|
||||
<vscale x 1 x half>,
|
||||
i32);
|
||||
|
||||
define <vscale x 1 x float> @intrinsic_vfwmsac_vf_nxv1f32_f16_nxv1f16(<vscale x 1 x float> %0, half %1, <vscale x 1 x half> %2, i32 %3) nounwind {
|
||||
; CHECK-LABEL: intrinsic_vfwmsac_vf_nxv1f32_f16_nxv1f16:
|
||||
; CHECK: # %bb.0: # %entry
|
||||
; CHECK-NEXT: fmv.h.x ft0, a0
|
||||
; CHECK-NEXT: vsetvli a0, a1, e16,mf4,ta,mu
|
||||
; CHECK-NEXT: vfwmsac.vf v16, ft0, v17
|
||||
; CHECK-NEXT: jalr zero, 0(ra)
|
||||
entry:
|
||||
%a = call <vscale x 1 x float> @llvm.riscv.vfwmsac.nxv1f32.f16(
|
||||
<vscale x 1 x float> %0,
|
||||
half %1,
|
||||
<vscale x 1 x half> %2,
|
||||
i32 %3)
|
||||
|
||||
ret <vscale x 1 x float> %a
|
||||
}
|
||||
|
||||
declare <vscale x 1 x float> @llvm.riscv.vfwmsac.mask.nxv1f32.f16(
|
||||
<vscale x 1 x float>,
|
||||
half,
|
||||
<vscale x 1 x half>,
|
||||
<vscale x 1 x i1>,
|
||||
i32);
|
||||
|
||||
define <vscale x 1 x float> @intrinsic_vfwmsac_mask_vf_nxv1f32_f16_nxv1f16(<vscale x 1 x float> %0, half %1, <vscale x 1 x half> %2, <vscale x 1 x i1> %3, i32 %4) nounwind {
|
||||
; CHECK-LABEL: intrinsic_vfwmsac_mask_vf_nxv1f32_f16_nxv1f16:
|
||||
; CHECK: # %bb.0: # %entry
|
||||
; CHECK-NEXT: fmv.h.x ft0, a0
|
||||
; CHECK-NEXT: vsetvli a0, a1, e16,mf4,ta,mu
|
||||
; CHECK-NEXT: vfwmsac.vf v16, ft0, v17, v0.t
|
||||
; CHECK-NEXT: jalr zero, 0(ra)
|
||||
entry:
|
||||
%a = call <vscale x 1 x float> @llvm.riscv.vfwmsac.mask.nxv1f32.f16(
|
||||
<vscale x 1 x float> %0,
|
||||
half %1,
|
||||
<vscale x 1 x half> %2,
|
||||
<vscale x 1 x i1> %3,
|
||||
i32 %4)
|
||||
|
||||
ret <vscale x 1 x float> %a
|
||||
}
|
||||
|
||||
declare <vscale x 2 x float> @llvm.riscv.vfwmsac.nxv2f32.f16(
|
||||
<vscale x 2 x float>,
|
||||
half,
|
||||
<vscale x 2 x half>,
|
||||
i32);
|
||||
|
||||
define <vscale x 2 x float> @intrinsic_vfwmsac_vf_nxv2f32_f16_nxv2f16(<vscale x 2 x float> %0, half %1, <vscale x 2 x half> %2, i32 %3) nounwind {
|
||||
; CHECK-LABEL: intrinsic_vfwmsac_vf_nxv2f32_f16_nxv2f16:
|
||||
; CHECK: # %bb.0: # %entry
|
||||
; CHECK-NEXT: fmv.h.x ft0, a0
|
||||
; CHECK-NEXT: vsetvli a0, a1, e16,mf2,ta,mu
|
||||
; CHECK-NEXT: vfwmsac.vf v16, ft0, v17
|
||||
; CHECK-NEXT: jalr zero, 0(ra)
|
||||
entry:
|
||||
%a = call <vscale x 2 x float> @llvm.riscv.vfwmsac.nxv2f32.f16(
|
||||
<vscale x 2 x float> %0,
|
||||
half %1,
|
||||
<vscale x 2 x half> %2,
|
||||
i32 %3)
|
||||
|
||||
ret <vscale x 2 x float> %a
|
||||
}
|
||||
|
||||
declare <vscale x 2 x float> @llvm.riscv.vfwmsac.mask.nxv2f32.f16(
|
||||
<vscale x 2 x float>,
|
||||
half,
|
||||
<vscale x 2 x half>,
|
||||
<vscale x 2 x i1>,
|
||||
i32);
|
||||
|
||||
define <vscale x 2 x float> @intrinsic_vfwmsac_mask_vf_nxv2f32_f16_nxv2f16(<vscale x 2 x float> %0, half %1, <vscale x 2 x half> %2, <vscale x 2 x i1> %3, i32 %4) nounwind {
|
||||
; CHECK-LABEL: intrinsic_vfwmsac_mask_vf_nxv2f32_f16_nxv2f16:
|
||||
; CHECK: # %bb.0: # %entry
|
||||
; CHECK-NEXT: fmv.h.x ft0, a0
|
||||
; CHECK-NEXT: vsetvli a0, a1, e16,mf2,ta,mu
|
||||
; CHECK-NEXT: vfwmsac.vf v16, ft0, v17, v0.t
|
||||
; CHECK-NEXT: jalr zero, 0(ra)
|
||||
entry:
|
||||
%a = call <vscale x 2 x float> @llvm.riscv.vfwmsac.mask.nxv2f32.f16(
|
||||
<vscale x 2 x float> %0,
|
||||
half %1,
|
||||
<vscale x 2 x half> %2,
|
||||
<vscale x 2 x i1> %3,
|
||||
i32 %4)
|
||||
|
||||
ret <vscale x 2 x float> %a
|
||||
}
|
||||
|
||||
declare <vscale x 4 x float> @llvm.riscv.vfwmsac.nxv4f32.f16(
|
||||
<vscale x 4 x float>,
|
||||
half,
|
||||
<vscale x 4 x half>,
|
||||
i32);
|
||||
|
||||
define <vscale x 4 x float> @intrinsic_vfwmsac_vf_nxv4f32_f16_nxv4f16(<vscale x 4 x float> %0, half %1, <vscale x 4 x half> %2, i32 %3) nounwind {
|
||||
; CHECK-LABEL: intrinsic_vfwmsac_vf_nxv4f32_f16_nxv4f16:
|
||||
; CHECK: # %bb.0: # %entry
|
||||
; CHECK-NEXT: fmv.h.x ft0, a0
|
||||
; CHECK-NEXT: vsetvli a0, a1, e16,m1,ta,mu
|
||||
; CHECK-NEXT: vfwmsac.vf v16, ft0, v18
|
||||
; CHECK-NEXT: jalr zero, 0(ra)
|
||||
entry:
|
||||
%a = call <vscale x 4 x float> @llvm.riscv.vfwmsac.nxv4f32.f16(
|
||||
<vscale x 4 x float> %0,
|
||||
half %1,
|
||||
<vscale x 4 x half> %2,
|
||||
i32 %3)
|
||||
|
||||
ret <vscale x 4 x float> %a
|
||||
}
|
||||
|
||||
declare <vscale x 4 x float> @llvm.riscv.vfwmsac.mask.nxv4f32.f16(
|
||||
<vscale x 4 x float>,
|
||||
half,
|
||||
<vscale x 4 x half>,
|
||||
<vscale x 4 x i1>,
|
||||
i32);
|
||||
|
||||
define <vscale x 4 x float> @intrinsic_vfwmsac_mask_vf_nxv4f32_f16_nxv4f16(<vscale x 4 x float> %0, half %1, <vscale x 4 x half> %2, <vscale x 4 x i1> %3, i32 %4) nounwind {
|
||||
; CHECK-LABEL: intrinsic_vfwmsac_mask_vf_nxv4f32_f16_nxv4f16:
|
||||
; CHECK: # %bb.0: # %entry
|
||||
; CHECK-NEXT: fmv.h.x ft0, a0
|
||||
; CHECK-NEXT: vsetvli a0, a1, e16,m1,ta,mu
|
||||
; CHECK-NEXT: vfwmsac.vf v16, ft0, v18, v0.t
|
||||
; CHECK-NEXT: jalr zero, 0(ra)
|
||||
entry:
|
||||
%a = call <vscale x 4 x float> @llvm.riscv.vfwmsac.mask.nxv4f32.f16(
|
||||
<vscale x 4 x float> %0,
|
||||
half %1,
|
||||
<vscale x 4 x half> %2,
|
||||
<vscale x 4 x i1> %3,
|
||||
i32 %4)
|
||||
|
||||
ret <vscale x 4 x float> %a
|
||||
}
|
||||
|
||||
declare <vscale x 8 x float> @llvm.riscv.vfwmsac.nxv8f32.f16(
|
||||
<vscale x 8 x float>,
|
||||
half,
|
||||
<vscale x 8 x half>,
|
||||
i32);
|
||||
|
||||
define <vscale x 8 x float> @intrinsic_vfwmsac_vf_nxv8f32_f16_nxv8f16(<vscale x 8 x float> %0, half %1, <vscale x 8 x half> %2, i32 %3) nounwind {
|
||||
; CHECK-LABEL: intrinsic_vfwmsac_vf_nxv8f32_f16_nxv8f16:
|
||||
; CHECK: # %bb.0: # %entry
|
||||
; CHECK-NEXT: fmv.h.x ft0, a0
|
||||
; CHECK-NEXT: vsetvli a0, a1, e16,m2,ta,mu
|
||||
; CHECK-NEXT: vfwmsac.vf v16, ft0, v20
|
||||
; CHECK-NEXT: jalr zero, 0(ra)
|
||||
entry:
|
||||
%a = call <vscale x 8 x float> @llvm.riscv.vfwmsac.nxv8f32.f16(
|
||||
<vscale x 8 x float> %0,
|
||||
half %1,
|
||||
<vscale x 8 x half> %2,
|
||||
i32 %3)
|
||||
|
||||
ret <vscale x 8 x float> %a
|
||||
}
|
||||
|
||||
declare <vscale x 8 x float> @llvm.riscv.vfwmsac.mask.nxv8f32.f16(
|
||||
<vscale x 8 x float>,
|
||||
half,
|
||||
<vscale x 8 x half>,
|
||||
<vscale x 8 x i1>,
|
||||
i32);
|
||||
|
||||
define <vscale x 8 x float> @intrinsic_vfwmsac_mask_vf_nxv8f32_f16_nxv8f16(<vscale x 8 x float> %0, half %1, <vscale x 8 x half> %2, <vscale x 8 x i1> %3, i32 %4) nounwind {
|
||||
; CHECK-LABEL: intrinsic_vfwmsac_mask_vf_nxv8f32_f16_nxv8f16:
|
||||
; CHECK: # %bb.0: # %entry
|
||||
; CHECK-NEXT: fmv.h.x ft0, a0
|
||||
; CHECK-NEXT: vsetvli a0, a1, e16,m2,ta,mu
|
||||
; CHECK-NEXT: vfwmsac.vf v16, ft0, v20, v0.t
|
||||
; CHECK-NEXT: jalr zero, 0(ra)
|
||||
entry:
|
||||
%a = call <vscale x 8 x float> @llvm.riscv.vfwmsac.mask.nxv8f32.f16(
|
||||
<vscale x 8 x float> %0,
|
||||
half %1,
|
||||
<vscale x 8 x half> %2,
|
||||
<vscale x 8 x i1> %3,
|
||||
i32 %4)
|
||||
|
||||
ret <vscale x 8 x float> %a
|
||||
}
|
||||
|
||||
declare <vscale x 16 x float> @llvm.riscv.vfwmsac.nxv16f32.f16(
|
||||
<vscale x 16 x float>,
|
||||
half,
|
||||
<vscale x 16 x half>,
|
||||
i32);
|
||||
|
||||
define <vscale x 16 x float> @intrinsic_vfwmsac_vf_nxv16f32_f16_nxv16f16(<vscale x 16 x float> %0, half %1, <vscale x 16 x half> %2, i32 %3) nounwind {
|
||||
; CHECK-LABEL: intrinsic_vfwmsac_vf_nxv16f32_f16_nxv16f16:
|
||||
; CHECK: # %bb.0: # %entry
|
||||
; CHECK-NEXT: vsetvli a3, zero, e16,m4,ta,mu
|
||||
; CHECK-NEXT: vle16.v v28, (a1)
|
||||
; CHECK-NEXT: fmv.h.x ft0, a0
|
||||
; CHECK-NEXT: vsetvli a0, a2, e16,m4,ta,mu
|
||||
; CHECK-NEXT: vfwmsac.vf v16, ft0, v28
|
||||
; CHECK-NEXT: jalr zero, 0(ra)
|
||||
entry:
|
||||
%a = call <vscale x 16 x float> @llvm.riscv.vfwmsac.nxv16f32.f16(
|
||||
<vscale x 16 x float> %0,
|
||||
half %1,
|
||||
<vscale x 16 x half> %2,
|
||||
i32 %3)
|
||||
|
||||
ret <vscale x 16 x float> %a
|
||||
}
|
||||
|
||||
declare <vscale x 16 x float> @llvm.riscv.vfwmsac.mask.nxv16f32.f16(
|
||||
<vscale x 16 x float>,
|
||||
half,
|
||||
<vscale x 16 x half>,
|
||||
<vscale x 16 x i1>,
|
||||
i32);
|
||||
|
||||
define <vscale x 16 x float> @intrinsic_vfwmsac_mask_vf_nxv16f32_f16_nxv16f16(<vscale x 16 x float> %0, half %1, <vscale x 16 x half> %2, <vscale x 16 x i1> %3, i32 %4) nounwind {
|
||||
; CHECK-LABEL: intrinsic_vfwmsac_mask_vf_nxv16f32_f16_nxv16f16:
|
||||
; CHECK: # %bb.0: # %entry
|
||||
; CHECK-NEXT: vsetvli a3, zero, e16,m4,ta,mu
|
||||
; CHECK-NEXT: vle16.v v28, (a1)
|
||||
; CHECK-NEXT: fmv.h.x ft0, a0
|
||||
; CHECK-NEXT: vsetvli a0, a2, e16,m4,ta,mu
|
||||
; CHECK-NEXT: vfwmsac.vf v16, ft0, v28, v0.t
|
||||
; CHECK-NEXT: jalr zero, 0(ra)
|
||||
entry:
|
||||
%a = call <vscale x 16 x float> @llvm.riscv.vfwmsac.mask.nxv16f32.f16(
|
||||
<vscale x 16 x float> %0,
|
||||
half %1,
|
||||
<vscale x 16 x half> %2,
|
||||
<vscale x 16 x i1> %3,
|
||||
i32 %4)
|
||||
|
||||
ret <vscale x 16 x float> %a
|
||||
}
|
||||
868
test/CodeGen/RISCV/rvv/vfwmsac-rv64.ll
Normal file
868
test/CodeGen/RISCV/rvv/vfwmsac-rv64.ll
Normal file
@ -0,0 +1,868 @@
|
||||
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
|
||||
; RUN: llc -mtriple=riscv64 -mattr=+experimental-v,+d,+experimental-zfh -verify-machineinstrs \
|
||||
; RUN: --riscv-no-aliases < %s | FileCheck %s
|
||||
declare <vscale x 1 x float> @llvm.riscv.vfwmsac.nxv1f32.nxv1f16(
|
||||
<vscale x 1 x float>,
|
||||
<vscale x 1 x half>,
|
||||
<vscale x 1 x half>,
|
||||
i64);
|
||||
|
||||
define <vscale x 1 x float> @intrinsic_vfwmsac_vv_nxv1f32_nxv1f16_nxv1f16(<vscale x 1 x float> %0, <vscale x 1 x half> %1, <vscale x 1 x half> %2, i64 %3) nounwind {
|
||||
; CHECK-LABEL: intrinsic_vfwmsac_vv_nxv1f32_nxv1f16_nxv1f16:
|
||||
; CHECK: # %bb.0: # %entry
|
||||
; CHECK-NEXT: vsetvli a0, a0, e16,mf4,ta,mu
|
||||
; CHECK-NEXT: vfwmsac.vv v16, v17, v18
|
||||
; CHECK-NEXT: jalr zero, 0(ra)
|
||||
entry:
|
||||
%a = call <vscale x 1 x float> @llvm.riscv.vfwmsac.nxv1f32.nxv1f16(
|
||||
<vscale x 1 x float> %0,
|
||||
<vscale x 1 x half> %1,
|
||||
<vscale x 1 x half> %2,
|
||||
i64 %3)
|
||||
|
||||
ret <vscale x 1 x float> %a
|
||||
}
|
||||
|
||||
declare <vscale x 1 x float> @llvm.riscv.vfwmsac.mask.nxv1f32.nxv1f16(
|
||||
<vscale x 1 x float>,
|
||||
<vscale x 1 x half>,
|
||||
<vscale x 1 x half>,
|
||||
<vscale x 1 x i1>,
|
||||
i64);
|
||||
|
||||
define <vscale x 1 x float> @intrinsic_vfwmsac_mask_vv_nxv1f32_nxv1f16_nxv1f16(<vscale x 1 x float> %0, <vscale x 1 x half> %1, <vscale x 1 x half> %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
|
||||
; CHECK-LABEL: intrinsic_vfwmsac_mask_vv_nxv1f32_nxv1f16_nxv1f16:
|
||||
; CHECK: # %bb.0: # %entry
|
||||
; CHECK-NEXT: vsetvli a0, a0, e16,mf4,ta,mu
|
||||
; CHECK-NEXT: vfwmsac.vv v16, v17, v18, v0.t
|
||||
; CHECK-NEXT: jalr zero, 0(ra)
|
||||
entry:
|
||||
%a = call <vscale x 1 x float> @llvm.riscv.vfwmsac.mask.nxv1f32.nxv1f16(
|
||||
<vscale x 1 x float> %0,
|
||||
<vscale x 1 x half> %1,
|
||||
<vscale x 1 x half> %2,
|
||||
<vscale x 1 x i1> %3,
|
||||
i64 %4)
|
||||
|
||||
ret <vscale x 1 x float> %a
|
||||
}
|
||||
|
||||
declare <vscale x 2 x float> @llvm.riscv.vfwmsac.nxv2f32.nxv2f16(
|
||||
<vscale x 2 x float>,
|
||||
<vscale x 2 x half>,
|
||||
<vscale x 2 x half>,
|
||||
i64);
|
||||
|
||||
define <vscale x 2 x float> @intrinsic_vfwmsac_vv_nxv2f32_nxv2f16_nxv2f16(<vscale x 2 x float> %0, <vscale x 2 x half> %1, <vscale x 2 x half> %2, i64 %3) nounwind {
|
||||
; CHECK-LABEL: intrinsic_vfwmsac_vv_nxv2f32_nxv2f16_nxv2f16:
|
||||
; CHECK: # %bb.0: # %entry
|
||||
; CHECK-NEXT: vsetvli a0, a0, e16,mf2,ta,mu
|
||||
; CHECK-NEXT: vfwmsac.vv v16, v17, v18
|
||||
; CHECK-NEXT: jalr zero, 0(ra)
|
||||
entry:
|
||||
%a = call <vscale x 2 x float> @llvm.riscv.vfwmsac.nxv2f32.nxv2f16(
|
||||
<vscale x 2 x float> %0,
|
||||
<vscale x 2 x half> %1,
|
||||
<vscale x 2 x half> %2,
|
||||
i64 %3)
|
||||
|
||||
ret <vscale x 2 x float> %a
|
||||
}
|
||||
|
||||
declare <vscale x 2 x float> @llvm.riscv.vfwmsac.mask.nxv2f32.nxv2f16(
|
||||
<vscale x 2 x float>,
|
||||
<vscale x 2 x half>,
|
||||
<vscale x 2 x half>,
|
||||
<vscale x 2 x i1>,
|
||||
i64);
|
||||
|
||||
define <vscale x 2 x float> @intrinsic_vfwmsac_mask_vv_nxv2f32_nxv2f16_nxv2f16(<vscale x 2 x float> %0, <vscale x 2 x half> %1, <vscale x 2 x half> %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
|
||||
; CHECK-LABEL: intrinsic_vfwmsac_mask_vv_nxv2f32_nxv2f16_nxv2f16:
|
||||
; CHECK: # %bb.0: # %entry
|
||||
; CHECK-NEXT: vsetvli a0, a0, e16,mf2,ta,mu
|
||||
; CHECK-NEXT: vfwmsac.vv v16, v17, v18, v0.t
|
||||
; CHECK-NEXT: jalr zero, 0(ra)
|
||||
entry:
|
||||
%a = call <vscale x 2 x float> @llvm.riscv.vfwmsac.mask.nxv2f32.nxv2f16(
|
||||
<vscale x 2 x float> %0,
|
||||
<vscale x 2 x half> %1,
|
||||
<vscale x 2 x half> %2,
|
||||
<vscale x 2 x i1> %3,
|
||||
i64 %4)
|
||||
|
||||
ret <vscale x 2 x float> %a
|
||||
}
|
||||
|
||||
declare <vscale x 4 x float> @llvm.riscv.vfwmsac.nxv4f32.nxv4f16(
|
||||
<vscale x 4 x float>,
|
||||
<vscale x 4 x half>,
|
||||
<vscale x 4 x half>,
|
||||
i64);
|
||||
|
||||
define <vscale x 4 x float> @intrinsic_vfwmsac_vv_nxv4f32_nxv4f16_nxv4f16(<vscale x 4 x float> %0, <vscale x 4 x half> %1, <vscale x 4 x half> %2, i64 %3) nounwind {
|
||||
; CHECK-LABEL: intrinsic_vfwmsac_vv_nxv4f32_nxv4f16_nxv4f16:
|
||||
; CHECK: # %bb.0: # %entry
|
||||
; CHECK-NEXT: vsetvli a0, a0, e16,m1,ta,mu
|
||||
; CHECK-NEXT: vfwmsac.vv v16, v18, v19
|
||||
; CHECK-NEXT: jalr zero, 0(ra)
|
||||
entry:
|
||||
%a = call <vscale x 4 x float> @llvm.riscv.vfwmsac.nxv4f32.nxv4f16(
|
||||
<vscale x 4 x float> %0,
|
||||
<vscale x 4 x half> %1,
|
||||
<vscale x 4 x half> %2,
|
||||
i64 %3)
|
||||
|
||||
ret <vscale x 4 x float> %a
|
||||
}
|
||||
|
||||
declare <vscale x 4 x float> @llvm.riscv.vfwmsac.mask.nxv4f32.nxv4f16(
|
||||
<vscale x 4 x float>,
|
||||
<vscale x 4 x half>,
|
||||
<vscale x 4 x half>,
|
||||
<vscale x 4 x i1>,
|
||||
i64);
|
||||
|
||||
define <vscale x 4 x float> @intrinsic_vfwmsac_mask_vv_nxv4f32_nxv4f16_nxv4f16(<vscale x 4 x float> %0, <vscale x 4 x half> %1, <vscale x 4 x half> %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
|
||||
; CHECK-LABEL: intrinsic_vfwmsac_mask_vv_nxv4f32_nxv4f16_nxv4f16:
|
||||
; CHECK: # %bb.0: # %entry
|
||||
; CHECK-NEXT: vsetvli a0, a0, e16,m1,ta,mu
|
||||
; CHECK-NEXT: vfwmsac.vv v16, v18, v19, v0.t
|
||||
; CHECK-NEXT: jalr zero, 0(ra)
|
||||
entry:
|
||||
%a = call <vscale x 4 x float> @llvm.riscv.vfwmsac.mask.nxv4f32.nxv4f16(
|
||||
<vscale x 4 x float> %0,
|
||||
<vscale x 4 x half> %1,
|
||||
<vscale x 4 x half> %2,
|
||||
<vscale x 4 x i1> %3,
|
||||
i64 %4)
|
||||
|
||||
ret <vscale x 4 x float> %a
|
||||
}
|
||||
|
||||
declare <vscale x 8 x float> @llvm.riscv.vfwmsac.nxv8f32.nxv8f16(
|
||||
<vscale x 8 x float>,
|
||||
<vscale x 8 x half>,
|
||||
<vscale x 8 x half>,
|
||||
i64);
|
||||
|
||||
define <vscale x 8 x float> @intrinsic_vfwmsac_vv_nxv8f32_nxv8f16_nxv8f16(<vscale x 8 x float> %0, <vscale x 8 x half> %1, <vscale x 8 x half> %2, i64 %3) nounwind {
|
||||
; CHECK-LABEL: intrinsic_vfwmsac_vv_nxv8f32_nxv8f16_nxv8f16:
|
||||
; CHECK: # %bb.0: # %entry
|
||||
; CHECK-NEXT: vsetvli a0, a0, e16,m2,ta,mu
|
||||
; CHECK-NEXT: vfwmsac.vv v16, v20, v22
|
||||
; CHECK-NEXT: jalr zero, 0(ra)
|
||||
entry:
|
||||
%a = call <vscale x 8 x float> @llvm.riscv.vfwmsac.nxv8f32.nxv8f16(
|
||||
<vscale x 8 x float> %0,
|
||||
<vscale x 8 x half> %1,
|
||||
<vscale x 8 x half> %2,
|
||||
i64 %3)
|
||||
|
||||
ret <vscale x 8 x float> %a
|
||||
}
|
||||
|
||||
declare <vscale x 8 x float> @llvm.riscv.vfwmsac.mask.nxv8f32.nxv8f16(
|
||||
<vscale x 8 x float>,
|
||||
<vscale x 8 x half>,
|
||||
<vscale x 8 x half>,
|
||||
<vscale x 8 x i1>,
|
||||
i64);
|
||||
|
||||
define <vscale x 8 x float> @intrinsic_vfwmsac_mask_vv_nxv8f32_nxv8f16_nxv8f16(<vscale x 8 x float> %0, <vscale x 8 x half> %1, <vscale x 8 x half> %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
|
||||
; CHECK-LABEL: intrinsic_vfwmsac_mask_vv_nxv8f32_nxv8f16_nxv8f16:
|
||||
; CHECK: # %bb.0: # %entry
|
||||
; CHECK-NEXT: vsetvli a0, a0, e16,m2,ta,mu
|
||||
; CHECK-NEXT: vfwmsac.vv v16, v20, v22, v0.t
|
||||
; CHECK-NEXT: jalr zero, 0(ra)
|
||||
entry:
|
||||
%a = call <vscale x 8 x float> @llvm.riscv.vfwmsac.mask.nxv8f32.nxv8f16(
|
||||
<vscale x 8 x float> %0,
|
||||
<vscale x 8 x half> %1,
|
||||
<vscale x 8 x half> %2,
|
||||
<vscale x 8 x i1> %3,
|
||||
i64 %4)
|
||||
|
||||
ret <vscale x 8 x float> %a
|
||||
}
|
||||
|
||||
declare <vscale x 16 x float> @llvm.riscv.vfwmsac.nxv16f32.nxv16f16(
|
||||
<vscale x 16 x float>,
|
||||
<vscale x 16 x half>,
|
||||
<vscale x 16 x half>,
|
||||
i64);
|
||||
|
||||
define <vscale x 16 x float> @intrinsic_vfwmsac_vv_nxv16f32_nxv16f16_nxv16f16(<vscale x 16 x float> %0, <vscale x 16 x half> %1, <vscale x 16 x half> %2, i64 %3) nounwind {
|
||||
; CHECK-LABEL: intrinsic_vfwmsac_vv_nxv16f32_nxv16f16_nxv16f16:
|
||||
; CHECK: # %bb.0: # %entry
|
||||
; CHECK-NEXT: vsetvli a3, zero, e16,m4,ta,mu
|
||||
; CHECK-NEXT: vle16.v v28, (a1)
|
||||
; CHECK-NEXT: vle16.v v8, (a0)
|
||||
; CHECK-NEXT: vsetvli a0, a2, e16,m4,ta,mu
|
||||
; CHECK-NEXT: vfwmsac.vv v16, v8, v28
|
||||
; CHECK-NEXT: jalr zero, 0(ra)
|
||||
entry:
|
||||
%a = call <vscale x 16 x float> @llvm.riscv.vfwmsac.nxv16f32.nxv16f16(
|
||||
<vscale x 16 x float> %0,
|
||||
<vscale x 16 x half> %1,
|
||||
<vscale x 16 x half> %2,
|
||||
i64 %3)
|
||||
|
||||
ret <vscale x 16 x float> %a
|
||||
}
|
||||
|
||||
declare <vscale x 16 x float> @llvm.riscv.vfwmsac.mask.nxv16f32.nxv16f16(
|
||||
<vscale x 16 x float>,
|
||||
<vscale x 16 x half>,
|
||||
<vscale x 16 x half>,
|
||||
<vscale x 16 x i1>,
|
||||
i64);
|
||||
|
||||
define <vscale x 16 x float> @intrinsic_vfwmsac_mask_vv_nxv16f32_nxv16f16_nxv16f16(<vscale x 16 x float> %0, <vscale x 16 x half> %1, <vscale x 16 x half> %2, <vscale x 16 x i1> %3, i64 %4) nounwind {
|
||||
; CHECK-LABEL: intrinsic_vfwmsac_mask_vv_nxv16f32_nxv16f16_nxv16f16:
|
||||
; CHECK: # %bb.0: # %entry
|
||||
; CHECK-NEXT: vsetvli a3, zero, e16,m4,ta,mu
|
||||
; CHECK-NEXT: vle16.v v28, (a1)
|
||||
; CHECK-NEXT: vle16.v v8, (a0)
|
||||
; CHECK-NEXT: vsetvli a0, a2, e16,m4,ta,mu
|
||||
; CHECK-NEXT: vfwmsac.vv v16, v8, v28, v0.t
|
||||
; CHECK-NEXT: jalr zero, 0(ra)
|
||||
entry:
|
||||
%a = call <vscale x 16 x float> @llvm.riscv.vfwmsac.mask.nxv16f32.nxv16f16(
|
||||
<vscale x 16 x float> %0,
|
||||
<vscale x 16 x half> %1,
|
||||
<vscale x 16 x half> %2,
|
||||
<vscale x 16 x i1> %3,
|
||||
i64 %4)
|
||||
|
||||
ret <vscale x 16 x float> %a
|
||||
}
|
||||
|
||||
declare <vscale x 1 x double> @llvm.riscv.vfwmsac.nxv1f64.nxv1f32(
|
||||
<vscale x 1 x double>,
|
||||
<vscale x 1 x float>,
|
||||
<vscale x 1 x float>,
|
||||
i64);
|
||||
|
||||
define <vscale x 1 x double> @intrinsic_vfwmsac_vv_nxv1f64_nxv1f32_nxv1f32(<vscale x 1 x double> %0, <vscale x 1 x float> %1, <vscale x 1 x float> %2, i64 %3) nounwind {
|
||||
; CHECK-LABEL: intrinsic_vfwmsac_vv_nxv1f64_nxv1f32_nxv1f32:
|
||||
; CHECK: # %bb.0: # %entry
|
||||
; CHECK-NEXT: vsetvli a0, a0, e32,mf2,ta,mu
|
||||
; CHECK-NEXT: vfwmsac.vv v16, v17, v18
|
||||
; CHECK-NEXT: jalr zero, 0(ra)
|
||||
entry:
|
||||
%a = call <vscale x 1 x double> @llvm.riscv.vfwmsac.nxv1f64.nxv1f32(
|
||||
<vscale x 1 x double> %0,
|
||||
<vscale x 1 x float> %1,
|
||||
<vscale x 1 x float> %2,
|
||||
i64 %3)
|
||||
|
||||
ret <vscale x 1 x double> %a
|
||||
}
|
||||
|
||||
declare <vscale x 1 x double> @llvm.riscv.vfwmsac.mask.nxv1f64.nxv1f32(
|
||||
<vscale x 1 x double>,
|
||||
<vscale x 1 x float>,
|
||||
<vscale x 1 x float>,
|
||||
<vscale x 1 x i1>,
|
||||
i64);
|
||||
|
||||
define <vscale x 1 x double> @intrinsic_vfwmsac_mask_vv_nxv1f64_nxv1f32_nxv1f32(<vscale x 1 x double> %0, <vscale x 1 x float> %1, <vscale x 1 x float> %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
|
||||
; CHECK-LABEL: intrinsic_vfwmsac_mask_vv_nxv1f64_nxv1f32_nxv1f32:
|
||||
; CHECK: # %bb.0: # %entry
|
||||
; CHECK-NEXT: vsetvli a0, a0, e32,mf2,ta,mu
|
||||
; CHECK-NEXT: vfwmsac.vv v16, v17, v18, v0.t
|
||||
; CHECK-NEXT: jalr zero, 0(ra)
|
||||
entry:
|
||||
%a = call <vscale x 1 x double> @llvm.riscv.vfwmsac.mask.nxv1f64.nxv1f32(
|
||||
<vscale x 1 x double> %0,
|
||||
<vscale x 1 x float> %1,
|
||||
<vscale x 1 x float> %2,
|
||||
<vscale x 1 x i1> %3,
|
||||
i64 %4)
|
||||
|
||||
ret <vscale x 1 x double> %a
|
||||
}
|
||||
|
||||
declare <vscale x 2 x double> @llvm.riscv.vfwmsac.nxv2f64.nxv2f32(
|
||||
<vscale x 2 x double>,
|
||||
<vscale x 2 x float>,
|
||||
<vscale x 2 x float>,
|
||||
i64);
|
||||
|
||||
define <vscale x 2 x double> @intrinsic_vfwmsac_vv_nxv2f64_nxv2f32_nxv2f32(<vscale x 2 x double> %0, <vscale x 2 x float> %1, <vscale x 2 x float> %2, i64 %3) nounwind {
|
||||
; CHECK-LABEL: intrinsic_vfwmsac_vv_nxv2f64_nxv2f32_nxv2f32:
|
||||
; CHECK: # %bb.0: # %entry
|
||||
; CHECK-NEXT: vsetvli a0, a0, e32,m1,ta,mu
|
||||
; CHECK-NEXT: vfwmsac.vv v16, v18, v19
|
||||
; CHECK-NEXT: jalr zero, 0(ra)
|
||||
entry:
|
||||
%a = call <vscale x 2 x double> @llvm.riscv.vfwmsac.nxv2f64.nxv2f32(
|
||||
<vscale x 2 x double> %0,
|
||||
<vscale x 2 x float> %1,
|
||||
<vscale x 2 x float> %2,
|
||||
i64 %3)
|
||||
|
||||
ret <vscale x 2 x double> %a
|
||||
}
|
||||
|
||||
declare <vscale x 2 x double> @llvm.riscv.vfwmsac.mask.nxv2f64.nxv2f32(
|
||||
<vscale x 2 x double>,
|
||||
<vscale x 2 x float>,
|
||||
<vscale x 2 x float>,
|
||||
<vscale x 2 x i1>,
|
||||
i64);
|
||||
|
||||
define <vscale x 2 x double> @intrinsic_vfwmsac_mask_vv_nxv2f64_nxv2f32_nxv2f32(<vscale x 2 x double> %0, <vscale x 2 x float> %1, <vscale x 2 x float> %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
|
||||
; CHECK-LABEL: intrinsic_vfwmsac_mask_vv_nxv2f64_nxv2f32_nxv2f32:
|
||||
; CHECK: # %bb.0: # %entry
|
||||
; CHECK-NEXT: vsetvli a0, a0, e32,m1,ta,mu
|
||||
; CHECK-NEXT: vfwmsac.vv v16, v18, v19, v0.t
|
||||
; CHECK-NEXT: jalr zero, 0(ra)
|
||||
entry:
|
||||
%a = call <vscale x 2 x double> @llvm.riscv.vfwmsac.mask.nxv2f64.nxv2f32(
|
||||
<vscale x 2 x double> %0,
|
||||
<vscale x 2 x float> %1,
|
||||
<vscale x 2 x float> %2,
|
||||
<vscale x 2 x i1> %3,
|
||||
i64 %4)
|
||||
|
||||
ret <vscale x 2 x double> %a
|
||||
}
|
||||
|
||||
declare <vscale x 4 x double> @llvm.riscv.vfwmsac.nxv4f64.nxv4f32(
|
||||
<vscale x 4 x double>,
|
||||
<vscale x 4 x float>,
|
||||
<vscale x 4 x float>,
|
||||
i64);
|
||||
|
||||
define <vscale x 4 x double> @intrinsic_vfwmsac_vv_nxv4f64_nxv4f32_nxv4f32(<vscale x 4 x double> %0, <vscale x 4 x float> %1, <vscale x 4 x float> %2, i64 %3) nounwind {
|
||||
; CHECK-LABEL: intrinsic_vfwmsac_vv_nxv4f64_nxv4f32_nxv4f32:
|
||||
; CHECK: # %bb.0: # %entry
|
||||
; CHECK-NEXT: vsetvli a0, a0, e32,m2,ta,mu
|
||||
; CHECK-NEXT: vfwmsac.vv v16, v20, v22
|
||||
; CHECK-NEXT: jalr zero, 0(ra)
|
||||
entry:
|
||||
%a = call <vscale x 4 x double> @llvm.riscv.vfwmsac.nxv4f64.nxv4f32(
|
||||
<vscale x 4 x double> %0,
|
||||
<vscale x 4 x float> %1,
|
||||
<vscale x 4 x float> %2,
|
||||
i64 %3)
|
||||
|
||||
ret <vscale x 4 x double> %a
|
||||
}
|
||||
|
||||
declare <vscale x 4 x double> @llvm.riscv.vfwmsac.mask.nxv4f64.nxv4f32(
|
||||
<vscale x 4 x double>,
|
||||
<vscale x 4 x float>,
|
||||
<vscale x 4 x float>,
|
||||
<vscale x 4 x i1>,
|
||||
i64);
|
||||
|
||||
define <vscale x 4 x double> @intrinsic_vfwmsac_mask_vv_nxv4f64_nxv4f32_nxv4f32(<vscale x 4 x double> %0, <vscale x 4 x float> %1, <vscale x 4 x float> %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
|
||||
; CHECK-LABEL: intrinsic_vfwmsac_mask_vv_nxv4f64_nxv4f32_nxv4f32:
|
||||
; CHECK: # %bb.0: # %entry
|
||||
; CHECK-NEXT: vsetvli a0, a0, e32,m2,ta,mu
|
||||
; CHECK-NEXT: vfwmsac.vv v16, v20, v22, v0.t
|
||||
; CHECK-NEXT: jalr zero, 0(ra)
|
||||
entry:
|
||||
%a = call <vscale x 4 x double> @llvm.riscv.vfwmsac.mask.nxv4f64.nxv4f32(
|
||||
<vscale x 4 x double> %0,
|
||||
<vscale x 4 x float> %1,
|
||||
<vscale x 4 x float> %2,
|
||||
<vscale x 4 x i1> %3,
|
||||
i64 %4)
|
||||
|
||||
ret <vscale x 4 x double> %a
|
||||
}
|
||||
|
||||
declare <vscale x 8 x double> @llvm.riscv.vfwmsac.nxv8f64.nxv8f32(
|
||||
<vscale x 8 x double>,
|
||||
<vscale x 8 x float>,
|
||||
<vscale x 8 x float>,
|
||||
i64);
|
||||
|
||||
define <vscale x 8 x double> @intrinsic_vfwmsac_vv_nxv8f64_nxv8f32_nxv8f32(<vscale x 8 x double> %0, <vscale x 8 x float> %1, <vscale x 8 x float> %2, i64 %3) nounwind {
|
||||
; CHECK-LABEL: intrinsic_vfwmsac_vv_nxv8f64_nxv8f32_nxv8f32:
|
||||
; CHECK: # %bb.0: # %entry
|
||||
; CHECK-NEXT: vsetvli a3, zero, e32,m4,ta,mu
|
||||
; CHECK-NEXT: vle32.v v28, (a1)
|
||||
; CHECK-NEXT: vle32.v v8, (a0)
|
||||
; CHECK-NEXT: vsetvli a0, a2, e32,m4,ta,mu
|
||||
; CHECK-NEXT: vfwmsac.vv v16, v8, v28
|
||||
; CHECK-NEXT: jalr zero, 0(ra)
|
||||
entry:
|
||||
%a = call <vscale x 8 x double> @llvm.riscv.vfwmsac.nxv8f64.nxv8f32(
|
||||
<vscale x 8 x double> %0,
|
||||
<vscale x 8 x float> %1,
|
||||
<vscale x 8 x float> %2,
|
||||
i64 %3)
|
||||
|
||||
ret <vscale x 8 x double> %a
|
||||
}
|
||||
|
||||
declare <vscale x 8 x double> @llvm.riscv.vfwmsac.mask.nxv8f64.nxv8f32(
|
||||
<vscale x 8 x double>,
|
||||
<vscale x 8 x float>,
|
||||
<vscale x 8 x float>,
|
||||
<vscale x 8 x i1>,
|
||||
i64);
|
||||
|
||||
define <vscale x 8 x double> @intrinsic_vfwmsac_mask_vv_nxv8f64_nxv8f32_nxv8f32(<vscale x 8 x double> %0, <vscale x 8 x float> %1, <vscale x 8 x float> %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
|
||||
; CHECK-LABEL: intrinsic_vfwmsac_mask_vv_nxv8f64_nxv8f32_nxv8f32:
|
||||
; CHECK: # %bb.0: # %entry
|
||||
; CHECK-NEXT: vsetvli a3, zero, e32,m4,ta,mu
|
||||
; CHECK-NEXT: vle32.v v28, (a1)
|
||||
; CHECK-NEXT: vle32.v v8, (a0)
|
||||
; CHECK-NEXT: vsetvli a0, a2, e32,m4,ta,mu
|
||||
; CHECK-NEXT: vfwmsac.vv v16, v8, v28, v0.t
|
||||
; CHECK-NEXT: jalr zero, 0(ra)
|
||||
entry:
|
||||
%a = call <vscale x 8 x double> @llvm.riscv.vfwmsac.mask.nxv8f64.nxv8f32(
|
||||
<vscale x 8 x double> %0,
|
||||
<vscale x 8 x float> %1,
|
||||
<vscale x 8 x float> %2,
|
||||
<vscale x 8 x i1> %3,
|
||||
i64 %4)
|
||||
|
||||
ret <vscale x 8 x double> %a
|
||||
}
|
||||
|
||||
declare <vscale x 1 x float> @llvm.riscv.vfwmsac.nxv1f32.f16(
|
||||
<vscale x 1 x float>,
|
||||
half,
|
||||
<vscale x 1 x half>,
|
||||
i64);
|
||||
|
||||
define <vscale x 1 x float> @intrinsic_vfwmsac_vf_nxv1f32_f16_nxv1f16(<vscale x 1 x float> %0, half %1, <vscale x 1 x half> %2, i64 %3) nounwind {
|
||||
; CHECK-LABEL: intrinsic_vfwmsac_vf_nxv1f32_f16_nxv1f16:
|
||||
; CHECK: # %bb.0: # %entry
|
||||
; CHECK-NEXT: fmv.h.x ft0, a0
|
||||
; CHECK-NEXT: vsetvli a0, a1, e16,mf4,ta,mu
|
||||
; CHECK-NEXT: vfwmsac.vf v16, ft0, v17
|
||||
; CHECK-NEXT: jalr zero, 0(ra)
|
||||
entry:
|
||||
%a = call <vscale x 1 x float> @llvm.riscv.vfwmsac.nxv1f32.f16(
|
||||
<vscale x 1 x float> %0,
|
||||
half %1,
|
||||
<vscale x 1 x half> %2,
|
||||
i64 %3)
|
||||
|
||||
ret <vscale x 1 x float> %a
|
||||
}
|
||||
|
||||
declare <vscale x 1 x float> @llvm.riscv.vfwmsac.mask.nxv1f32.f16(
|
||||
<vscale x 1 x float>,
|
||||
half,
|
||||
<vscale x 1 x half>,
|
||||
<vscale x 1 x i1>,
|
||||
i64);
|
||||
|
||||
define <vscale x 1 x float> @intrinsic_vfwmsac_mask_vf_nxv1f32_f16_nxv1f16(<vscale x 1 x float> %0, half %1, <vscale x 1 x half> %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
|
||||
; CHECK-LABEL: intrinsic_vfwmsac_mask_vf_nxv1f32_f16_nxv1f16:
|
||||
; CHECK: # %bb.0: # %entry
|
||||
; CHECK-NEXT: fmv.h.x ft0, a0
|
||||
; CHECK-NEXT: vsetvli a0, a1, e16,mf4,ta,mu
|
||||
; CHECK-NEXT: vfwmsac.vf v16, ft0, v17, v0.t
|
||||
; CHECK-NEXT: jalr zero, 0(ra)
|
||||
entry:
|
||||
%a = call <vscale x 1 x float> @llvm.riscv.vfwmsac.mask.nxv1f32.f16(
|
||||
<vscale x 1 x float> %0,
|
||||
half %1,
|
||||
<vscale x 1 x half> %2,
|
||||
<vscale x 1 x i1> %3,
|
||||
i64 %4)
|
||||
|
||||
ret <vscale x 1 x float> %a
|
||||
}
|
||||
|
||||
declare <vscale x 2 x float> @llvm.riscv.vfwmsac.nxv2f32.f16(
|
||||
<vscale x 2 x float>,
|
||||
half,
|
||||
<vscale x 2 x half>,
|
||||
i64);
|
||||
|
||||
define <vscale x 2 x float> @intrinsic_vfwmsac_vf_nxv2f32_f16_nxv2f16(<vscale x 2 x float> %0, half %1, <vscale x 2 x half> %2, i64 %3) nounwind {
|
||||
; CHECK-LABEL: intrinsic_vfwmsac_vf_nxv2f32_f16_nxv2f16:
|
||||
; CHECK: # %bb.0: # %entry
|
||||
; CHECK-NEXT: fmv.h.x ft0, a0
|
||||
; CHECK-NEXT: vsetvli a0, a1, e16,mf2,ta,mu
|
||||
; CHECK-NEXT: vfwmsac.vf v16, ft0, v17
|
||||
; CHECK-NEXT: jalr zero, 0(ra)
|
||||
entry:
|
||||
%a = call <vscale x 2 x float> @llvm.riscv.vfwmsac.nxv2f32.f16(
|
||||
<vscale x 2 x float> %0,
|
||||
half %1,
|
||||
<vscale x 2 x half> %2,
|
||||
i64 %3)
|
||||
|
||||
ret <vscale x 2 x float> %a
|
||||
}
|
||||
|
||||
declare <vscale x 2 x float> @llvm.riscv.vfwmsac.mask.nxv2f32.f16(
|
||||
<vscale x 2 x float>,
|
||||
half,
|
||||
<vscale x 2 x half>,
|
||||
<vscale x 2 x i1>,
|
||||
i64);
|
||||
|
||||
define <vscale x 2 x float> @intrinsic_vfwmsac_mask_vf_nxv2f32_f16_nxv2f16(<vscale x 2 x float> %0, half %1, <vscale x 2 x half> %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
|
||||
; CHECK-LABEL: intrinsic_vfwmsac_mask_vf_nxv2f32_f16_nxv2f16:
|
||||
; CHECK: # %bb.0: # %entry
|
||||
; CHECK-NEXT: fmv.h.x ft0, a0
|
||||
; CHECK-NEXT: vsetvli a0, a1, e16,mf2,ta,mu
|
||||
; CHECK-NEXT: vfwmsac.vf v16, ft0, v17, v0.t
|
||||
; CHECK-NEXT: jalr zero, 0(ra)
|
||||
entry:
|
||||
%a = call <vscale x 2 x float> @llvm.riscv.vfwmsac.mask.nxv2f32.f16(
|
||||
<vscale x 2 x float> %0,
|
||||
half %1,
|
||||
<vscale x 2 x half> %2,
|
||||
<vscale x 2 x i1> %3,
|
||||
i64 %4)
|
||||
|
||||
ret <vscale x 2 x float> %a
|
||||
}
|
||||
|
||||
declare <vscale x 4 x float> @llvm.riscv.vfwmsac.nxv4f32.f16(
|
||||
<vscale x 4 x float>,
|
||||
half,
|
||||
<vscale x 4 x half>,
|
||||
i64);
|
||||
|
||||
define <vscale x 4 x float> @intrinsic_vfwmsac_vf_nxv4f32_f16_nxv4f16(<vscale x 4 x float> %0, half %1, <vscale x 4 x half> %2, i64 %3) nounwind {
|
||||
; CHECK-LABEL: intrinsic_vfwmsac_vf_nxv4f32_f16_nxv4f16:
|
||||
; CHECK: # %bb.0: # %entry
|
||||
; CHECK-NEXT: fmv.h.x ft0, a0
|
||||
; CHECK-NEXT: vsetvli a0, a1, e16,m1,ta,mu
|
||||
; CHECK-NEXT: vfwmsac.vf v16, ft0, v18
|
||||
; CHECK-NEXT: jalr zero, 0(ra)
|
||||
entry:
|
||||
%a = call <vscale x 4 x float> @llvm.riscv.vfwmsac.nxv4f32.f16(
|
||||
<vscale x 4 x float> %0,
|
||||
half %1,
|
||||
<vscale x 4 x half> %2,
|
||||
i64 %3)
|
||||
|
||||
ret <vscale x 4 x float> %a
|
||||
}
|
||||
|
||||
declare <vscale x 4 x float> @llvm.riscv.vfwmsac.mask.nxv4f32.f16(
|
||||
<vscale x 4 x float>,
|
||||
half,
|
||||
<vscale x 4 x half>,
|
||||
<vscale x 4 x i1>,
|
||||
i64);
|
||||
|
||||
define <vscale x 4 x float> @intrinsic_vfwmsac_mask_vf_nxv4f32_f16_nxv4f16(<vscale x 4 x float> %0, half %1, <vscale x 4 x half> %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
|
||||
; CHECK-LABEL: intrinsic_vfwmsac_mask_vf_nxv4f32_f16_nxv4f16:
|
||||
; CHECK: # %bb.0: # %entry
|
||||
; CHECK-NEXT: fmv.h.x ft0, a0
|
||||
; CHECK-NEXT: vsetvli a0, a1, e16,m1,ta,mu
|
||||
; CHECK-NEXT: vfwmsac.vf v16, ft0, v18, v0.t
|
||||
; CHECK-NEXT: jalr zero, 0(ra)
|
||||
entry:
|
||||
%a = call <vscale x 4 x float> @llvm.riscv.vfwmsac.mask.nxv4f32.f16(
|
||||
<vscale x 4 x float> %0,
|
||||
half %1,
|
||||
<vscale x 4 x half> %2,
|
||||
<vscale x 4 x i1> %3,
|
||||
i64 %4)
|
||||
|
||||
ret <vscale x 4 x float> %a
|
||||
}
|
||||
|
||||
declare <vscale x 8 x float> @llvm.riscv.vfwmsac.nxv8f32.f16(
|
||||
<vscale x 8 x float>,
|
||||
half,
|
||||
<vscale x 8 x half>,
|
||||
i64);
|
||||
|
||||
define <vscale x 8 x float> @intrinsic_vfwmsac_vf_nxv8f32_f16_nxv8f16(<vscale x 8 x float> %0, half %1, <vscale x 8 x half> %2, i64 %3) nounwind {
|
||||
; CHECK-LABEL: intrinsic_vfwmsac_vf_nxv8f32_f16_nxv8f16:
|
||||
; CHECK: # %bb.0: # %entry
|
||||
; CHECK-NEXT: fmv.h.x ft0, a0
|
||||
; CHECK-NEXT: vsetvli a0, a1, e16,m2,ta,mu
|
||||
; CHECK-NEXT: vfwmsac.vf v16, ft0, v20
|
||||
; CHECK-NEXT: jalr zero, 0(ra)
|
||||
entry:
|
||||
%a = call <vscale x 8 x float> @llvm.riscv.vfwmsac.nxv8f32.f16(
|
||||
<vscale x 8 x float> %0,
|
||||
half %1,
|
||||
<vscale x 8 x half> %2,
|
||||
i64 %3)
|
||||
|
||||
ret <vscale x 8 x float> %a
|
||||
}
|
||||
|
||||
declare <vscale x 8 x float> @llvm.riscv.vfwmsac.mask.nxv8f32.f16(
|
||||
<vscale x 8 x float>,
|
||||
half,
|
||||
<vscale x 8 x half>,
|
||||
<vscale x 8 x i1>,
|
||||
i64);
|
||||
|
||||
define <vscale x 8 x float> @intrinsic_vfwmsac_mask_vf_nxv8f32_f16_nxv8f16(<vscale x 8 x float> %0, half %1, <vscale x 8 x half> %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
|
||||
; CHECK-LABEL: intrinsic_vfwmsac_mask_vf_nxv8f32_f16_nxv8f16:
|
||||
; CHECK: # %bb.0: # %entry
|
||||
; CHECK-NEXT: fmv.h.x ft0, a0
|
||||
; CHECK-NEXT: vsetvli a0, a1, e16,m2,ta,mu
|
||||
; CHECK-NEXT: vfwmsac.vf v16, ft0, v20, v0.t
|
||||
; CHECK-NEXT: jalr zero, 0(ra)
|
||||
entry:
|
||||
%a = call <vscale x 8 x float> @llvm.riscv.vfwmsac.mask.nxv8f32.f16(
|
||||
<vscale x 8 x float> %0,
|
||||
half %1,
|
||||
<vscale x 8 x half> %2,
|
||||
<vscale x 8 x i1> %3,
|
||||
i64 %4)
|
||||
|
||||
ret <vscale x 8 x float> %a
|
||||
}
|
||||
|
||||
declare <vscale x 16 x float> @llvm.riscv.vfwmsac.nxv16f32.f16(
|
||||
<vscale x 16 x float>,
|
||||
half,
|
||||
<vscale x 16 x half>,
|
||||
i64);
|
||||
|
||||
define <vscale x 16 x float> @intrinsic_vfwmsac_vf_nxv16f32_f16_nxv16f16(<vscale x 16 x float> %0, half %1, <vscale x 16 x half> %2, i64 %3) nounwind {
|
||||
; CHECK-LABEL: intrinsic_vfwmsac_vf_nxv16f32_f16_nxv16f16:
|
||||
; CHECK: # %bb.0: # %entry
|
||||
; CHECK-NEXT: vsetvli a3, zero, e16,m4,ta,mu
|
||||
; CHECK-NEXT: vle16.v v28, (a1)
|
||||
; CHECK-NEXT: fmv.h.x ft0, a0
|
||||
; CHECK-NEXT: vsetvli a0, a2, e16,m4,ta,mu
|
||||
; CHECK-NEXT: vfwmsac.vf v16, ft0, v28
|
||||
; CHECK-NEXT: jalr zero, 0(ra)
|
||||
entry:
|
||||
%a = call <vscale x 16 x float> @llvm.riscv.vfwmsac.nxv16f32.f16(
|
||||
<vscale x 16 x float> %0,
|
||||
half %1,
|
||||
<vscale x 16 x half> %2,
|
||||
i64 %3)
|
||||
|
||||
ret <vscale x 16 x float> %a
|
||||
}
|
||||
|
||||
declare <vscale x 16 x float> @llvm.riscv.vfwmsac.mask.nxv16f32.f16(
|
||||
<vscale x 16 x float>,
|
||||
half,
|
||||
<vscale x 16 x half>,
|
||||
<vscale x 16 x i1>,
|
||||
i64);
|
||||
|
||||
define <vscale x 16 x float> @intrinsic_vfwmsac_mask_vf_nxv16f32_f16_nxv16f16(<vscale x 16 x float> %0, half %1, <vscale x 16 x half> %2, <vscale x 16 x i1> %3, i64 %4) nounwind {
|
||||
; CHECK-LABEL: intrinsic_vfwmsac_mask_vf_nxv16f32_f16_nxv16f16:
|
||||
; CHECK: # %bb.0: # %entry
|
||||
; CHECK-NEXT: vsetvli a3, zero, e16,m4,ta,mu
|
||||
; CHECK-NEXT: vle16.v v28, (a1)
|
||||
; CHECK-NEXT: fmv.h.x ft0, a0
|
||||
; CHECK-NEXT: vsetvli a0, a2, e16,m4,ta,mu
|
||||
; CHECK-NEXT: vfwmsac.vf v16, ft0, v28, v0.t
|
||||
; CHECK-NEXT: jalr zero, 0(ra)
|
||||
entry:
|
||||
%a = call <vscale x 16 x float> @llvm.riscv.vfwmsac.mask.nxv16f32.f16(
|
||||
<vscale x 16 x float> %0,
|
||||
half %1,
|
||||
<vscale x 16 x half> %2,
|
||||
<vscale x 16 x i1> %3,
|
||||
i64 %4)
|
||||
|
||||
ret <vscale x 16 x float> %a
|
||||
}
|
||||
|
||||
declare <vscale x 1 x double> @llvm.riscv.vfwmsac.nxv1f64.f32(
|
||||
<vscale x 1 x double>,
|
||||
float,
|
||||
<vscale x 1 x float>,
|
||||
i64);
|
||||
|
||||
define <vscale x 1 x double> @intrinsic_vfwmsac_vf_nxv1f64_f32_nxv1f32(<vscale x 1 x double> %0, float %1, <vscale x 1 x float> %2, i64 %3) nounwind {
|
||||
; CHECK-LABEL: intrinsic_vfwmsac_vf_nxv1f64_f32_nxv1f32:
|
||||
; CHECK: # %bb.0: # %entry
|
||||
; CHECK-NEXT: fmv.w.x ft0, a0
|
||||
; CHECK-NEXT: vsetvli a0, a1, e32,mf2,ta,mu
|
||||
; CHECK-NEXT: vfwmsac.vf v16, ft0, v17
|
||||
; CHECK-NEXT: jalr zero, 0(ra)
|
||||
entry:
|
||||
%a = call <vscale x 1 x double> @llvm.riscv.vfwmsac.nxv1f64.f32(
|
||||
<vscale x 1 x double> %0,
|
||||
float %1,
|
||||
<vscale x 1 x float> %2,
|
||||
i64 %3)
|
||||
|
||||
ret <vscale x 1 x double> %a
|
||||
}
|
||||
|
||||
declare <vscale x 1 x double> @llvm.riscv.vfwmsac.mask.nxv1f64.f32(
|
||||
<vscale x 1 x double>,
|
||||
float,
|
||||
<vscale x 1 x float>,
|
||||
<vscale x 1 x i1>,
|
||||
i64);
|
||||
|
||||
define <vscale x 1 x double> @intrinsic_vfwmsac_mask_vf_nxv1f64_f32_nxv1f32(<vscale x 1 x double> %0, float %1, <vscale x 1 x float> %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
|
||||
; CHECK-LABEL: intrinsic_vfwmsac_mask_vf_nxv1f64_f32_nxv1f32:
|
||||
; CHECK: # %bb.0: # %entry
|
||||
; CHECK-NEXT: fmv.w.x ft0, a0
|
||||
; CHECK-NEXT: vsetvli a0, a1, e32,mf2,ta,mu
|
||||
; CHECK-NEXT: vfwmsac.vf v16, ft0, v17, v0.t
|
||||
; CHECK-NEXT: jalr zero, 0(ra)
|
||||
entry:
|
||||
%a = call <vscale x 1 x double> @llvm.riscv.vfwmsac.mask.nxv1f64.f32(
|
||||
<vscale x 1 x double> %0,
|
||||
float %1,
|
||||
<vscale x 1 x float> %2,
|
||||
<vscale x 1 x i1> %3,
|
||||
i64 %4)
|
||||
|
||||
ret <vscale x 1 x double> %a
|
||||
}
|
||||
|
||||
declare <vscale x 2 x double> @llvm.riscv.vfwmsac.nxv2f64.f32(
|
||||
<vscale x 2 x double>,
|
||||
float,
|
||||
<vscale x 2 x float>,
|
||||
i64);
|
||||
|
||||
define <vscale x 2 x double> @intrinsic_vfwmsac_vf_nxv2f64_f32_nxv2f32(<vscale x 2 x double> %0, float %1, <vscale x 2 x float> %2, i64 %3) nounwind {
|
||||
; CHECK-LABEL: intrinsic_vfwmsac_vf_nxv2f64_f32_nxv2f32:
|
||||
; CHECK: # %bb.0: # %entry
|
||||
; CHECK-NEXT: fmv.w.x ft0, a0
|
||||
; CHECK-NEXT: vsetvli a0, a1, e32,m1,ta,mu
|
||||
; CHECK-NEXT: vfwmsac.vf v16, ft0, v18
|
||||
; CHECK-NEXT: jalr zero, 0(ra)
|
||||
entry:
|
||||
%a = call <vscale x 2 x double> @llvm.riscv.vfwmsac.nxv2f64.f32(
|
||||
<vscale x 2 x double> %0,
|
||||
float %1,
|
||||
<vscale x 2 x float> %2,
|
||||
i64 %3)
|
||||
|
||||
ret <vscale x 2 x double> %a
|
||||
}
|
||||
|
||||
declare <vscale x 2 x double> @llvm.riscv.vfwmsac.mask.nxv2f64.f32(
|
||||
<vscale x 2 x double>,
|
||||
float,
|
||||
<vscale x 2 x float>,
|
||||
<vscale x 2 x i1>,
|
||||
i64);
|
||||
|
||||
define <vscale x 2 x double> @intrinsic_vfwmsac_mask_vf_nxv2f64_f32_nxv2f32(<vscale x 2 x double> %0, float %1, <vscale x 2 x float> %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
|
||||
; CHECK-LABEL: intrinsic_vfwmsac_mask_vf_nxv2f64_f32_nxv2f32:
|
||||
; CHECK: # %bb.0: # %entry
|
||||
; CHECK-NEXT: fmv.w.x ft0, a0
|
||||
; CHECK-NEXT: vsetvli a0, a1, e32,m1,ta,mu
|
||||
; CHECK-NEXT: vfwmsac.vf v16, ft0, v18, v0.t
|
||||
; CHECK-NEXT: jalr zero, 0(ra)
|
||||
entry:
|
||||
%a = call <vscale x 2 x double> @llvm.riscv.vfwmsac.mask.nxv2f64.f32(
|
||||
<vscale x 2 x double> %0,
|
||||
float %1,
|
||||
<vscale x 2 x float> %2,
|
||||
<vscale x 2 x i1> %3,
|
||||
i64 %4)
|
||||
|
||||
ret <vscale x 2 x double> %a
|
||||
}
|
||||
|
||||
declare <vscale x 4 x double> @llvm.riscv.vfwmsac.nxv4f64.f32(
|
||||
<vscale x 4 x double>,
|
||||
float,
|
||||
<vscale x 4 x float>,
|
||||
i64);
|
||||
|
||||
define <vscale x 4 x double> @intrinsic_vfwmsac_vf_nxv4f64_f32_nxv4f32(<vscale x 4 x double> %0, float %1, <vscale x 4 x float> %2, i64 %3) nounwind {
|
||||
; CHECK-LABEL: intrinsic_vfwmsac_vf_nxv4f64_f32_nxv4f32:
|
||||
; CHECK: # %bb.0: # %entry
|
||||
; CHECK-NEXT: fmv.w.x ft0, a0
|
||||
; CHECK-NEXT: vsetvli a0, a1, e32,m2,ta,mu
|
||||
; CHECK-NEXT: vfwmsac.vf v16, ft0, v20
|
||||
; CHECK-NEXT: jalr zero, 0(ra)
|
||||
entry:
|
||||
%a = call <vscale x 4 x double> @llvm.riscv.vfwmsac.nxv4f64.f32(
|
||||
<vscale x 4 x double> %0,
|
||||
float %1,
|
||||
<vscale x 4 x float> %2,
|
||||
i64 %3)
|
||||
|
||||
ret <vscale x 4 x double> %a
|
||||
}
|
||||
|
||||
declare <vscale x 4 x double> @llvm.riscv.vfwmsac.mask.nxv4f64.f32(
|
||||
<vscale x 4 x double>,
|
||||
float,
|
||||
<vscale x 4 x float>,
|
||||
<vscale x 4 x i1>,
|
||||
i64);
|
||||
|
||||
define <vscale x 4 x double> @intrinsic_vfwmsac_mask_vf_nxv4f64_f32_nxv4f32(<vscale x 4 x double> %0, float %1, <vscale x 4 x float> %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
|
||||
; CHECK-LABEL: intrinsic_vfwmsac_mask_vf_nxv4f64_f32_nxv4f32:
|
||||
; CHECK: # %bb.0: # %entry
|
||||
; CHECK-NEXT: fmv.w.x ft0, a0
|
||||
; CHECK-NEXT: vsetvli a0, a1, e32,m2,ta,mu
|
||||
; CHECK-NEXT: vfwmsac.vf v16, ft0, v20, v0.t
|
||||
; CHECK-NEXT: jalr zero, 0(ra)
|
||||
entry:
|
||||
%a = call <vscale x 4 x double> @llvm.riscv.vfwmsac.mask.nxv4f64.f32(
|
||||
<vscale x 4 x double> %0,
|
||||
float %1,
|
||||
<vscale x 4 x float> %2,
|
||||
<vscale x 4 x i1> %3,
|
||||
i64 %4)
|
||||
|
||||
ret <vscale x 4 x double> %a
|
||||
}
|
||||
|
||||
declare <vscale x 8 x double> @llvm.riscv.vfwmsac.nxv8f64.f32(
|
||||
<vscale x 8 x double>,
|
||||
float,
|
||||
<vscale x 8 x float>,
|
||||
i64);
|
||||
|
||||
define <vscale x 8 x double> @intrinsic_vfwmsac_vf_nxv8f64_f32_nxv8f32(<vscale x 8 x double> %0, float %1, <vscale x 8 x float> %2, i64 %3) nounwind {
|
||||
; CHECK-LABEL: intrinsic_vfwmsac_vf_nxv8f64_f32_nxv8f32:
|
||||
; CHECK: # %bb.0: # %entry
|
||||
; CHECK-NEXT: vsetvli a3, zero, e32,m4,ta,mu
|
||||
; CHECK-NEXT: vle32.v v28, (a1)
|
||||
; CHECK-NEXT: fmv.w.x ft0, a0
|
||||
; CHECK-NEXT: vsetvli a0, a2, e32,m4,ta,mu
|
||||
; CHECK-NEXT: vfwmsac.vf v16, ft0, v28
|
||||
; CHECK-NEXT: jalr zero, 0(ra)
|
||||
entry:
|
||||
%a = call <vscale x 8 x double> @llvm.riscv.vfwmsac.nxv8f64.f32(
|
||||
<vscale x 8 x double> %0,
|
||||
float %1,
|
||||
<vscale x 8 x float> %2,
|
||||
i64 %3)
|
||||
|
||||
ret <vscale x 8 x double> %a
|
||||
}
|
||||
|
||||
declare <vscale x 8 x double> @llvm.riscv.vfwmsac.mask.nxv8f64.f32(
|
||||
<vscale x 8 x double>,
|
||||
float,
|
||||
<vscale x 8 x float>,
|
||||
<vscale x 8 x i1>,
|
||||
i64);
|
||||
|
||||
define <vscale x 8 x double> @intrinsic_vfwmsac_mask_vf_nxv8f64_f32_nxv8f32(<vscale x 8 x double> %0, float %1, <vscale x 8 x float> %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
|
||||
; CHECK-LABEL: intrinsic_vfwmsac_mask_vf_nxv8f64_f32_nxv8f32:
|
||||
; CHECK: # %bb.0: # %entry
|
||||
; CHECK-NEXT: vsetvli a3, zero, e32,m4,ta,mu
|
||||
; CHECK-NEXT: vle32.v v28, (a1)
|
||||
; CHECK-NEXT: fmv.w.x ft0, a0
|
||||
; CHECK-NEXT: vsetvli a0, a2, e32,m4,ta,mu
|
||||
; CHECK-NEXT: vfwmsac.vf v16, ft0, v28, v0.t
|
||||
; CHECK-NEXT: jalr zero, 0(ra)
|
||||
entry:
|
||||
%a = call <vscale x 8 x double> @llvm.riscv.vfwmsac.mask.nxv8f64.f32(
|
||||
<vscale x 8 x double> %0,
|
||||
float %1,
|
||||
<vscale x 8 x float> %2,
|
||||
<vscale x 8 x i1> %3,
|
||||
i64 %4)
|
||||
|
||||
ret <vscale x 8 x double> %a
|
||||
}
|
||||
482
test/CodeGen/RISCV/rvv/vfwnmacc-rv32.ll
Normal file
482
test/CodeGen/RISCV/rvv/vfwnmacc-rv32.ll
Normal file
@ -0,0 +1,482 @@
|
||||
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
|
||||
; RUN: llc -mtriple=riscv32 -mattr=+experimental-v,+f,+experimental-zfh -verify-machineinstrs \
|
||||
; RUN: --riscv-no-aliases < %s | FileCheck %s
|
||||
declare <vscale x 1 x float> @llvm.riscv.vfwnmacc.nxv1f32.nxv1f16(
|
||||
<vscale x 1 x float>,
|
||||
<vscale x 1 x half>,
|
||||
<vscale x 1 x half>,
|
||||
i32);
|
||||
|
||||
define <vscale x 1 x float> @intrinsic_vfwnmacc_vv_nxv1f32_nxv1f16_nxv1f16(<vscale x 1 x float> %0, <vscale x 1 x half> %1, <vscale x 1 x half> %2, i32 %3) nounwind {
|
||||
; CHECK-LABEL: intrinsic_vfwnmacc_vv_nxv1f32_nxv1f16_nxv1f16:
|
||||
; CHECK: # %bb.0: # %entry
|
||||
; CHECK-NEXT: vsetvli a0, a0, e16,mf4,ta,mu
|
||||
; CHECK-NEXT: vfwnmacc.vv v16, v17, v18
|
||||
; CHECK-NEXT: jalr zero, 0(ra)
|
||||
entry:
|
||||
%a = call <vscale x 1 x float> @llvm.riscv.vfwnmacc.nxv1f32.nxv1f16(
|
||||
<vscale x 1 x float> %0,
|
||||
<vscale x 1 x half> %1,
|
||||
<vscale x 1 x half> %2,
|
||||
i32 %3)
|
||||
|
||||
ret <vscale x 1 x float> %a
|
||||
}
|
||||
|
||||
declare <vscale x 1 x float> @llvm.riscv.vfwnmacc.mask.nxv1f32.nxv1f16(
|
||||
<vscale x 1 x float>,
|
||||
<vscale x 1 x half>,
|
||||
<vscale x 1 x half>,
|
||||
<vscale x 1 x i1>,
|
||||
i32);
|
||||
|
||||
define <vscale x 1 x float> @intrinsic_vfwnmacc_mask_vv_nxv1f32_nxv1f16_nxv1f16(<vscale x 1 x float> %0, <vscale x 1 x half> %1, <vscale x 1 x half> %2, <vscale x 1 x i1> %3, i32 %4) nounwind {
|
||||
; CHECK-LABEL: intrinsic_vfwnmacc_mask_vv_nxv1f32_nxv1f16_nxv1f16:
|
||||
; CHECK: # %bb.0: # %entry
|
||||
; CHECK-NEXT: vsetvli a0, a0, e16,mf4,ta,mu
|
||||
; CHECK-NEXT: vfwnmacc.vv v16, v17, v18, v0.t
|
||||
; CHECK-NEXT: jalr zero, 0(ra)
|
||||
entry:
|
||||
%a = call <vscale x 1 x float> @llvm.riscv.vfwnmacc.mask.nxv1f32.nxv1f16(
|
||||
<vscale x 1 x float> %0,
|
||||
<vscale x 1 x half> %1,
|
||||
<vscale x 1 x half> %2,
|
||||
<vscale x 1 x i1> %3,
|
||||
i32 %4)
|
||||
|
||||
ret <vscale x 1 x float> %a
|
||||
}
|
||||
|
||||
declare <vscale x 2 x float> @llvm.riscv.vfwnmacc.nxv2f32.nxv2f16(
|
||||
<vscale x 2 x float>,
|
||||
<vscale x 2 x half>,
|
||||
<vscale x 2 x half>,
|
||||
i32);
|
||||
|
||||
define <vscale x 2 x float> @intrinsic_vfwnmacc_vv_nxv2f32_nxv2f16_nxv2f16(<vscale x 2 x float> %0, <vscale x 2 x half> %1, <vscale x 2 x half> %2, i32 %3) nounwind {
|
||||
; CHECK-LABEL: intrinsic_vfwnmacc_vv_nxv2f32_nxv2f16_nxv2f16:
|
||||
; CHECK: # %bb.0: # %entry
|
||||
; CHECK-NEXT: vsetvli a0, a0, e16,mf2,ta,mu
|
||||
; CHECK-NEXT: vfwnmacc.vv v16, v17, v18
|
||||
; CHECK-NEXT: jalr zero, 0(ra)
|
||||
entry:
|
||||
%a = call <vscale x 2 x float> @llvm.riscv.vfwnmacc.nxv2f32.nxv2f16(
|
||||
<vscale x 2 x float> %0,
|
||||
<vscale x 2 x half> %1,
|
||||
<vscale x 2 x half> %2,
|
||||
i32 %3)
|
||||
|
||||
ret <vscale x 2 x float> %a
|
||||
}
|
||||
|
||||
declare <vscale x 2 x float> @llvm.riscv.vfwnmacc.mask.nxv2f32.nxv2f16(
|
||||
<vscale x 2 x float>,
|
||||
<vscale x 2 x half>,
|
||||
<vscale x 2 x half>,
|
||||
<vscale x 2 x i1>,
|
||||
i32);
|
||||
|
||||
define <vscale x 2 x float> @intrinsic_vfwnmacc_mask_vv_nxv2f32_nxv2f16_nxv2f16(<vscale x 2 x float> %0, <vscale x 2 x half> %1, <vscale x 2 x half> %2, <vscale x 2 x i1> %3, i32 %4) nounwind {
|
||||
; CHECK-LABEL: intrinsic_vfwnmacc_mask_vv_nxv2f32_nxv2f16_nxv2f16:
|
||||
; CHECK: # %bb.0: # %entry
|
||||
; CHECK-NEXT: vsetvli a0, a0, e16,mf2,ta,mu
|
||||
; CHECK-NEXT: vfwnmacc.vv v16, v17, v18, v0.t
|
||||
; CHECK-NEXT: jalr zero, 0(ra)
|
||||
entry:
|
||||
%a = call <vscale x 2 x float> @llvm.riscv.vfwnmacc.mask.nxv2f32.nxv2f16(
|
||||
<vscale x 2 x float> %0,
|
||||
<vscale x 2 x half> %1,
|
||||
<vscale x 2 x half> %2,
|
||||
<vscale x 2 x i1> %3,
|
||||
i32 %4)
|
||||
|
||||
ret <vscale x 2 x float> %a
|
||||
}
|
||||
|
||||
declare <vscale x 4 x float> @llvm.riscv.vfwnmacc.nxv4f32.nxv4f16(
|
||||
<vscale x 4 x float>,
|
||||
<vscale x 4 x half>,
|
||||
<vscale x 4 x half>,
|
||||
i32);
|
||||
|
||||
define <vscale x 4 x float> @intrinsic_vfwnmacc_vv_nxv4f32_nxv4f16_nxv4f16(<vscale x 4 x float> %0, <vscale x 4 x half> %1, <vscale x 4 x half> %2, i32 %3) nounwind {
|
||||
; CHECK-LABEL: intrinsic_vfwnmacc_vv_nxv4f32_nxv4f16_nxv4f16:
|
||||
; CHECK: # %bb.0: # %entry
|
||||
; CHECK-NEXT: vsetvli a0, a0, e16,m1,ta,mu
|
||||
; CHECK-NEXT: vfwnmacc.vv v16, v18, v19
|
||||
; CHECK-NEXT: jalr zero, 0(ra)
|
||||
entry:
|
||||
%a = call <vscale x 4 x float> @llvm.riscv.vfwnmacc.nxv4f32.nxv4f16(
|
||||
<vscale x 4 x float> %0,
|
||||
<vscale x 4 x half> %1,
|
||||
<vscale x 4 x half> %2,
|
||||
i32 %3)
|
||||
|
||||
ret <vscale x 4 x float> %a
|
||||
}
|
||||
|
||||
declare <vscale x 4 x float> @llvm.riscv.vfwnmacc.mask.nxv4f32.nxv4f16(
|
||||
<vscale x 4 x float>,
|
||||
<vscale x 4 x half>,
|
||||
<vscale x 4 x half>,
|
||||
<vscale x 4 x i1>,
|
||||
i32);
|
||||
|
||||
define <vscale x 4 x float> @intrinsic_vfwnmacc_mask_vv_nxv4f32_nxv4f16_nxv4f16(<vscale x 4 x float> %0, <vscale x 4 x half> %1, <vscale x 4 x half> %2, <vscale x 4 x i1> %3, i32 %4) nounwind {
|
||||
; CHECK-LABEL: intrinsic_vfwnmacc_mask_vv_nxv4f32_nxv4f16_nxv4f16:
|
||||
; CHECK: # %bb.0: # %entry
|
||||
; CHECK-NEXT: vsetvli a0, a0, e16,m1,ta,mu
|
||||
; CHECK-NEXT: vfwnmacc.vv v16, v18, v19, v0.t
|
||||
; CHECK-NEXT: jalr zero, 0(ra)
|
||||
entry:
|
||||
%a = call <vscale x 4 x float> @llvm.riscv.vfwnmacc.mask.nxv4f32.nxv4f16(
|
||||
<vscale x 4 x float> %0,
|
||||
<vscale x 4 x half> %1,
|
||||
<vscale x 4 x half> %2,
|
||||
<vscale x 4 x i1> %3,
|
||||
i32 %4)
|
||||
|
||||
ret <vscale x 4 x float> %a
|
||||
}
|
||||
|
||||
declare <vscale x 8 x float> @llvm.riscv.vfwnmacc.nxv8f32.nxv8f16(
|
||||
<vscale x 8 x float>,
|
||||
<vscale x 8 x half>,
|
||||
<vscale x 8 x half>,
|
||||
i32);
|
||||
|
||||
define <vscale x 8 x float> @intrinsic_vfwnmacc_vv_nxv8f32_nxv8f16_nxv8f16(<vscale x 8 x float> %0, <vscale x 8 x half> %1, <vscale x 8 x half> %2, i32 %3) nounwind {
|
||||
; CHECK-LABEL: intrinsic_vfwnmacc_vv_nxv8f32_nxv8f16_nxv8f16:
|
||||
; CHECK: # %bb.0: # %entry
|
||||
; CHECK-NEXT: vsetvli a0, a0, e16,m2,ta,mu
|
||||
; CHECK-NEXT: vfwnmacc.vv v16, v20, v22
|
||||
; CHECK-NEXT: jalr zero, 0(ra)
|
||||
entry:
|
||||
%a = call <vscale x 8 x float> @llvm.riscv.vfwnmacc.nxv8f32.nxv8f16(
|
||||
<vscale x 8 x float> %0,
|
||||
<vscale x 8 x half> %1,
|
||||
<vscale x 8 x half> %2,
|
||||
i32 %3)
|
||||
|
||||
ret <vscale x 8 x float> %a
|
||||
}
|
||||
|
||||
declare <vscale x 8 x float> @llvm.riscv.vfwnmacc.mask.nxv8f32.nxv8f16(
|
||||
<vscale x 8 x float>,
|
||||
<vscale x 8 x half>,
|
||||
<vscale x 8 x half>,
|
||||
<vscale x 8 x i1>,
|
||||
i32);
|
||||
|
||||
define <vscale x 8 x float> @intrinsic_vfwnmacc_mask_vv_nxv8f32_nxv8f16_nxv8f16(<vscale x 8 x float> %0, <vscale x 8 x half> %1, <vscale x 8 x half> %2, <vscale x 8 x i1> %3, i32 %4) nounwind {
|
||||
; CHECK-LABEL: intrinsic_vfwnmacc_mask_vv_nxv8f32_nxv8f16_nxv8f16:
|
||||
; CHECK: # %bb.0: # %entry
|
||||
; CHECK-NEXT: vsetvli a0, a0, e16,m2,ta,mu
|
||||
; CHECK-NEXT: vfwnmacc.vv v16, v20, v22, v0.t
|
||||
; CHECK-NEXT: jalr zero, 0(ra)
|
||||
entry:
|
||||
%a = call <vscale x 8 x float> @llvm.riscv.vfwnmacc.mask.nxv8f32.nxv8f16(
|
||||
<vscale x 8 x float> %0,
|
||||
<vscale x 8 x half> %1,
|
||||
<vscale x 8 x half> %2,
|
||||
<vscale x 8 x i1> %3,
|
||||
i32 %4)
|
||||
|
||||
ret <vscale x 8 x float> %a
|
||||
}
|
||||
|
||||
declare <vscale x 16 x float> @llvm.riscv.vfwnmacc.nxv16f32.nxv16f16(
|
||||
<vscale x 16 x float>,
|
||||
<vscale x 16 x half>,
|
||||
<vscale x 16 x half>,
|
||||
i32);
|
||||
|
||||
define <vscale x 16 x float> @intrinsic_vfwnmacc_vv_nxv16f32_nxv16f16_nxv16f16(<vscale x 16 x float> %0, <vscale x 16 x half> %1, <vscale x 16 x half> %2, i32 %3) nounwind {
|
||||
; CHECK-LABEL: intrinsic_vfwnmacc_vv_nxv16f32_nxv16f16_nxv16f16:
|
||||
; CHECK: # %bb.0: # %entry
|
||||
; CHECK-NEXT: vsetvli a3, zero, e16,m4,ta,mu
|
||||
; CHECK-NEXT: vle16.v v28, (a1)
|
||||
; CHECK-NEXT: vle16.v v8, (a0)
|
||||
; CHECK-NEXT: vsetvli a0, a2, e16,m4,ta,mu
|
||||
; CHECK-NEXT: vfwnmacc.vv v16, v8, v28
|
||||
; CHECK-NEXT: jalr zero, 0(ra)
|
||||
entry:
|
||||
%a = call <vscale x 16 x float> @llvm.riscv.vfwnmacc.nxv16f32.nxv16f16(
|
||||
<vscale x 16 x float> %0,
|
||||
<vscale x 16 x half> %1,
|
||||
<vscale x 16 x half> %2,
|
||||
i32 %3)
|
||||
|
||||
ret <vscale x 16 x float> %a
|
||||
}
|
||||
|
||||
declare <vscale x 16 x float> @llvm.riscv.vfwnmacc.mask.nxv16f32.nxv16f16(
|
||||
<vscale x 16 x float>,
|
||||
<vscale x 16 x half>,
|
||||
<vscale x 16 x half>,
|
||||
<vscale x 16 x i1>,
|
||||
i32);
|
||||
|
||||
define <vscale x 16 x float> @intrinsic_vfwnmacc_mask_vv_nxv16f32_nxv16f16_nxv16f16(<vscale x 16 x float> %0, <vscale x 16 x half> %1, <vscale x 16 x half> %2, <vscale x 16 x i1> %3, i32 %4) nounwind {
|
||||
; CHECK-LABEL: intrinsic_vfwnmacc_mask_vv_nxv16f32_nxv16f16_nxv16f16:
|
||||
; CHECK: # %bb.0: # %entry
|
||||
; CHECK-NEXT: vsetvli a3, zero, e16,m4,ta,mu
|
||||
; CHECK-NEXT: vle16.v v28, (a1)
|
||||
; CHECK-NEXT: vle16.v v8, (a0)
|
||||
; CHECK-NEXT: vsetvli a0, a2, e16,m4,ta,mu
|
||||
; CHECK-NEXT: vfwnmacc.vv v16, v8, v28, v0.t
|
||||
; CHECK-NEXT: jalr zero, 0(ra)
|
||||
entry:
|
||||
%a = call <vscale x 16 x float> @llvm.riscv.vfwnmacc.mask.nxv16f32.nxv16f16(
|
||||
<vscale x 16 x float> %0,
|
||||
<vscale x 16 x half> %1,
|
||||
<vscale x 16 x half> %2,
|
||||
<vscale x 16 x i1> %3,
|
||||
i32 %4)
|
||||
|
||||
ret <vscale x 16 x float> %a
|
||||
}
|
||||
|
||||
declare <vscale x 1 x float> @llvm.riscv.vfwnmacc.nxv1f32.f16(
|
||||
<vscale x 1 x float>,
|
||||
half,
|
||||
<vscale x 1 x half>,
|
||||
i32);
|
||||
|
||||
define <vscale x 1 x float> @intrinsic_vfwnmacc_vf_nxv1f32_f16_nxv1f16(<vscale x 1 x float> %0, half %1, <vscale x 1 x half> %2, i32 %3) nounwind {
|
||||
; CHECK-LABEL: intrinsic_vfwnmacc_vf_nxv1f32_f16_nxv1f16:
|
||||
; CHECK: # %bb.0: # %entry
|
||||
; CHECK-NEXT: fmv.h.x ft0, a0
|
||||
; CHECK-NEXT: vsetvli a0, a1, e16,mf4,ta,mu
|
||||
; CHECK-NEXT: vfwnmacc.vf v16, ft0, v17
|
||||
; CHECK-NEXT: jalr zero, 0(ra)
|
||||
entry:
|
||||
%a = call <vscale x 1 x float> @llvm.riscv.vfwnmacc.nxv1f32.f16(
|
||||
<vscale x 1 x float> %0,
|
||||
half %1,
|
||||
<vscale x 1 x half> %2,
|
||||
i32 %3)
|
||||
|
||||
ret <vscale x 1 x float> %a
|
||||
}
|
||||
|
||||
declare <vscale x 1 x float> @llvm.riscv.vfwnmacc.mask.nxv1f32.f16(
|
||||
<vscale x 1 x float>,
|
||||
half,
|
||||
<vscale x 1 x half>,
|
||||
<vscale x 1 x i1>,
|
||||
i32);
|
||||
|
||||
define <vscale x 1 x float> @intrinsic_vfwnmacc_mask_vf_nxv1f32_f16_nxv1f16(<vscale x 1 x float> %0, half %1, <vscale x 1 x half> %2, <vscale x 1 x i1> %3, i32 %4) nounwind {
|
||||
; CHECK-LABEL: intrinsic_vfwnmacc_mask_vf_nxv1f32_f16_nxv1f16:
|
||||
; CHECK: # %bb.0: # %entry
|
||||
; CHECK-NEXT: fmv.h.x ft0, a0
|
||||
; CHECK-NEXT: vsetvli a0, a1, e16,mf4,ta,mu
|
||||
; CHECK-NEXT: vfwnmacc.vf v16, ft0, v17, v0.t
|
||||
; CHECK-NEXT: jalr zero, 0(ra)
|
||||
entry:
|
||||
%a = call <vscale x 1 x float> @llvm.riscv.vfwnmacc.mask.nxv1f32.f16(
|
||||
<vscale x 1 x float> %0,
|
||||
half %1,
|
||||
<vscale x 1 x half> %2,
|
||||
<vscale x 1 x i1> %3,
|
||||
i32 %4)
|
||||
|
||||
ret <vscale x 1 x float> %a
|
||||
}
|
||||
|
||||
declare <vscale x 2 x float> @llvm.riscv.vfwnmacc.nxv2f32.f16(
|
||||
<vscale x 2 x float>,
|
||||
half,
|
||||
<vscale x 2 x half>,
|
||||
i32);
|
||||
|
||||
define <vscale x 2 x float> @intrinsic_vfwnmacc_vf_nxv2f32_f16_nxv2f16(<vscale x 2 x float> %0, half %1, <vscale x 2 x half> %2, i32 %3) nounwind {
|
||||
; CHECK-LABEL: intrinsic_vfwnmacc_vf_nxv2f32_f16_nxv2f16:
|
||||
; CHECK: # %bb.0: # %entry
|
||||
; CHECK-NEXT: fmv.h.x ft0, a0
|
||||
; CHECK-NEXT: vsetvli a0, a1, e16,mf2,ta,mu
|
||||
; CHECK-NEXT: vfwnmacc.vf v16, ft0, v17
|
||||
; CHECK-NEXT: jalr zero, 0(ra)
|
||||
entry:
|
||||
%a = call <vscale x 2 x float> @llvm.riscv.vfwnmacc.nxv2f32.f16(
|
||||
<vscale x 2 x float> %0,
|
||||
half %1,
|
||||
<vscale x 2 x half> %2,
|
||||
i32 %3)
|
||||
|
||||
ret <vscale x 2 x float> %a
|
||||
}
|
||||
|
||||
declare <vscale x 2 x float> @llvm.riscv.vfwnmacc.mask.nxv2f32.f16(
|
||||
<vscale x 2 x float>,
|
||||
half,
|
||||
<vscale x 2 x half>,
|
||||
<vscale x 2 x i1>,
|
||||
i32);
|
||||
|
||||
define <vscale x 2 x float> @intrinsic_vfwnmacc_mask_vf_nxv2f32_f16_nxv2f16(<vscale x 2 x float> %0, half %1, <vscale x 2 x half> %2, <vscale x 2 x i1> %3, i32 %4) nounwind {
|
||||
; CHECK-LABEL: intrinsic_vfwnmacc_mask_vf_nxv2f32_f16_nxv2f16:
|
||||
; CHECK: # %bb.0: # %entry
|
||||
; CHECK-NEXT: fmv.h.x ft0, a0
|
||||
; CHECK-NEXT: vsetvli a0, a1, e16,mf2,ta,mu
|
||||
; CHECK-NEXT: vfwnmacc.vf v16, ft0, v17, v0.t
|
||||
; CHECK-NEXT: jalr zero, 0(ra)
|
||||
entry:
|
||||
%a = call <vscale x 2 x float> @llvm.riscv.vfwnmacc.mask.nxv2f32.f16(
|
||||
<vscale x 2 x float> %0,
|
||||
half %1,
|
||||
<vscale x 2 x half> %2,
|
||||
<vscale x 2 x i1> %3,
|
||||
i32 %4)
|
||||
|
||||
ret <vscale x 2 x float> %a
|
||||
}
|
||||
|
||||
declare <vscale x 4 x float> @llvm.riscv.vfwnmacc.nxv4f32.f16(
|
||||
<vscale x 4 x float>,
|
||||
half,
|
||||
<vscale x 4 x half>,
|
||||
i32);
|
||||
|
||||
define <vscale x 4 x float> @intrinsic_vfwnmacc_vf_nxv4f32_f16_nxv4f16(<vscale x 4 x float> %0, half %1, <vscale x 4 x half> %2, i32 %3) nounwind {
|
||||
; CHECK-LABEL: intrinsic_vfwnmacc_vf_nxv4f32_f16_nxv4f16:
|
||||
; CHECK: # %bb.0: # %entry
|
||||
; CHECK-NEXT: fmv.h.x ft0, a0
|
||||
; CHECK-NEXT: vsetvli a0, a1, e16,m1,ta,mu
|
||||
; CHECK-NEXT: vfwnmacc.vf v16, ft0, v18
|
||||
; CHECK-NEXT: jalr zero, 0(ra)
|
||||
entry:
|
||||
%a = call <vscale x 4 x float> @llvm.riscv.vfwnmacc.nxv4f32.f16(
|
||||
<vscale x 4 x float> %0,
|
||||
half %1,
|
||||
<vscale x 4 x half> %2,
|
||||
i32 %3)
|
||||
|
||||
ret <vscale x 4 x float> %a
|
||||
}
|
||||
|
||||
declare <vscale x 4 x float> @llvm.riscv.vfwnmacc.mask.nxv4f32.f16(
|
||||
<vscale x 4 x float>,
|
||||
half,
|
||||
<vscale x 4 x half>,
|
||||
<vscale x 4 x i1>,
|
||||
i32);
|
||||
|
||||
define <vscale x 4 x float> @intrinsic_vfwnmacc_mask_vf_nxv4f32_f16_nxv4f16(<vscale x 4 x float> %0, half %1, <vscale x 4 x half> %2, <vscale x 4 x i1> %3, i32 %4) nounwind {
|
||||
; CHECK-LABEL: intrinsic_vfwnmacc_mask_vf_nxv4f32_f16_nxv4f16:
|
||||
; CHECK: # %bb.0: # %entry
|
||||
; CHECK-NEXT: fmv.h.x ft0, a0
|
||||
; CHECK-NEXT: vsetvli a0, a1, e16,m1,ta,mu
|
||||
; CHECK-NEXT: vfwnmacc.vf v16, ft0, v18, v0.t
|
||||
; CHECK-NEXT: jalr zero, 0(ra)
|
||||
entry:
|
||||
%a = call <vscale x 4 x float> @llvm.riscv.vfwnmacc.mask.nxv4f32.f16(
|
||||
<vscale x 4 x float> %0,
|
||||
half %1,
|
||||
<vscale x 4 x half> %2,
|
||||
<vscale x 4 x i1> %3,
|
||||
i32 %4)
|
||||
|
||||
ret <vscale x 4 x float> %a
|
||||
}
|
||||
|
||||
declare <vscale x 8 x float> @llvm.riscv.vfwnmacc.nxv8f32.f16(
|
||||
<vscale x 8 x float>,
|
||||
half,
|
||||
<vscale x 8 x half>,
|
||||
i32);
|
||||
|
||||
define <vscale x 8 x float> @intrinsic_vfwnmacc_vf_nxv8f32_f16_nxv8f16(<vscale x 8 x float> %0, half %1, <vscale x 8 x half> %2, i32 %3) nounwind {
|
||||
; CHECK-LABEL: intrinsic_vfwnmacc_vf_nxv8f32_f16_nxv8f16:
|
||||
; CHECK: # %bb.0: # %entry
|
||||
; CHECK-NEXT: fmv.h.x ft0, a0
|
||||
; CHECK-NEXT: vsetvli a0, a1, e16,m2,ta,mu
|
||||
; CHECK-NEXT: vfwnmacc.vf v16, ft0, v20
|
||||
; CHECK-NEXT: jalr zero, 0(ra)
|
||||
entry:
|
||||
%a = call <vscale x 8 x float> @llvm.riscv.vfwnmacc.nxv8f32.f16(
|
||||
<vscale x 8 x float> %0,
|
||||
half %1,
|
||||
<vscale x 8 x half> %2,
|
||||
i32 %3)
|
||||
|
||||
ret <vscale x 8 x float> %a
|
||||
}
|
||||
|
||||
declare <vscale x 8 x float> @llvm.riscv.vfwnmacc.mask.nxv8f32.f16(
|
||||
<vscale x 8 x float>,
|
||||
half,
|
||||
<vscale x 8 x half>,
|
||||
<vscale x 8 x i1>,
|
||||
i32);
|
||||
|
||||
define <vscale x 8 x float> @intrinsic_vfwnmacc_mask_vf_nxv8f32_f16_nxv8f16(<vscale x 8 x float> %0, half %1, <vscale x 8 x half> %2, <vscale x 8 x i1> %3, i32 %4) nounwind {
|
||||
; CHECK-LABEL: intrinsic_vfwnmacc_mask_vf_nxv8f32_f16_nxv8f16:
|
||||
; CHECK: # %bb.0: # %entry
|
||||
; CHECK-NEXT: fmv.h.x ft0, a0
|
||||
; CHECK-NEXT: vsetvli a0, a1, e16,m2,ta,mu
|
||||
; CHECK-NEXT: vfwnmacc.vf v16, ft0, v20, v0.t
|
||||
; CHECK-NEXT: jalr zero, 0(ra)
|
||||
entry:
|
||||
%a = call <vscale x 8 x float> @llvm.riscv.vfwnmacc.mask.nxv8f32.f16(
|
||||
<vscale x 8 x float> %0,
|
||||
half %1,
|
||||
<vscale x 8 x half> %2,
|
||||
<vscale x 8 x i1> %3,
|
||||
i32 %4)
|
||||
|
||||
ret <vscale x 8 x float> %a
|
||||
}
|
||||
|
||||
declare <vscale x 16 x float> @llvm.riscv.vfwnmacc.nxv16f32.f16(
|
||||
<vscale x 16 x float>,
|
||||
half,
|
||||
<vscale x 16 x half>,
|
||||
i32);
|
||||
|
||||
define <vscale x 16 x float> @intrinsic_vfwnmacc_vf_nxv16f32_f16_nxv16f16(<vscale x 16 x float> %0, half %1, <vscale x 16 x half> %2, i32 %3) nounwind {
|
||||
; CHECK-LABEL: intrinsic_vfwnmacc_vf_nxv16f32_f16_nxv16f16:
|
||||
; CHECK: # %bb.0: # %entry
|
||||
; CHECK-NEXT: vsetvli a3, zero, e16,m4,ta,mu
|
||||
; CHECK-NEXT: vle16.v v28, (a1)
|
||||
; CHECK-NEXT: fmv.h.x ft0, a0
|
||||
; CHECK-NEXT: vsetvli a0, a2, e16,m4,ta,mu
|
||||
; CHECK-NEXT: vfwnmacc.vf v16, ft0, v28
|
||||
; CHECK-NEXT: jalr zero, 0(ra)
|
||||
entry:
|
||||
%a = call <vscale x 16 x float> @llvm.riscv.vfwnmacc.nxv16f32.f16(
|
||||
<vscale x 16 x float> %0,
|
||||
half %1,
|
||||
<vscale x 16 x half> %2,
|
||||
i32 %3)
|
||||
|
||||
ret <vscale x 16 x float> %a
|
||||
}
|
||||
|
||||
declare <vscale x 16 x float> @llvm.riscv.vfwnmacc.mask.nxv16f32.f16(
|
||||
<vscale x 16 x float>,
|
||||
half,
|
||||
<vscale x 16 x half>,
|
||||
<vscale x 16 x i1>,
|
||||
i32);
|
||||
|
||||
define <vscale x 16 x float> @intrinsic_vfwnmacc_mask_vf_nxv16f32_f16_nxv16f16(<vscale x 16 x float> %0, half %1, <vscale x 16 x half> %2, <vscale x 16 x i1> %3, i32 %4) nounwind {
|
||||
; CHECK-LABEL: intrinsic_vfwnmacc_mask_vf_nxv16f32_f16_nxv16f16:
|
||||
; CHECK: # %bb.0: # %entry
|
||||
; CHECK-NEXT: vsetvli a3, zero, e16,m4,ta,mu
|
||||
; CHECK-NEXT: vle16.v v28, (a1)
|
||||
; CHECK-NEXT: fmv.h.x ft0, a0
|
||||
; CHECK-NEXT: vsetvli a0, a2, e16,m4,ta,mu
|
||||
; CHECK-NEXT: vfwnmacc.vf v16, ft0, v28, v0.t
|
||||
; CHECK-NEXT: jalr zero, 0(ra)
|
||||
entry:
|
||||
%a = call <vscale x 16 x float> @llvm.riscv.vfwnmacc.mask.nxv16f32.f16(
|
||||
<vscale x 16 x float> %0,
|
||||
half %1,
|
||||
<vscale x 16 x half> %2,
|
||||
<vscale x 16 x i1> %3,
|
||||
i32 %4)
|
||||
|
||||
ret <vscale x 16 x float> %a
|
||||
}
|
||||
868
test/CodeGen/RISCV/rvv/vfwnmacc-rv64.ll
Normal file
868
test/CodeGen/RISCV/rvv/vfwnmacc-rv64.ll
Normal file
@ -0,0 +1,868 @@
|
||||
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
|
||||
; RUN: llc -mtriple=riscv64 -mattr=+experimental-v,+d,+experimental-zfh -verify-machineinstrs \
|
||||
; RUN: --riscv-no-aliases < %s | FileCheck %s
|
||||
declare <vscale x 1 x float> @llvm.riscv.vfwnmacc.nxv1f32.nxv1f16(
|
||||
<vscale x 1 x float>,
|
||||
<vscale x 1 x half>,
|
||||
<vscale x 1 x half>,
|
||||
i64);
|
||||
|
||||
define <vscale x 1 x float> @intrinsic_vfwnmacc_vv_nxv1f32_nxv1f16_nxv1f16(<vscale x 1 x float> %0, <vscale x 1 x half> %1, <vscale x 1 x half> %2, i64 %3) nounwind {
|
||||
; CHECK-LABEL: intrinsic_vfwnmacc_vv_nxv1f32_nxv1f16_nxv1f16:
|
||||
; CHECK: # %bb.0: # %entry
|
||||
; CHECK-NEXT: vsetvli a0, a0, e16,mf4,ta,mu
|
||||
; CHECK-NEXT: vfwnmacc.vv v16, v17, v18
|
||||
; CHECK-NEXT: jalr zero, 0(ra)
|
||||
entry:
|
||||
%a = call <vscale x 1 x float> @llvm.riscv.vfwnmacc.nxv1f32.nxv1f16(
|
||||
<vscale x 1 x float> %0,
|
||||
<vscale x 1 x half> %1,
|
||||
<vscale x 1 x half> %2,
|
||||
i64 %3)
|
||||
|
||||
ret <vscale x 1 x float> %a
|
||||
}
|
||||
|
||||
declare <vscale x 1 x float> @llvm.riscv.vfwnmacc.mask.nxv1f32.nxv1f16(
|
||||
<vscale x 1 x float>,
|
||||
<vscale x 1 x half>,
|
||||
<vscale x 1 x half>,
|
||||
<vscale x 1 x i1>,
|
||||
i64);
|
||||
|
||||
define <vscale x 1 x float> @intrinsic_vfwnmacc_mask_vv_nxv1f32_nxv1f16_nxv1f16(<vscale x 1 x float> %0, <vscale x 1 x half> %1, <vscale x 1 x half> %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
|
||||
; CHECK-LABEL: intrinsic_vfwnmacc_mask_vv_nxv1f32_nxv1f16_nxv1f16:
|
||||
; CHECK: # %bb.0: # %entry
|
||||
; CHECK-NEXT: vsetvli a0, a0, e16,mf4,ta,mu
|
||||
; CHECK-NEXT: vfwnmacc.vv v16, v17, v18, v0.t
|
||||
; CHECK-NEXT: jalr zero, 0(ra)
|
||||
entry:
|
||||
%a = call <vscale x 1 x float> @llvm.riscv.vfwnmacc.mask.nxv1f32.nxv1f16(
|
||||
<vscale x 1 x float> %0,
|
||||
<vscale x 1 x half> %1,
|
||||
<vscale x 1 x half> %2,
|
||||
<vscale x 1 x i1> %3,
|
||||
i64 %4)
|
||||
|
||||
ret <vscale x 1 x float> %a
|
||||
}
|
||||
|
||||
declare <vscale x 2 x float> @llvm.riscv.vfwnmacc.nxv2f32.nxv2f16(
|
||||
<vscale x 2 x float>,
|
||||
<vscale x 2 x half>,
|
||||
<vscale x 2 x half>,
|
||||
i64);
|
||||
|
||||
define <vscale x 2 x float> @intrinsic_vfwnmacc_vv_nxv2f32_nxv2f16_nxv2f16(<vscale x 2 x float> %0, <vscale x 2 x half> %1, <vscale x 2 x half> %2, i64 %3) nounwind {
|
||||
; CHECK-LABEL: intrinsic_vfwnmacc_vv_nxv2f32_nxv2f16_nxv2f16:
|
||||
; CHECK: # %bb.0: # %entry
|
||||
; CHECK-NEXT: vsetvli a0, a0, e16,mf2,ta,mu
|
||||
; CHECK-NEXT: vfwnmacc.vv v16, v17, v18
|
||||
; CHECK-NEXT: jalr zero, 0(ra)
|
||||
entry:
|
||||
%a = call <vscale x 2 x float> @llvm.riscv.vfwnmacc.nxv2f32.nxv2f16(
|
||||
<vscale x 2 x float> %0,
|
||||
<vscale x 2 x half> %1,
|
||||
<vscale x 2 x half> %2,
|
||||
i64 %3)
|
||||
|
||||
ret <vscale x 2 x float> %a
|
||||
}
|
||||
|
||||
declare <vscale x 2 x float> @llvm.riscv.vfwnmacc.mask.nxv2f32.nxv2f16(
|
||||
<vscale x 2 x float>,
|
||||
<vscale x 2 x half>,
|
||||
<vscale x 2 x half>,
|
||||
<vscale x 2 x i1>,
|
||||
i64);
|
||||
|
||||
define <vscale x 2 x float> @intrinsic_vfwnmacc_mask_vv_nxv2f32_nxv2f16_nxv2f16(<vscale x 2 x float> %0, <vscale x 2 x half> %1, <vscale x 2 x half> %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
|
||||
; CHECK-LABEL: intrinsic_vfwnmacc_mask_vv_nxv2f32_nxv2f16_nxv2f16:
|
||||
; CHECK: # %bb.0: # %entry
|
||||
; CHECK-NEXT: vsetvli a0, a0, e16,mf2,ta,mu
|
||||
; CHECK-NEXT: vfwnmacc.vv v16, v17, v18, v0.t
|
||||
; CHECK-NEXT: jalr zero, 0(ra)
|
||||
entry:
|
||||
%a = call <vscale x 2 x float> @llvm.riscv.vfwnmacc.mask.nxv2f32.nxv2f16(
|
||||
<vscale x 2 x float> %0,
|
||||
<vscale x 2 x half> %1,
|
||||
<vscale x 2 x half> %2,
|
||||
<vscale x 2 x i1> %3,
|
||||
i64 %4)
|
||||
|
||||
ret <vscale x 2 x float> %a
|
||||
}
|
||||
|
||||
declare <vscale x 4 x float> @llvm.riscv.vfwnmacc.nxv4f32.nxv4f16(
|
||||
<vscale x 4 x float>,
|
||||
<vscale x 4 x half>,
|
||||
<vscale x 4 x half>,
|
||||
i64);
|
||||
|
||||
define <vscale x 4 x float> @intrinsic_vfwnmacc_vv_nxv4f32_nxv4f16_nxv4f16(<vscale x 4 x float> %0, <vscale x 4 x half> %1, <vscale x 4 x half> %2, i64 %3) nounwind {
|
||||
; CHECK-LABEL: intrinsic_vfwnmacc_vv_nxv4f32_nxv4f16_nxv4f16:
|
||||
; CHECK: # %bb.0: # %entry
|
||||
; CHECK-NEXT: vsetvli a0, a0, e16,m1,ta,mu
|
||||
; CHECK-NEXT: vfwnmacc.vv v16, v18, v19
|
||||
; CHECK-NEXT: jalr zero, 0(ra)
|
||||
entry:
|
||||
%a = call <vscale x 4 x float> @llvm.riscv.vfwnmacc.nxv4f32.nxv4f16(
|
||||
<vscale x 4 x float> %0,
|
||||
<vscale x 4 x half> %1,
|
||||
<vscale x 4 x half> %2,
|
||||
i64 %3)
|
||||
|
||||
ret <vscale x 4 x float> %a
|
||||
}
|
||||
|
||||
declare <vscale x 4 x float> @llvm.riscv.vfwnmacc.mask.nxv4f32.nxv4f16(
|
||||
<vscale x 4 x float>,
|
||||
<vscale x 4 x half>,
|
||||
<vscale x 4 x half>,
|
||||
<vscale x 4 x i1>,
|
||||
i64);
|
||||
|
||||
define <vscale x 4 x float> @intrinsic_vfwnmacc_mask_vv_nxv4f32_nxv4f16_nxv4f16(<vscale x 4 x float> %0, <vscale x 4 x half> %1, <vscale x 4 x half> %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
|
||||
; CHECK-LABEL: intrinsic_vfwnmacc_mask_vv_nxv4f32_nxv4f16_nxv4f16:
|
||||
; CHECK: # %bb.0: # %entry
|
||||
; CHECK-NEXT: vsetvli a0, a0, e16,m1,ta,mu
|
||||
; CHECK-NEXT: vfwnmacc.vv v16, v18, v19, v0.t
|
||||
; CHECK-NEXT: jalr zero, 0(ra)
|
||||
entry:
|
||||
%a = call <vscale x 4 x float> @llvm.riscv.vfwnmacc.mask.nxv4f32.nxv4f16(
|
||||
<vscale x 4 x float> %0,
|
||||
<vscale x 4 x half> %1,
|
||||
<vscale x 4 x half> %2,
|
||||
<vscale x 4 x i1> %3,
|
||||
i64 %4)
|
||||
|
||||
ret <vscale x 4 x float> %a
|
||||
}
|
||||
|
||||
declare <vscale x 8 x float> @llvm.riscv.vfwnmacc.nxv8f32.nxv8f16(
|
||||
<vscale x 8 x float>,
|
||||
<vscale x 8 x half>,
|
||||
<vscale x 8 x half>,
|
||||
i64);
|
||||
|
||||
define <vscale x 8 x float> @intrinsic_vfwnmacc_vv_nxv8f32_nxv8f16_nxv8f16(<vscale x 8 x float> %0, <vscale x 8 x half> %1, <vscale x 8 x half> %2, i64 %3) nounwind {
|
||||
; CHECK-LABEL: intrinsic_vfwnmacc_vv_nxv8f32_nxv8f16_nxv8f16:
|
||||
; CHECK: # %bb.0: # %entry
|
||||
; CHECK-NEXT: vsetvli a0, a0, e16,m2,ta,mu
|
||||
; CHECK-NEXT: vfwnmacc.vv v16, v20, v22
|
||||
; CHECK-NEXT: jalr zero, 0(ra)
|
||||
entry:
|
||||
%a = call <vscale x 8 x float> @llvm.riscv.vfwnmacc.nxv8f32.nxv8f16(
|
||||
<vscale x 8 x float> %0,
|
||||
<vscale x 8 x half> %1,
|
||||
<vscale x 8 x half> %2,
|
||||
i64 %3)
|
||||
|
||||
ret <vscale x 8 x float> %a
|
||||
}
|
||||
|
||||
declare <vscale x 8 x float> @llvm.riscv.vfwnmacc.mask.nxv8f32.nxv8f16(
|
||||
<vscale x 8 x float>,
|
||||
<vscale x 8 x half>,
|
||||
<vscale x 8 x half>,
|
||||
<vscale x 8 x i1>,
|
||||
i64);
|
||||
|
||||
define <vscale x 8 x float> @intrinsic_vfwnmacc_mask_vv_nxv8f32_nxv8f16_nxv8f16(<vscale x 8 x float> %0, <vscale x 8 x half> %1, <vscale x 8 x half> %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
|
||||
; CHECK-LABEL: intrinsic_vfwnmacc_mask_vv_nxv8f32_nxv8f16_nxv8f16:
|
||||
; CHECK: # %bb.0: # %entry
|
||||
; CHECK-NEXT: vsetvli a0, a0, e16,m2,ta,mu
|
||||
; CHECK-NEXT: vfwnmacc.vv v16, v20, v22, v0.t
|
||||
; CHECK-NEXT: jalr zero, 0(ra)
|
||||
entry:
|
||||
%a = call <vscale x 8 x float> @llvm.riscv.vfwnmacc.mask.nxv8f32.nxv8f16(
|
||||
<vscale x 8 x float> %0,
|
||||
<vscale x 8 x half> %1,
|
||||
<vscale x 8 x half> %2,
|
||||
<vscale x 8 x i1> %3,
|
||||
i64 %4)
|
||||
|
||||
ret <vscale x 8 x float> %a
|
||||
}
|
||||
|
||||
declare <vscale x 16 x float> @llvm.riscv.vfwnmacc.nxv16f32.nxv16f16(
|
||||
<vscale x 16 x float>,
|
||||
<vscale x 16 x half>,
|
||||
<vscale x 16 x half>,
|
||||
i64);
|
||||
|
||||
define <vscale x 16 x float> @intrinsic_vfwnmacc_vv_nxv16f32_nxv16f16_nxv16f16(<vscale x 16 x float> %0, <vscale x 16 x half> %1, <vscale x 16 x half> %2, i64 %3) nounwind {
|
||||
; CHECK-LABEL: intrinsic_vfwnmacc_vv_nxv16f32_nxv16f16_nxv16f16:
|
||||
; CHECK: # %bb.0: # %entry
|
||||
; CHECK-NEXT: vsetvli a3, zero, e16,m4,ta,mu
|
||||
; CHECK-NEXT: vle16.v v28, (a1)
|
||||
; CHECK-NEXT: vle16.v v8, (a0)
|
||||
; CHECK-NEXT: vsetvli a0, a2, e16,m4,ta,mu
|
||||
; CHECK-NEXT: vfwnmacc.vv v16, v8, v28
|
||||
; CHECK-NEXT: jalr zero, 0(ra)
|
||||
entry:
|
||||
%a = call <vscale x 16 x float> @llvm.riscv.vfwnmacc.nxv16f32.nxv16f16(
|
||||
<vscale x 16 x float> %0,
|
||||
<vscale x 16 x half> %1,
|
||||
<vscale x 16 x half> %2,
|
||||
i64 %3)
|
||||
|
||||
ret <vscale x 16 x float> %a
|
||||
}
|
||||
|
||||
declare <vscale x 16 x float> @llvm.riscv.vfwnmacc.mask.nxv16f32.nxv16f16(
|
||||
<vscale x 16 x float>,
|
||||
<vscale x 16 x half>,
|
||||
<vscale x 16 x half>,
|
||||
<vscale x 16 x i1>,
|
||||
i64);
|
||||
|
||||
define <vscale x 16 x float> @intrinsic_vfwnmacc_mask_vv_nxv16f32_nxv16f16_nxv16f16(<vscale x 16 x float> %0, <vscale x 16 x half> %1, <vscale x 16 x half> %2, <vscale x 16 x i1> %3, i64 %4) nounwind {
|
||||
; CHECK-LABEL: intrinsic_vfwnmacc_mask_vv_nxv16f32_nxv16f16_nxv16f16:
|
||||
; CHECK: # %bb.0: # %entry
|
||||
; CHECK-NEXT: vsetvli a3, zero, e16,m4,ta,mu
|
||||
; CHECK-NEXT: vle16.v v28, (a1)
|
||||
; CHECK-NEXT: vle16.v v8, (a0)
|
||||
; CHECK-NEXT: vsetvli a0, a2, e16,m4,ta,mu
|
||||
; CHECK-NEXT: vfwnmacc.vv v16, v8, v28, v0.t
|
||||
; CHECK-NEXT: jalr zero, 0(ra)
|
||||
entry:
|
||||
%a = call <vscale x 16 x float> @llvm.riscv.vfwnmacc.mask.nxv16f32.nxv16f16(
|
||||
<vscale x 16 x float> %0,
|
||||
<vscale x 16 x half> %1,
|
||||
<vscale x 16 x half> %2,
|
||||
<vscale x 16 x i1> %3,
|
||||
i64 %4)
|
||||
|
||||
ret <vscale x 16 x float> %a
|
||||
}
|
||||
|
||||
declare <vscale x 1 x double> @llvm.riscv.vfwnmacc.nxv1f64.nxv1f32(
|
||||
<vscale x 1 x double>,
|
||||
<vscale x 1 x float>,
|
||||
<vscale x 1 x float>,
|
||||
i64);
|
||||
|
||||
define <vscale x 1 x double> @intrinsic_vfwnmacc_vv_nxv1f64_nxv1f32_nxv1f32(<vscale x 1 x double> %0, <vscale x 1 x float> %1, <vscale x 1 x float> %2, i64 %3) nounwind {
|
||||
; CHECK-LABEL: intrinsic_vfwnmacc_vv_nxv1f64_nxv1f32_nxv1f32:
|
||||
; CHECK: # %bb.0: # %entry
|
||||
; CHECK-NEXT: vsetvli a0, a0, e32,mf2,ta,mu
|
||||
; CHECK-NEXT: vfwnmacc.vv v16, v17, v18
|
||||
; CHECK-NEXT: jalr zero, 0(ra)
|
||||
entry:
|
||||
%a = call <vscale x 1 x double> @llvm.riscv.vfwnmacc.nxv1f64.nxv1f32(
|
||||
<vscale x 1 x double> %0,
|
||||
<vscale x 1 x float> %1,
|
||||
<vscale x 1 x float> %2,
|
||||
i64 %3)
|
||||
|
||||
ret <vscale x 1 x double> %a
|
||||
}
|
||||
|
||||
declare <vscale x 1 x double> @llvm.riscv.vfwnmacc.mask.nxv1f64.nxv1f32(
|
||||
<vscale x 1 x double>,
|
||||
<vscale x 1 x float>,
|
||||
<vscale x 1 x float>,
|
||||
<vscale x 1 x i1>,
|
||||
i64);
|
||||
|
||||
define <vscale x 1 x double> @intrinsic_vfwnmacc_mask_vv_nxv1f64_nxv1f32_nxv1f32(<vscale x 1 x double> %0, <vscale x 1 x float> %1, <vscale x 1 x float> %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
|
||||
; CHECK-LABEL: intrinsic_vfwnmacc_mask_vv_nxv1f64_nxv1f32_nxv1f32:
|
||||
; CHECK: # %bb.0: # %entry
|
||||
; CHECK-NEXT: vsetvli a0, a0, e32,mf2,ta,mu
|
||||
; CHECK-NEXT: vfwnmacc.vv v16, v17, v18, v0.t
|
||||
; CHECK-NEXT: jalr zero, 0(ra)
|
||||
entry:
|
||||
%a = call <vscale x 1 x double> @llvm.riscv.vfwnmacc.mask.nxv1f64.nxv1f32(
|
||||
<vscale x 1 x double> %0,
|
||||
<vscale x 1 x float> %1,
|
||||
<vscale x 1 x float> %2,
|
||||
<vscale x 1 x i1> %3,
|
||||
i64 %4)
|
||||
|
||||
ret <vscale x 1 x double> %a
|
||||
}
|
||||
|
||||
declare <vscale x 2 x double> @llvm.riscv.vfwnmacc.nxv2f64.nxv2f32(
|
||||
<vscale x 2 x double>,
|
||||
<vscale x 2 x float>,
|
||||
<vscale x 2 x float>,
|
||||
i64);
|
||||
|
||||
define <vscale x 2 x double> @intrinsic_vfwnmacc_vv_nxv2f64_nxv2f32_nxv2f32(<vscale x 2 x double> %0, <vscale x 2 x float> %1, <vscale x 2 x float> %2, i64 %3) nounwind {
|
||||
; CHECK-LABEL: intrinsic_vfwnmacc_vv_nxv2f64_nxv2f32_nxv2f32:
|
||||
; CHECK: # %bb.0: # %entry
|
||||
; CHECK-NEXT: vsetvli a0, a0, e32,m1,ta,mu
|
||||
; CHECK-NEXT: vfwnmacc.vv v16, v18, v19
|
||||
; CHECK-NEXT: jalr zero, 0(ra)
|
||||
entry:
|
||||
%a = call <vscale x 2 x double> @llvm.riscv.vfwnmacc.nxv2f64.nxv2f32(
|
||||
<vscale x 2 x double> %0,
|
||||
<vscale x 2 x float> %1,
|
||||
<vscale x 2 x float> %2,
|
||||
i64 %3)
|
||||
|
||||
ret <vscale x 2 x double> %a
|
||||
}
|
||||
|
||||
declare <vscale x 2 x double> @llvm.riscv.vfwnmacc.mask.nxv2f64.nxv2f32(
|
||||
<vscale x 2 x double>,
|
||||
<vscale x 2 x float>,
|
||||
<vscale x 2 x float>,
|
||||
<vscale x 2 x i1>,
|
||||
i64);
|
||||
|
||||
define <vscale x 2 x double> @intrinsic_vfwnmacc_mask_vv_nxv2f64_nxv2f32_nxv2f32(<vscale x 2 x double> %0, <vscale x 2 x float> %1, <vscale x 2 x float> %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
|
||||
; CHECK-LABEL: intrinsic_vfwnmacc_mask_vv_nxv2f64_nxv2f32_nxv2f32:
|
||||
; CHECK: # %bb.0: # %entry
|
||||
; CHECK-NEXT: vsetvli a0, a0, e32,m1,ta,mu
|
||||
; CHECK-NEXT: vfwnmacc.vv v16, v18, v19, v0.t
|
||||
; CHECK-NEXT: jalr zero, 0(ra)
|
||||
entry:
|
||||
%a = call <vscale x 2 x double> @llvm.riscv.vfwnmacc.mask.nxv2f64.nxv2f32(
|
||||
<vscale x 2 x double> %0,
|
||||
<vscale x 2 x float> %1,
|
||||
<vscale x 2 x float> %2,
|
||||
<vscale x 2 x i1> %3,
|
||||
i64 %4)
|
||||
|
||||
ret <vscale x 2 x double> %a
|
||||
}
|
||||
|
||||
declare <vscale x 4 x double> @llvm.riscv.vfwnmacc.nxv4f64.nxv4f32(
|
||||
<vscale x 4 x double>,
|
||||
<vscale x 4 x float>,
|
||||
<vscale x 4 x float>,
|
||||
i64);
|
||||
|
||||
define <vscale x 4 x double> @intrinsic_vfwnmacc_vv_nxv4f64_nxv4f32_nxv4f32(<vscale x 4 x double> %0, <vscale x 4 x float> %1, <vscale x 4 x float> %2, i64 %3) nounwind {
|
||||
; CHECK-LABEL: intrinsic_vfwnmacc_vv_nxv4f64_nxv4f32_nxv4f32:
|
||||
; CHECK: # %bb.0: # %entry
|
||||
; CHECK-NEXT: vsetvli a0, a0, e32,m2,ta,mu
|
||||
; CHECK-NEXT: vfwnmacc.vv v16, v20, v22
|
||||
; CHECK-NEXT: jalr zero, 0(ra)
|
||||
entry:
|
||||
%a = call <vscale x 4 x double> @llvm.riscv.vfwnmacc.nxv4f64.nxv4f32(
|
||||
<vscale x 4 x double> %0,
|
||||
<vscale x 4 x float> %1,
|
||||
<vscale x 4 x float> %2,
|
||||
i64 %3)
|
||||
|
||||
ret <vscale x 4 x double> %a
|
||||
}
|
||||
|
||||
declare <vscale x 4 x double> @llvm.riscv.vfwnmacc.mask.nxv4f64.nxv4f32(
|
||||
<vscale x 4 x double>,
|
||||
<vscale x 4 x float>,
|
||||
<vscale x 4 x float>,
|
||||
<vscale x 4 x i1>,
|
||||
i64);
|
||||
|
||||
define <vscale x 4 x double> @intrinsic_vfwnmacc_mask_vv_nxv4f64_nxv4f32_nxv4f32(<vscale x 4 x double> %0, <vscale x 4 x float> %1, <vscale x 4 x float> %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
|
||||
; CHECK-LABEL: intrinsic_vfwnmacc_mask_vv_nxv4f64_nxv4f32_nxv4f32:
|
||||
; CHECK: # %bb.0: # %entry
|
||||
; CHECK-NEXT: vsetvli a0, a0, e32,m2,ta,mu
|
||||
; CHECK-NEXT: vfwnmacc.vv v16, v20, v22, v0.t
|
||||
; CHECK-NEXT: jalr zero, 0(ra)
|
||||
entry:
|
||||
%a = call <vscale x 4 x double> @llvm.riscv.vfwnmacc.mask.nxv4f64.nxv4f32(
|
||||
<vscale x 4 x double> %0,
|
||||
<vscale x 4 x float> %1,
|
||||
<vscale x 4 x float> %2,
|
||||
<vscale x 4 x i1> %3,
|
||||
i64 %4)
|
||||
|
||||
ret <vscale x 4 x double> %a
|
||||
}
|
||||
|
||||
declare <vscale x 8 x double> @llvm.riscv.vfwnmacc.nxv8f64.nxv8f32(
|
||||
<vscale x 8 x double>,
|
||||
<vscale x 8 x float>,
|
||||
<vscale x 8 x float>,
|
||||
i64);
|
||||
|
||||
define <vscale x 8 x double> @intrinsic_vfwnmacc_vv_nxv8f64_nxv8f32_nxv8f32(<vscale x 8 x double> %0, <vscale x 8 x float> %1, <vscale x 8 x float> %2, i64 %3) nounwind {
|
||||
; CHECK-LABEL: intrinsic_vfwnmacc_vv_nxv8f64_nxv8f32_nxv8f32:
|
||||
; CHECK: # %bb.0: # %entry
|
||||
; CHECK-NEXT: vsetvli a3, zero, e32,m4,ta,mu
|
||||
; CHECK-NEXT: vle32.v v28, (a1)
|
||||
; CHECK-NEXT: vle32.v v8, (a0)
|
||||
; CHECK-NEXT: vsetvli a0, a2, e32,m4,ta,mu
|
||||
; CHECK-NEXT: vfwnmacc.vv v16, v8, v28
|
||||
; CHECK-NEXT: jalr zero, 0(ra)
|
||||
entry:
|
||||
%a = call <vscale x 8 x double> @llvm.riscv.vfwnmacc.nxv8f64.nxv8f32(
|
||||
<vscale x 8 x double> %0,
|
||||
<vscale x 8 x float> %1,
|
||||
<vscale x 8 x float> %2,
|
||||
i64 %3)
|
||||
|
||||
ret <vscale x 8 x double> %a
|
||||
}
|
||||
|
||||
declare <vscale x 8 x double> @llvm.riscv.vfwnmacc.mask.nxv8f64.nxv8f32(
|
||||
<vscale x 8 x double>,
|
||||
<vscale x 8 x float>,
|
||||
<vscale x 8 x float>,
|
||||
<vscale x 8 x i1>,
|
||||
i64);
|
||||
|
||||
define <vscale x 8 x double> @intrinsic_vfwnmacc_mask_vv_nxv8f64_nxv8f32_nxv8f32(<vscale x 8 x double> %0, <vscale x 8 x float> %1, <vscale x 8 x float> %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
|
||||
; CHECK-LABEL: intrinsic_vfwnmacc_mask_vv_nxv8f64_nxv8f32_nxv8f32:
|
||||
; CHECK: # %bb.0: # %entry
|
||||
; CHECK-NEXT: vsetvli a3, zero, e32,m4,ta,mu
|
||||
; CHECK-NEXT: vle32.v v28, (a1)
|
||||
; CHECK-NEXT: vle32.v v8, (a0)
|
||||
; CHECK-NEXT: vsetvli a0, a2, e32,m4,ta,mu
|
||||
; CHECK-NEXT: vfwnmacc.vv v16, v8, v28, v0.t
|
||||
; CHECK-NEXT: jalr zero, 0(ra)
|
||||
entry:
|
||||
%a = call <vscale x 8 x double> @llvm.riscv.vfwnmacc.mask.nxv8f64.nxv8f32(
|
||||
<vscale x 8 x double> %0,
|
||||
<vscale x 8 x float> %1,
|
||||
<vscale x 8 x float> %2,
|
||||
<vscale x 8 x i1> %3,
|
||||
i64 %4)
|
||||
|
||||
ret <vscale x 8 x double> %a
|
||||
}
|
||||
|
||||
declare <vscale x 1 x float> @llvm.riscv.vfwnmacc.nxv1f32.f16(
|
||||
<vscale x 1 x float>,
|
||||
half,
|
||||
<vscale x 1 x half>,
|
||||
i64);
|
||||
|
||||
define <vscale x 1 x float> @intrinsic_vfwnmacc_vf_nxv1f32_f16_nxv1f16(<vscale x 1 x float> %0, half %1, <vscale x 1 x half> %2, i64 %3) nounwind {
|
||||
; CHECK-LABEL: intrinsic_vfwnmacc_vf_nxv1f32_f16_nxv1f16:
|
||||
; CHECK: # %bb.0: # %entry
|
||||
; CHECK-NEXT: fmv.h.x ft0, a0
|
||||
; CHECK-NEXT: vsetvli a0, a1, e16,mf4,ta,mu
|
||||
; CHECK-NEXT: vfwnmacc.vf v16, ft0, v17
|
||||
; CHECK-NEXT: jalr zero, 0(ra)
|
||||
entry:
|
||||
%a = call <vscale x 1 x float> @llvm.riscv.vfwnmacc.nxv1f32.f16(
|
||||
<vscale x 1 x float> %0,
|
||||
half %1,
|
||||
<vscale x 1 x half> %2,
|
||||
i64 %3)
|
||||
|
||||
ret <vscale x 1 x float> %a
|
||||
}
|
||||
|
||||
declare <vscale x 1 x float> @llvm.riscv.vfwnmacc.mask.nxv1f32.f16(
|
||||
<vscale x 1 x float>,
|
||||
half,
|
||||
<vscale x 1 x half>,
|
||||
<vscale x 1 x i1>,
|
||||
i64);
|
||||
|
||||
define <vscale x 1 x float> @intrinsic_vfwnmacc_mask_vf_nxv1f32_f16_nxv1f16(<vscale x 1 x float> %0, half %1, <vscale x 1 x half> %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
|
||||
; CHECK-LABEL: intrinsic_vfwnmacc_mask_vf_nxv1f32_f16_nxv1f16:
|
||||
; CHECK: # %bb.0: # %entry
|
||||
; CHECK-NEXT: fmv.h.x ft0, a0
|
||||
; CHECK-NEXT: vsetvli a0, a1, e16,mf4,ta,mu
|
||||
; CHECK-NEXT: vfwnmacc.vf v16, ft0, v17, v0.t
|
||||
; CHECK-NEXT: jalr zero, 0(ra)
|
||||
entry:
|
||||
%a = call <vscale x 1 x float> @llvm.riscv.vfwnmacc.mask.nxv1f32.f16(
|
||||
<vscale x 1 x float> %0,
|
||||
half %1,
|
||||
<vscale x 1 x half> %2,
|
||||
<vscale x 1 x i1> %3,
|
||||
i64 %4)
|
||||
|
||||
ret <vscale x 1 x float> %a
|
||||
}
|
||||
|
||||
declare <vscale x 2 x float> @llvm.riscv.vfwnmacc.nxv2f32.f16(
|
||||
<vscale x 2 x float>,
|
||||
half,
|
||||
<vscale x 2 x half>,
|
||||
i64);
|
||||
|
||||
define <vscale x 2 x float> @intrinsic_vfwnmacc_vf_nxv2f32_f16_nxv2f16(<vscale x 2 x float> %0, half %1, <vscale x 2 x half> %2, i64 %3) nounwind {
|
||||
; CHECK-LABEL: intrinsic_vfwnmacc_vf_nxv2f32_f16_nxv2f16:
|
||||
; CHECK: # %bb.0: # %entry
|
||||
; CHECK-NEXT: fmv.h.x ft0, a0
|
||||
; CHECK-NEXT: vsetvli a0, a1, e16,mf2,ta,mu
|
||||
; CHECK-NEXT: vfwnmacc.vf v16, ft0, v17
|
||||
; CHECK-NEXT: jalr zero, 0(ra)
|
||||
entry:
|
||||
%a = call <vscale x 2 x float> @llvm.riscv.vfwnmacc.nxv2f32.f16(
|
||||
<vscale x 2 x float> %0,
|
||||
half %1,
|
||||
<vscale x 2 x half> %2,
|
||||
i64 %3)
|
||||
|
||||
ret <vscale x 2 x float> %a
|
||||
}
|
||||
|
||||
declare <vscale x 2 x float> @llvm.riscv.vfwnmacc.mask.nxv2f32.f16(
|
||||
<vscale x 2 x float>,
|
||||
half,
|
||||
<vscale x 2 x half>,
|
||||
<vscale x 2 x i1>,
|
||||
i64);
|
||||
|
||||
define <vscale x 2 x float> @intrinsic_vfwnmacc_mask_vf_nxv2f32_f16_nxv2f16(<vscale x 2 x float> %0, half %1, <vscale x 2 x half> %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
|
||||
; CHECK-LABEL: intrinsic_vfwnmacc_mask_vf_nxv2f32_f16_nxv2f16:
|
||||
; CHECK: # %bb.0: # %entry
|
||||
; CHECK-NEXT: fmv.h.x ft0, a0
|
||||
; CHECK-NEXT: vsetvli a0, a1, e16,mf2,ta,mu
|
||||
; CHECK-NEXT: vfwnmacc.vf v16, ft0, v17, v0.t
|
||||
; CHECK-NEXT: jalr zero, 0(ra)
|
||||
entry:
|
||||
%a = call <vscale x 2 x float> @llvm.riscv.vfwnmacc.mask.nxv2f32.f16(
|
||||
<vscale x 2 x float> %0,
|
||||
half %1,
|
||||
<vscale x 2 x half> %2,
|
||||
<vscale x 2 x i1> %3,
|
||||
i64 %4)
|
||||
|
||||
ret <vscale x 2 x float> %a
|
||||
}
|
||||
|
||||
declare <vscale x 4 x float> @llvm.riscv.vfwnmacc.nxv4f32.f16(
|
||||
<vscale x 4 x float>,
|
||||
half,
|
||||
<vscale x 4 x half>,
|
||||
i64);
|
||||
|
||||
define <vscale x 4 x float> @intrinsic_vfwnmacc_vf_nxv4f32_f16_nxv4f16(<vscale x 4 x float> %0, half %1, <vscale x 4 x half> %2, i64 %3) nounwind {
|
||||
; CHECK-LABEL: intrinsic_vfwnmacc_vf_nxv4f32_f16_nxv4f16:
|
||||
; CHECK: # %bb.0: # %entry
|
||||
; CHECK-NEXT: fmv.h.x ft0, a0
|
||||
; CHECK-NEXT: vsetvli a0, a1, e16,m1,ta,mu
|
||||
; CHECK-NEXT: vfwnmacc.vf v16, ft0, v18
|
||||
; CHECK-NEXT: jalr zero, 0(ra)
|
||||
entry:
|
||||
%a = call <vscale x 4 x float> @llvm.riscv.vfwnmacc.nxv4f32.f16(
|
||||
<vscale x 4 x float> %0,
|
||||
half %1,
|
||||
<vscale x 4 x half> %2,
|
||||
i64 %3)
|
||||
|
||||
ret <vscale x 4 x float> %a
|
||||
}
|
||||
|
||||
declare <vscale x 4 x float> @llvm.riscv.vfwnmacc.mask.nxv4f32.f16(
|
||||
<vscale x 4 x float>,
|
||||
half,
|
||||
<vscale x 4 x half>,
|
||||
<vscale x 4 x i1>,
|
||||
i64);
|
||||
|
||||
define <vscale x 4 x float> @intrinsic_vfwnmacc_mask_vf_nxv4f32_f16_nxv4f16(<vscale x 4 x float> %0, half %1, <vscale x 4 x half> %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
|
||||
; CHECK-LABEL: intrinsic_vfwnmacc_mask_vf_nxv4f32_f16_nxv4f16:
|
||||
; CHECK: # %bb.0: # %entry
|
||||
; CHECK-NEXT: fmv.h.x ft0, a0
|
||||
; CHECK-NEXT: vsetvli a0, a1, e16,m1,ta,mu
|
||||
; CHECK-NEXT: vfwnmacc.vf v16, ft0, v18, v0.t
|
||||
; CHECK-NEXT: jalr zero, 0(ra)
|
||||
entry:
|
||||
%a = call <vscale x 4 x float> @llvm.riscv.vfwnmacc.mask.nxv4f32.f16(
|
||||
<vscale x 4 x float> %0,
|
||||
half %1,
|
||||
<vscale x 4 x half> %2,
|
||||
<vscale x 4 x i1> %3,
|
||||
i64 %4)
|
||||
|
||||
ret <vscale x 4 x float> %a
|
||||
}
|
||||
|
||||
declare <vscale x 8 x float> @llvm.riscv.vfwnmacc.nxv8f32.f16(
|
||||
<vscale x 8 x float>,
|
||||
half,
|
||||
<vscale x 8 x half>,
|
||||
i64);
|
||||
|
||||
define <vscale x 8 x float> @intrinsic_vfwnmacc_vf_nxv8f32_f16_nxv8f16(<vscale x 8 x float> %0, half %1, <vscale x 8 x half> %2, i64 %3) nounwind {
|
||||
; CHECK-LABEL: intrinsic_vfwnmacc_vf_nxv8f32_f16_nxv8f16:
|
||||
; CHECK: # %bb.0: # %entry
|
||||
; CHECK-NEXT: fmv.h.x ft0, a0
|
||||
; CHECK-NEXT: vsetvli a0, a1, e16,m2,ta,mu
|
||||
; CHECK-NEXT: vfwnmacc.vf v16, ft0, v20
|
||||
; CHECK-NEXT: jalr zero, 0(ra)
|
||||
entry:
|
||||
%a = call <vscale x 8 x float> @llvm.riscv.vfwnmacc.nxv8f32.f16(
|
||||
<vscale x 8 x float> %0,
|
||||
half %1,
|
||||
<vscale x 8 x half> %2,
|
||||
i64 %3)
|
||||
|
||||
ret <vscale x 8 x float> %a
|
||||
}
|
||||
|
||||
declare <vscale x 8 x float> @llvm.riscv.vfwnmacc.mask.nxv8f32.f16(
|
||||
<vscale x 8 x float>,
|
||||
half,
|
||||
<vscale x 8 x half>,
|
||||
<vscale x 8 x i1>,
|
||||
i64);
|
||||
|
||||
define <vscale x 8 x float> @intrinsic_vfwnmacc_mask_vf_nxv8f32_f16_nxv8f16(<vscale x 8 x float> %0, half %1, <vscale x 8 x half> %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
|
||||
; CHECK-LABEL: intrinsic_vfwnmacc_mask_vf_nxv8f32_f16_nxv8f16:
|
||||
; CHECK: # %bb.0: # %entry
|
||||
; CHECK-NEXT: fmv.h.x ft0, a0
|
||||
; CHECK-NEXT: vsetvli a0, a1, e16,m2,ta,mu
|
||||
; CHECK-NEXT: vfwnmacc.vf v16, ft0, v20, v0.t
|
||||
; CHECK-NEXT: jalr zero, 0(ra)
|
||||
entry:
|
||||
%a = call <vscale x 8 x float> @llvm.riscv.vfwnmacc.mask.nxv8f32.f16(
|
||||
<vscale x 8 x float> %0,
|
||||
half %1,
|
||||
<vscale x 8 x half> %2,
|
||||
<vscale x 8 x i1> %3,
|
||||
i64 %4)
|
||||
|
||||
ret <vscale x 8 x float> %a
|
||||
}
|
||||
|
||||
declare <vscale x 16 x float> @llvm.riscv.vfwnmacc.nxv16f32.f16(
|
||||
<vscale x 16 x float>,
|
||||
half,
|
||||
<vscale x 16 x half>,
|
||||
i64);
|
||||
|
||||
define <vscale x 16 x float> @intrinsic_vfwnmacc_vf_nxv16f32_f16_nxv16f16(<vscale x 16 x float> %0, half %1, <vscale x 16 x half> %2, i64 %3) nounwind {
|
||||
; CHECK-LABEL: intrinsic_vfwnmacc_vf_nxv16f32_f16_nxv16f16:
|
||||
; CHECK: # %bb.0: # %entry
|
||||
; CHECK-NEXT: vsetvli a3, zero, e16,m4,ta,mu
|
||||
; CHECK-NEXT: vle16.v v28, (a1)
|
||||
; CHECK-NEXT: fmv.h.x ft0, a0
|
||||
; CHECK-NEXT: vsetvli a0, a2, e16,m4,ta,mu
|
||||
; CHECK-NEXT: vfwnmacc.vf v16, ft0, v28
|
||||
; CHECK-NEXT: jalr zero, 0(ra)
|
||||
entry:
|
||||
%a = call <vscale x 16 x float> @llvm.riscv.vfwnmacc.nxv16f32.f16(
|
||||
<vscale x 16 x float> %0,
|
||||
half %1,
|
||||
<vscale x 16 x half> %2,
|
||||
i64 %3)
|
||||
|
||||
ret <vscale x 16 x float> %a
|
||||
}
|
||||
|
||||
declare <vscale x 16 x float> @llvm.riscv.vfwnmacc.mask.nxv16f32.f16(
|
||||
<vscale x 16 x float>,
|
||||
half,
|
||||
<vscale x 16 x half>,
|
||||
<vscale x 16 x i1>,
|
||||
i64);
|
||||
|
||||
define <vscale x 16 x float> @intrinsic_vfwnmacc_mask_vf_nxv16f32_f16_nxv16f16(<vscale x 16 x float> %0, half %1, <vscale x 16 x half> %2, <vscale x 16 x i1> %3, i64 %4) nounwind {
|
||||
; CHECK-LABEL: intrinsic_vfwnmacc_mask_vf_nxv16f32_f16_nxv16f16:
|
||||
; CHECK: # %bb.0: # %entry
|
||||
; CHECK-NEXT: vsetvli a3, zero, e16,m4,ta,mu
|
||||
; CHECK-NEXT: vle16.v v28, (a1)
|
||||
; CHECK-NEXT: fmv.h.x ft0, a0
|
||||
; CHECK-NEXT: vsetvli a0, a2, e16,m4,ta,mu
|
||||
; CHECK-NEXT: vfwnmacc.vf v16, ft0, v28, v0.t
|
||||
; CHECK-NEXT: jalr zero, 0(ra)
|
||||
entry:
|
||||
%a = call <vscale x 16 x float> @llvm.riscv.vfwnmacc.mask.nxv16f32.f16(
|
||||
<vscale x 16 x float> %0,
|
||||
half %1,
|
||||
<vscale x 16 x half> %2,
|
||||
<vscale x 16 x i1> %3,
|
||||
i64 %4)
|
||||
|
||||
ret <vscale x 16 x float> %a
|
||||
}
|
||||
|
||||
declare <vscale x 1 x double> @llvm.riscv.vfwnmacc.nxv1f64.f32(
|
||||
<vscale x 1 x double>,
|
||||
float,
|
||||
<vscale x 1 x float>,
|
||||
i64);
|
||||
|
||||
define <vscale x 1 x double> @intrinsic_vfwnmacc_vf_nxv1f64_f32_nxv1f32(<vscale x 1 x double> %0, float %1, <vscale x 1 x float> %2, i64 %3) nounwind {
|
||||
; CHECK-LABEL: intrinsic_vfwnmacc_vf_nxv1f64_f32_nxv1f32:
|
||||
; CHECK: # %bb.0: # %entry
|
||||
; CHECK-NEXT: fmv.w.x ft0, a0
|
||||
; CHECK-NEXT: vsetvli a0, a1, e32,mf2,ta,mu
|
||||
; CHECK-NEXT: vfwnmacc.vf v16, ft0, v17
|
||||
; CHECK-NEXT: jalr zero, 0(ra)
|
||||
entry:
|
||||
%a = call <vscale x 1 x double> @llvm.riscv.vfwnmacc.nxv1f64.f32(
|
||||
<vscale x 1 x double> %0,
|
||||
float %1,
|
||||
<vscale x 1 x float> %2,
|
||||
i64 %3)
|
||||
|
||||
ret <vscale x 1 x double> %a
|
||||
}
|
||||
|
||||
declare <vscale x 1 x double> @llvm.riscv.vfwnmacc.mask.nxv1f64.f32(
|
||||
<vscale x 1 x double>,
|
||||
float,
|
||||
<vscale x 1 x float>,
|
||||
<vscale x 1 x i1>,
|
||||
i64);
|
||||
|
||||
define <vscale x 1 x double> @intrinsic_vfwnmacc_mask_vf_nxv1f64_f32_nxv1f32(<vscale x 1 x double> %0, float %1, <vscale x 1 x float> %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
|
||||
; CHECK-LABEL: intrinsic_vfwnmacc_mask_vf_nxv1f64_f32_nxv1f32:
|
||||
; CHECK: # %bb.0: # %entry
|
||||
; CHECK-NEXT: fmv.w.x ft0, a0
|
||||
; CHECK-NEXT: vsetvli a0, a1, e32,mf2,ta,mu
|
||||
; CHECK-NEXT: vfwnmacc.vf v16, ft0, v17, v0.t
|
||||
; CHECK-NEXT: jalr zero, 0(ra)
|
||||
entry:
|
||||
%a = call <vscale x 1 x double> @llvm.riscv.vfwnmacc.mask.nxv1f64.f32(
|
||||
<vscale x 1 x double> %0,
|
||||
float %1,
|
||||
<vscale x 1 x float> %2,
|
||||
<vscale x 1 x i1> %3,
|
||||
i64 %4)
|
||||
|
||||
ret <vscale x 1 x double> %a
|
||||
}
|
||||
|
||||
declare <vscale x 2 x double> @llvm.riscv.vfwnmacc.nxv2f64.f32(
|
||||
<vscale x 2 x double>,
|
||||
float,
|
||||
<vscale x 2 x float>,
|
||||
i64);
|
||||
|
||||
define <vscale x 2 x double> @intrinsic_vfwnmacc_vf_nxv2f64_f32_nxv2f32(<vscale x 2 x double> %0, float %1, <vscale x 2 x float> %2, i64 %3) nounwind {
|
||||
; CHECK-LABEL: intrinsic_vfwnmacc_vf_nxv2f64_f32_nxv2f32:
|
||||
; CHECK: # %bb.0: # %entry
|
||||
; CHECK-NEXT: fmv.w.x ft0, a0
|
||||
; CHECK-NEXT: vsetvli a0, a1, e32,m1,ta,mu
|
||||
; CHECK-NEXT: vfwnmacc.vf v16, ft0, v18
|
||||
; CHECK-NEXT: jalr zero, 0(ra)
|
||||
entry:
|
||||
%a = call <vscale x 2 x double> @llvm.riscv.vfwnmacc.nxv2f64.f32(
|
||||
<vscale x 2 x double> %0,
|
||||
float %1,
|
||||
<vscale x 2 x float> %2,
|
||||
i64 %3)
|
||||
|
||||
ret <vscale x 2 x double> %a
|
||||
}
|
||||
|
||||
declare <vscale x 2 x double> @llvm.riscv.vfwnmacc.mask.nxv2f64.f32(
|
||||
<vscale x 2 x double>,
|
||||
float,
|
||||
<vscale x 2 x float>,
|
||||
<vscale x 2 x i1>,
|
||||
i64);
|
||||
|
||||
define <vscale x 2 x double> @intrinsic_vfwnmacc_mask_vf_nxv2f64_f32_nxv2f32(<vscale x 2 x double> %0, float %1, <vscale x 2 x float> %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
|
||||
; CHECK-LABEL: intrinsic_vfwnmacc_mask_vf_nxv2f64_f32_nxv2f32:
|
||||
; CHECK: # %bb.0: # %entry
|
||||
; CHECK-NEXT: fmv.w.x ft0, a0
|
||||
; CHECK-NEXT: vsetvli a0, a1, e32,m1,ta,mu
|
||||
; CHECK-NEXT: vfwnmacc.vf v16, ft0, v18, v0.t
|
||||
; CHECK-NEXT: jalr zero, 0(ra)
|
||||
entry:
|
||||
%a = call <vscale x 2 x double> @llvm.riscv.vfwnmacc.mask.nxv2f64.f32(
|
||||
<vscale x 2 x double> %0,
|
||||
float %1,
|
||||
<vscale x 2 x float> %2,
|
||||
<vscale x 2 x i1> %3,
|
||||
i64 %4)
|
||||
|
||||
ret <vscale x 2 x double> %a
|
||||
}
|
||||
|
||||
declare <vscale x 4 x double> @llvm.riscv.vfwnmacc.nxv4f64.f32(
|
||||
<vscale x 4 x double>,
|
||||
float,
|
||||
<vscale x 4 x float>,
|
||||
i64);
|
||||
|
||||
define <vscale x 4 x double> @intrinsic_vfwnmacc_vf_nxv4f64_f32_nxv4f32(<vscale x 4 x double> %0, float %1, <vscale x 4 x float> %2, i64 %3) nounwind {
|
||||
; CHECK-LABEL: intrinsic_vfwnmacc_vf_nxv4f64_f32_nxv4f32:
|
||||
; CHECK: # %bb.0: # %entry
|
||||
; CHECK-NEXT: fmv.w.x ft0, a0
|
||||
; CHECK-NEXT: vsetvli a0, a1, e32,m2,ta,mu
|
||||
; CHECK-NEXT: vfwnmacc.vf v16, ft0, v20
|
||||
; CHECK-NEXT: jalr zero, 0(ra)
|
||||
entry:
|
||||
%a = call <vscale x 4 x double> @llvm.riscv.vfwnmacc.nxv4f64.f32(
|
||||
<vscale x 4 x double> %0,
|
||||
float %1,
|
||||
<vscale x 4 x float> %2,
|
||||
i64 %3)
|
||||
|
||||
ret <vscale x 4 x double> %a
|
||||
}
|
||||
|
||||
declare <vscale x 4 x double> @llvm.riscv.vfwnmacc.mask.nxv4f64.f32(
|
||||
<vscale x 4 x double>,
|
||||
float,
|
||||
<vscale x 4 x float>,
|
||||
<vscale x 4 x i1>,
|
||||
i64);
|
||||
|
||||
define <vscale x 4 x double> @intrinsic_vfwnmacc_mask_vf_nxv4f64_f32_nxv4f32(<vscale x 4 x double> %0, float %1, <vscale x 4 x float> %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
|
||||
; CHECK-LABEL: intrinsic_vfwnmacc_mask_vf_nxv4f64_f32_nxv4f32:
|
||||
; CHECK: # %bb.0: # %entry
|
||||
; CHECK-NEXT: fmv.w.x ft0, a0
|
||||
; CHECK-NEXT: vsetvli a0, a1, e32,m2,ta,mu
|
||||
; CHECK-NEXT: vfwnmacc.vf v16, ft0, v20, v0.t
|
||||
; CHECK-NEXT: jalr zero, 0(ra)
|
||||
entry:
|
||||
%a = call <vscale x 4 x double> @llvm.riscv.vfwnmacc.mask.nxv4f64.f32(
|
||||
<vscale x 4 x double> %0,
|
||||
float %1,
|
||||
<vscale x 4 x float> %2,
|
||||
<vscale x 4 x i1> %3,
|
||||
i64 %4)
|
||||
|
||||
ret <vscale x 4 x double> %a
|
||||
}
|
||||
|
||||
declare <vscale x 8 x double> @llvm.riscv.vfwnmacc.nxv8f64.f32(
|
||||
<vscale x 8 x double>,
|
||||
float,
|
||||
<vscale x 8 x float>,
|
||||
i64);
|
||||
|
||||
define <vscale x 8 x double> @intrinsic_vfwnmacc_vf_nxv8f64_f32_nxv8f32(<vscale x 8 x double> %0, float %1, <vscale x 8 x float> %2, i64 %3) nounwind {
|
||||
; CHECK-LABEL: intrinsic_vfwnmacc_vf_nxv8f64_f32_nxv8f32:
|
||||
; CHECK: # %bb.0: # %entry
|
||||
; CHECK-NEXT: vsetvli a3, zero, e32,m4,ta,mu
|
||||
; CHECK-NEXT: vle32.v v28, (a1)
|
||||
; CHECK-NEXT: fmv.w.x ft0, a0
|
||||
; CHECK-NEXT: vsetvli a0, a2, e32,m4,ta,mu
|
||||
; CHECK-NEXT: vfwnmacc.vf v16, ft0, v28
|
||||
; CHECK-NEXT: jalr zero, 0(ra)
|
||||
entry:
|
||||
%a = call <vscale x 8 x double> @llvm.riscv.vfwnmacc.nxv8f64.f32(
|
||||
<vscale x 8 x double> %0,
|
||||
float %1,
|
||||
<vscale x 8 x float> %2,
|
||||
i64 %3)
|
||||
|
||||
ret <vscale x 8 x double> %a
|
||||
}
|
||||
|
||||
declare <vscale x 8 x double> @llvm.riscv.vfwnmacc.mask.nxv8f64.f32(
|
||||
<vscale x 8 x double>,
|
||||
float,
|
||||
<vscale x 8 x float>,
|
||||
<vscale x 8 x i1>,
|
||||
i64);
|
||||
|
||||
define <vscale x 8 x double> @intrinsic_vfwnmacc_mask_vf_nxv8f64_f32_nxv8f32(<vscale x 8 x double> %0, float %1, <vscale x 8 x float> %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
|
||||
; CHECK-LABEL: intrinsic_vfwnmacc_mask_vf_nxv8f64_f32_nxv8f32:
|
||||
; CHECK: # %bb.0: # %entry
|
||||
; CHECK-NEXT: vsetvli a3, zero, e32,m4,ta,mu
|
||||
; CHECK-NEXT: vle32.v v28, (a1)
|
||||
; CHECK-NEXT: fmv.w.x ft0, a0
|
||||
; CHECK-NEXT: vsetvli a0, a2, e32,m4,ta,mu
|
||||
; CHECK-NEXT: vfwnmacc.vf v16, ft0, v28, v0.t
|
||||
; CHECK-NEXT: jalr zero, 0(ra)
|
||||
entry:
|
||||
%a = call <vscale x 8 x double> @llvm.riscv.vfwnmacc.mask.nxv8f64.f32(
|
||||
<vscale x 8 x double> %0,
|
||||
float %1,
|
||||
<vscale x 8 x float> %2,
|
||||
<vscale x 8 x i1> %3,
|
||||
i64 %4)
|
||||
|
||||
ret <vscale x 8 x double> %a
|
||||
}
|
||||
482
test/CodeGen/RISCV/rvv/vfwnmsac-rv32.ll
Normal file
482
test/CodeGen/RISCV/rvv/vfwnmsac-rv32.ll
Normal file
@ -0,0 +1,482 @@
|
||||
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
|
||||
; RUN: llc -mtriple=riscv32 -mattr=+experimental-v,+f,+experimental-zfh -verify-machineinstrs \
|
||||
; RUN: --riscv-no-aliases < %s | FileCheck %s
|
||||
declare <vscale x 1 x float> @llvm.riscv.vfwnmsac.nxv1f32.nxv1f16(
|
||||
<vscale x 1 x float>,
|
||||
<vscale x 1 x half>,
|
||||
<vscale x 1 x half>,
|
||||
i32);
|
||||
|
||||
define <vscale x 1 x float> @intrinsic_vfwnmsac_vv_nxv1f32_nxv1f16_nxv1f16(<vscale x 1 x float> %0, <vscale x 1 x half> %1, <vscale x 1 x half> %2, i32 %3) nounwind {
|
||||
; CHECK-LABEL: intrinsic_vfwnmsac_vv_nxv1f32_nxv1f16_nxv1f16:
|
||||
; CHECK: # %bb.0: # %entry
|
||||
; CHECK-NEXT: vsetvli a0, a0, e16,mf4,ta,mu
|
||||
; CHECK-NEXT: vfwnmsac.vv v16, v17, v18
|
||||
; CHECK-NEXT: jalr zero, 0(ra)
|
||||
entry:
|
||||
%a = call <vscale x 1 x float> @llvm.riscv.vfwnmsac.nxv1f32.nxv1f16(
|
||||
<vscale x 1 x float> %0,
|
||||
<vscale x 1 x half> %1,
|
||||
<vscale x 1 x half> %2,
|
||||
i32 %3)
|
||||
|
||||
ret <vscale x 1 x float> %a
|
||||
}
|
||||
|
||||
declare <vscale x 1 x float> @llvm.riscv.vfwnmsac.mask.nxv1f32.nxv1f16(
|
||||
<vscale x 1 x float>,
|
||||
<vscale x 1 x half>,
|
||||
<vscale x 1 x half>,
|
||||
<vscale x 1 x i1>,
|
||||
i32);
|
||||
|
||||
define <vscale x 1 x float> @intrinsic_vfwnmsac_mask_vv_nxv1f32_nxv1f16_nxv1f16(<vscale x 1 x float> %0, <vscale x 1 x half> %1, <vscale x 1 x half> %2, <vscale x 1 x i1> %3, i32 %4) nounwind {
|
||||
; CHECK-LABEL: intrinsic_vfwnmsac_mask_vv_nxv1f32_nxv1f16_nxv1f16:
|
||||
; CHECK: # %bb.0: # %entry
|
||||
; CHECK-NEXT: vsetvli a0, a0, e16,mf4,ta,mu
|
||||
; CHECK-NEXT: vfwnmsac.vv v16, v17, v18, v0.t
|
||||
; CHECK-NEXT: jalr zero, 0(ra)
|
||||
entry:
|
||||
%a = call <vscale x 1 x float> @llvm.riscv.vfwnmsac.mask.nxv1f32.nxv1f16(
|
||||
<vscale x 1 x float> %0,
|
||||
<vscale x 1 x half> %1,
|
||||
<vscale x 1 x half> %2,
|
||||
<vscale x 1 x i1> %3,
|
||||
i32 %4)
|
||||
|
||||
ret <vscale x 1 x float> %a
|
||||
}
|
||||
|
||||
declare <vscale x 2 x float> @llvm.riscv.vfwnmsac.nxv2f32.nxv2f16(
|
||||
<vscale x 2 x float>,
|
||||
<vscale x 2 x half>,
|
||||
<vscale x 2 x half>,
|
||||
i32);
|
||||
|
||||
define <vscale x 2 x float> @intrinsic_vfwnmsac_vv_nxv2f32_nxv2f16_nxv2f16(<vscale x 2 x float> %0, <vscale x 2 x half> %1, <vscale x 2 x half> %2, i32 %3) nounwind {
|
||||
; CHECK-LABEL: intrinsic_vfwnmsac_vv_nxv2f32_nxv2f16_nxv2f16:
|
||||
; CHECK: # %bb.0: # %entry
|
||||
; CHECK-NEXT: vsetvli a0, a0, e16,mf2,ta,mu
|
||||
; CHECK-NEXT: vfwnmsac.vv v16, v17, v18
|
||||
; CHECK-NEXT: jalr zero, 0(ra)
|
||||
entry:
|
||||
%a = call <vscale x 2 x float> @llvm.riscv.vfwnmsac.nxv2f32.nxv2f16(
|
||||
<vscale x 2 x float> %0,
|
||||
<vscale x 2 x half> %1,
|
||||
<vscale x 2 x half> %2,
|
||||
i32 %3)
|
||||
|
||||
ret <vscale x 2 x float> %a
|
||||
}
|
||||
|
||||
declare <vscale x 2 x float> @llvm.riscv.vfwnmsac.mask.nxv2f32.nxv2f16(
|
||||
<vscale x 2 x float>,
|
||||
<vscale x 2 x half>,
|
||||
<vscale x 2 x half>,
|
||||
<vscale x 2 x i1>,
|
||||
i32);
|
||||
|
||||
define <vscale x 2 x float> @intrinsic_vfwnmsac_mask_vv_nxv2f32_nxv2f16_nxv2f16(<vscale x 2 x float> %0, <vscale x 2 x half> %1, <vscale x 2 x half> %2, <vscale x 2 x i1> %3, i32 %4) nounwind {
|
||||
; CHECK-LABEL: intrinsic_vfwnmsac_mask_vv_nxv2f32_nxv2f16_nxv2f16:
|
||||
; CHECK: # %bb.0: # %entry
|
||||
; CHECK-NEXT: vsetvli a0, a0, e16,mf2,ta,mu
|
||||
; CHECK-NEXT: vfwnmsac.vv v16, v17, v18, v0.t
|
||||
; CHECK-NEXT: jalr zero, 0(ra)
|
||||
entry:
|
||||
%a = call <vscale x 2 x float> @llvm.riscv.vfwnmsac.mask.nxv2f32.nxv2f16(
|
||||
<vscale x 2 x float> %0,
|
||||
<vscale x 2 x half> %1,
|
||||
<vscale x 2 x half> %2,
|
||||
<vscale x 2 x i1> %3,
|
||||
i32 %4)
|
||||
|
||||
ret <vscale x 2 x float> %a
|
||||
}
|
||||
|
||||
declare <vscale x 4 x float> @llvm.riscv.vfwnmsac.nxv4f32.nxv4f16(
|
||||
<vscale x 4 x float>,
|
||||
<vscale x 4 x half>,
|
||||
<vscale x 4 x half>,
|
||||
i32);
|
||||
|
||||
define <vscale x 4 x float> @intrinsic_vfwnmsac_vv_nxv4f32_nxv4f16_nxv4f16(<vscale x 4 x float> %0, <vscale x 4 x half> %1, <vscale x 4 x half> %2, i32 %3) nounwind {
|
||||
; CHECK-LABEL: intrinsic_vfwnmsac_vv_nxv4f32_nxv4f16_nxv4f16:
|
||||
; CHECK: # %bb.0: # %entry
|
||||
; CHECK-NEXT: vsetvli a0, a0, e16,m1,ta,mu
|
||||
; CHECK-NEXT: vfwnmsac.vv v16, v18, v19
|
||||
; CHECK-NEXT: jalr zero, 0(ra)
|
||||
entry:
|
||||
%a = call <vscale x 4 x float> @llvm.riscv.vfwnmsac.nxv4f32.nxv4f16(
|
||||
<vscale x 4 x float> %0,
|
||||
<vscale x 4 x half> %1,
|
||||
<vscale x 4 x half> %2,
|
||||
i32 %3)
|
||||
|
||||
ret <vscale x 4 x float> %a
|
||||
}
|
||||
|
||||
declare <vscale x 4 x float> @llvm.riscv.vfwnmsac.mask.nxv4f32.nxv4f16(
|
||||
<vscale x 4 x float>,
|
||||
<vscale x 4 x half>,
|
||||
<vscale x 4 x half>,
|
||||
<vscale x 4 x i1>,
|
||||
i32);
|
||||
|
||||
define <vscale x 4 x float> @intrinsic_vfwnmsac_mask_vv_nxv4f32_nxv4f16_nxv4f16(<vscale x 4 x float> %0, <vscale x 4 x half> %1, <vscale x 4 x half> %2, <vscale x 4 x i1> %3, i32 %4) nounwind {
|
||||
; CHECK-LABEL: intrinsic_vfwnmsac_mask_vv_nxv4f32_nxv4f16_nxv4f16:
|
||||
; CHECK: # %bb.0: # %entry
|
||||
; CHECK-NEXT: vsetvli a0, a0, e16,m1,ta,mu
|
||||
; CHECK-NEXT: vfwnmsac.vv v16, v18, v19, v0.t
|
||||
; CHECK-NEXT: jalr zero, 0(ra)
|
||||
entry:
|
||||
%a = call <vscale x 4 x float> @llvm.riscv.vfwnmsac.mask.nxv4f32.nxv4f16(
|
||||
<vscale x 4 x float> %0,
|
||||
<vscale x 4 x half> %1,
|
||||
<vscale x 4 x half> %2,
|
||||
<vscale x 4 x i1> %3,
|
||||
i32 %4)
|
||||
|
||||
ret <vscale x 4 x float> %a
|
||||
}
|
||||
|
||||
declare <vscale x 8 x float> @llvm.riscv.vfwnmsac.nxv8f32.nxv8f16(
|
||||
<vscale x 8 x float>,
|
||||
<vscale x 8 x half>,
|
||||
<vscale x 8 x half>,
|
||||
i32);
|
||||
|
||||
define <vscale x 8 x float> @intrinsic_vfwnmsac_vv_nxv8f32_nxv8f16_nxv8f16(<vscale x 8 x float> %0, <vscale x 8 x half> %1, <vscale x 8 x half> %2, i32 %3) nounwind {
|
||||
; CHECK-LABEL: intrinsic_vfwnmsac_vv_nxv8f32_nxv8f16_nxv8f16:
|
||||
; CHECK: # %bb.0: # %entry
|
||||
; CHECK-NEXT: vsetvli a0, a0, e16,m2,ta,mu
|
||||
; CHECK-NEXT: vfwnmsac.vv v16, v20, v22
|
||||
; CHECK-NEXT: jalr zero, 0(ra)
|
||||
entry:
|
||||
%a = call <vscale x 8 x float> @llvm.riscv.vfwnmsac.nxv8f32.nxv8f16(
|
||||
<vscale x 8 x float> %0,
|
||||
<vscale x 8 x half> %1,
|
||||
<vscale x 8 x half> %2,
|
||||
i32 %3)
|
||||
|
||||
ret <vscale x 8 x float> %a
|
||||
}
|
||||
|
||||
declare <vscale x 8 x float> @llvm.riscv.vfwnmsac.mask.nxv8f32.nxv8f16(
|
||||
<vscale x 8 x float>,
|
||||
<vscale x 8 x half>,
|
||||
<vscale x 8 x half>,
|
||||
<vscale x 8 x i1>,
|
||||
i32);
|
||||
|
||||
define <vscale x 8 x float> @intrinsic_vfwnmsac_mask_vv_nxv8f32_nxv8f16_nxv8f16(<vscale x 8 x float> %0, <vscale x 8 x half> %1, <vscale x 8 x half> %2, <vscale x 8 x i1> %3, i32 %4) nounwind {
|
||||
; CHECK-LABEL: intrinsic_vfwnmsac_mask_vv_nxv8f32_nxv8f16_nxv8f16:
|
||||
; CHECK: # %bb.0: # %entry
|
||||
; CHECK-NEXT: vsetvli a0, a0, e16,m2,ta,mu
|
||||
; CHECK-NEXT: vfwnmsac.vv v16, v20, v22, v0.t
|
||||
; CHECK-NEXT: jalr zero, 0(ra)
|
||||
entry:
|
||||
%a = call <vscale x 8 x float> @llvm.riscv.vfwnmsac.mask.nxv8f32.nxv8f16(
|
||||
<vscale x 8 x float> %0,
|
||||
<vscale x 8 x half> %1,
|
||||
<vscale x 8 x half> %2,
|
||||
<vscale x 8 x i1> %3,
|
||||
i32 %4)
|
||||
|
||||
ret <vscale x 8 x float> %a
|
||||
}
|
||||
|
||||
declare <vscale x 16 x float> @llvm.riscv.vfwnmsac.nxv16f32.nxv16f16(
|
||||
<vscale x 16 x float>,
|
||||
<vscale x 16 x half>,
|
||||
<vscale x 16 x half>,
|
||||
i32);
|
||||
|
||||
define <vscale x 16 x float> @intrinsic_vfwnmsac_vv_nxv16f32_nxv16f16_nxv16f16(<vscale x 16 x float> %0, <vscale x 16 x half> %1, <vscale x 16 x half> %2, i32 %3) nounwind {
|
||||
; CHECK-LABEL: intrinsic_vfwnmsac_vv_nxv16f32_nxv16f16_nxv16f16:
|
||||
; CHECK: # %bb.0: # %entry
|
||||
; CHECK-NEXT: vsetvli a3, zero, e16,m4,ta,mu
|
||||
; CHECK-NEXT: vle16.v v28, (a1)
|
||||
; CHECK-NEXT: vle16.v v8, (a0)
|
||||
; CHECK-NEXT: vsetvli a0, a2, e16,m4,ta,mu
|
||||
; CHECK-NEXT: vfwnmsac.vv v16, v8, v28
|
||||
; CHECK-NEXT: jalr zero, 0(ra)
|
||||
entry:
|
||||
%a = call <vscale x 16 x float> @llvm.riscv.vfwnmsac.nxv16f32.nxv16f16(
|
||||
<vscale x 16 x float> %0,
|
||||
<vscale x 16 x half> %1,
|
||||
<vscale x 16 x half> %2,
|
||||
i32 %3)
|
||||
|
||||
ret <vscale x 16 x float> %a
|
||||
}
|
||||
|
||||
declare <vscale x 16 x float> @llvm.riscv.vfwnmsac.mask.nxv16f32.nxv16f16(
|
||||
<vscale x 16 x float>,
|
||||
<vscale x 16 x half>,
|
||||
<vscale x 16 x half>,
|
||||
<vscale x 16 x i1>,
|
||||
i32);
|
||||
|
||||
define <vscale x 16 x float> @intrinsic_vfwnmsac_mask_vv_nxv16f32_nxv16f16_nxv16f16(<vscale x 16 x float> %0, <vscale x 16 x half> %1, <vscale x 16 x half> %2, <vscale x 16 x i1> %3, i32 %4) nounwind {
|
||||
; CHECK-LABEL: intrinsic_vfwnmsac_mask_vv_nxv16f32_nxv16f16_nxv16f16:
|
||||
; CHECK: # %bb.0: # %entry
|
||||
; CHECK-NEXT: vsetvli a3, zero, e16,m4,ta,mu
|
||||
; CHECK-NEXT: vle16.v v28, (a1)
|
||||
; CHECK-NEXT: vle16.v v8, (a0)
|
||||
; CHECK-NEXT: vsetvli a0, a2, e16,m4,ta,mu
|
||||
; CHECK-NEXT: vfwnmsac.vv v16, v8, v28, v0.t
|
||||
; CHECK-NEXT: jalr zero, 0(ra)
|
||||
entry:
|
||||
%a = call <vscale x 16 x float> @llvm.riscv.vfwnmsac.mask.nxv16f32.nxv16f16(
|
||||
<vscale x 16 x float> %0,
|
||||
<vscale x 16 x half> %1,
|
||||
<vscale x 16 x half> %2,
|
||||
<vscale x 16 x i1> %3,
|
||||
i32 %4)
|
||||
|
||||
ret <vscale x 16 x float> %a
|
||||
}
|
||||
|
||||
declare <vscale x 1 x float> @llvm.riscv.vfwnmsac.nxv1f32.f16(
|
||||
<vscale x 1 x float>,
|
||||
half,
|
||||
<vscale x 1 x half>,
|
||||
i32);
|
||||
|
||||
define <vscale x 1 x float> @intrinsic_vfwnmsac_vf_nxv1f32_f16_nxv1f16(<vscale x 1 x float> %0, half %1, <vscale x 1 x half> %2, i32 %3) nounwind {
|
||||
; CHECK-LABEL: intrinsic_vfwnmsac_vf_nxv1f32_f16_nxv1f16:
|
||||
; CHECK: # %bb.0: # %entry
|
||||
; CHECK-NEXT: fmv.h.x ft0, a0
|
||||
; CHECK-NEXT: vsetvli a0, a1, e16,mf4,ta,mu
|
||||
; CHECK-NEXT: vfwnmsac.vf v16, ft0, v17
|
||||
; CHECK-NEXT: jalr zero, 0(ra)
|
||||
entry:
|
||||
%a = call <vscale x 1 x float> @llvm.riscv.vfwnmsac.nxv1f32.f16(
|
||||
<vscale x 1 x float> %0,
|
||||
half %1,
|
||||
<vscale x 1 x half> %2,
|
||||
i32 %3)
|
||||
|
||||
ret <vscale x 1 x float> %a
|
||||
}
|
||||
|
||||
declare <vscale x 1 x float> @llvm.riscv.vfwnmsac.mask.nxv1f32.f16(
|
||||
<vscale x 1 x float>,
|
||||
half,
|
||||
<vscale x 1 x half>,
|
||||
<vscale x 1 x i1>,
|
||||
i32);
|
||||
|
||||
define <vscale x 1 x float> @intrinsic_vfwnmsac_mask_vf_nxv1f32_f16_nxv1f16(<vscale x 1 x float> %0, half %1, <vscale x 1 x half> %2, <vscale x 1 x i1> %3, i32 %4) nounwind {
|
||||
; CHECK-LABEL: intrinsic_vfwnmsac_mask_vf_nxv1f32_f16_nxv1f16:
|
||||
; CHECK: # %bb.0: # %entry
|
||||
; CHECK-NEXT: fmv.h.x ft0, a0
|
||||
; CHECK-NEXT: vsetvli a0, a1, e16,mf4,ta,mu
|
||||
; CHECK-NEXT: vfwnmsac.vf v16, ft0, v17, v0.t
|
||||
; CHECK-NEXT: jalr zero, 0(ra)
|
||||
entry:
|
||||
%a = call <vscale x 1 x float> @llvm.riscv.vfwnmsac.mask.nxv1f32.f16(
|
||||
<vscale x 1 x float> %0,
|
||||
half %1,
|
||||
<vscale x 1 x half> %2,
|
||||
<vscale x 1 x i1> %3,
|
||||
i32 %4)
|
||||
|
||||
ret <vscale x 1 x float> %a
|
||||
}
|
||||
|
||||
declare <vscale x 2 x float> @llvm.riscv.vfwnmsac.nxv2f32.f16(
|
||||
<vscale x 2 x float>,
|
||||
half,
|
||||
<vscale x 2 x half>,
|
||||
i32);
|
||||
|
||||
define <vscale x 2 x float> @intrinsic_vfwnmsac_vf_nxv2f32_f16_nxv2f16(<vscale x 2 x float> %0, half %1, <vscale x 2 x half> %2, i32 %3) nounwind {
|
||||
; CHECK-LABEL: intrinsic_vfwnmsac_vf_nxv2f32_f16_nxv2f16:
|
||||
; CHECK: # %bb.0: # %entry
|
||||
; CHECK-NEXT: fmv.h.x ft0, a0
|
||||
; CHECK-NEXT: vsetvli a0, a1, e16,mf2,ta,mu
|
||||
; CHECK-NEXT: vfwnmsac.vf v16, ft0, v17
|
||||
; CHECK-NEXT: jalr zero, 0(ra)
|
||||
entry:
|
||||
%a = call <vscale x 2 x float> @llvm.riscv.vfwnmsac.nxv2f32.f16(
|
||||
<vscale x 2 x float> %0,
|
||||
half %1,
|
||||
<vscale x 2 x half> %2,
|
||||
i32 %3)
|
||||
|
||||
ret <vscale x 2 x float> %a
|
||||
}
|
||||
|
||||
declare <vscale x 2 x float> @llvm.riscv.vfwnmsac.mask.nxv2f32.f16(
|
||||
<vscale x 2 x float>,
|
||||
half,
|
||||
<vscale x 2 x half>,
|
||||
<vscale x 2 x i1>,
|
||||
i32);
|
||||
|
||||
define <vscale x 2 x float> @intrinsic_vfwnmsac_mask_vf_nxv2f32_f16_nxv2f16(<vscale x 2 x float> %0, half %1, <vscale x 2 x half> %2, <vscale x 2 x i1> %3, i32 %4) nounwind {
|
||||
; CHECK-LABEL: intrinsic_vfwnmsac_mask_vf_nxv2f32_f16_nxv2f16:
|
||||
; CHECK: # %bb.0: # %entry
|
||||
; CHECK-NEXT: fmv.h.x ft0, a0
|
||||
; CHECK-NEXT: vsetvli a0, a1, e16,mf2,ta,mu
|
||||
; CHECK-NEXT: vfwnmsac.vf v16, ft0, v17, v0.t
|
||||
; CHECK-NEXT: jalr zero, 0(ra)
|
||||
entry:
|
||||
%a = call <vscale x 2 x float> @llvm.riscv.vfwnmsac.mask.nxv2f32.f16(
|
||||
<vscale x 2 x float> %0,
|
||||
half %1,
|
||||
<vscale x 2 x half> %2,
|
||||
<vscale x 2 x i1> %3,
|
||||
i32 %4)
|
||||
|
||||
ret <vscale x 2 x float> %a
|
||||
}
|
||||
|
||||
declare <vscale x 4 x float> @llvm.riscv.vfwnmsac.nxv4f32.f16(
|
||||
<vscale x 4 x float>,
|
||||
half,
|
||||
<vscale x 4 x half>,
|
||||
i32);
|
||||
|
||||
define <vscale x 4 x float> @intrinsic_vfwnmsac_vf_nxv4f32_f16_nxv4f16(<vscale x 4 x float> %0, half %1, <vscale x 4 x half> %2, i32 %3) nounwind {
|
||||
; CHECK-LABEL: intrinsic_vfwnmsac_vf_nxv4f32_f16_nxv4f16:
|
||||
; CHECK: # %bb.0: # %entry
|
||||
; CHECK-NEXT: fmv.h.x ft0, a0
|
||||
; CHECK-NEXT: vsetvli a0, a1, e16,m1,ta,mu
|
||||
; CHECK-NEXT: vfwnmsac.vf v16, ft0, v18
|
||||
; CHECK-NEXT: jalr zero, 0(ra)
|
||||
entry:
|
||||
%a = call <vscale x 4 x float> @llvm.riscv.vfwnmsac.nxv4f32.f16(
|
||||
<vscale x 4 x float> %0,
|
||||
half %1,
|
||||
<vscale x 4 x half> %2,
|
||||
i32 %3)
|
||||
|
||||
ret <vscale x 4 x float> %a
|
||||
}
|
||||
|
||||
declare <vscale x 4 x float> @llvm.riscv.vfwnmsac.mask.nxv4f32.f16(
|
||||
<vscale x 4 x float>,
|
||||
half,
|
||||
<vscale x 4 x half>,
|
||||
<vscale x 4 x i1>,
|
||||
i32);
|
||||
|
||||
define <vscale x 4 x float> @intrinsic_vfwnmsac_mask_vf_nxv4f32_f16_nxv4f16(<vscale x 4 x float> %0, half %1, <vscale x 4 x half> %2, <vscale x 4 x i1> %3, i32 %4) nounwind {
|
||||
; CHECK-LABEL: intrinsic_vfwnmsac_mask_vf_nxv4f32_f16_nxv4f16:
|
||||
; CHECK: # %bb.0: # %entry
|
||||
; CHECK-NEXT: fmv.h.x ft0, a0
|
||||
; CHECK-NEXT: vsetvli a0, a1, e16,m1,ta,mu
|
||||
; CHECK-NEXT: vfwnmsac.vf v16, ft0, v18, v0.t
|
||||
; CHECK-NEXT: jalr zero, 0(ra)
|
||||
entry:
|
||||
%a = call <vscale x 4 x float> @llvm.riscv.vfwnmsac.mask.nxv4f32.f16(
|
||||
<vscale x 4 x float> %0,
|
||||
half %1,
|
||||
<vscale x 4 x half> %2,
|
||||
<vscale x 4 x i1> %3,
|
||||
i32 %4)
|
||||
|
||||
ret <vscale x 4 x float> %a
|
||||
}
|
||||
|
||||
declare <vscale x 8 x float> @llvm.riscv.vfwnmsac.nxv8f32.f16(
|
||||
<vscale x 8 x float>,
|
||||
half,
|
||||
<vscale x 8 x half>,
|
||||
i32);
|
||||
|
||||
define <vscale x 8 x float> @intrinsic_vfwnmsac_vf_nxv8f32_f16_nxv8f16(<vscale x 8 x float> %0, half %1, <vscale x 8 x half> %2, i32 %3) nounwind {
|
||||
; CHECK-LABEL: intrinsic_vfwnmsac_vf_nxv8f32_f16_nxv8f16:
|
||||
; CHECK: # %bb.0: # %entry
|
||||
; CHECK-NEXT: fmv.h.x ft0, a0
|
||||
; CHECK-NEXT: vsetvli a0, a1, e16,m2,ta,mu
|
||||
; CHECK-NEXT: vfwnmsac.vf v16, ft0, v20
|
||||
; CHECK-NEXT: jalr zero, 0(ra)
|
||||
entry:
|
||||
%a = call <vscale x 8 x float> @llvm.riscv.vfwnmsac.nxv8f32.f16(
|
||||
<vscale x 8 x float> %0,
|
||||
half %1,
|
||||
<vscale x 8 x half> %2,
|
||||
i32 %3)
|
||||
|
||||
ret <vscale x 8 x float> %a
|
||||
}
|
||||
|
||||
declare <vscale x 8 x float> @llvm.riscv.vfwnmsac.mask.nxv8f32.f16(
|
||||
<vscale x 8 x float>,
|
||||
half,
|
||||
<vscale x 8 x half>,
|
||||
<vscale x 8 x i1>,
|
||||
i32);
|
||||
|
||||
define <vscale x 8 x float> @intrinsic_vfwnmsac_mask_vf_nxv8f32_f16_nxv8f16(<vscale x 8 x float> %0, half %1, <vscale x 8 x half> %2, <vscale x 8 x i1> %3, i32 %4) nounwind {
|
||||
; CHECK-LABEL: intrinsic_vfwnmsac_mask_vf_nxv8f32_f16_nxv8f16:
|
||||
; CHECK: # %bb.0: # %entry
|
||||
; CHECK-NEXT: fmv.h.x ft0, a0
|
||||
; CHECK-NEXT: vsetvli a0, a1, e16,m2,ta,mu
|
||||
; CHECK-NEXT: vfwnmsac.vf v16, ft0, v20, v0.t
|
||||
; CHECK-NEXT: jalr zero, 0(ra)
|
||||
entry:
|
||||
%a = call <vscale x 8 x float> @llvm.riscv.vfwnmsac.mask.nxv8f32.f16(
|
||||
<vscale x 8 x float> %0,
|
||||
half %1,
|
||||
<vscale x 8 x half> %2,
|
||||
<vscale x 8 x i1> %3,
|
||||
i32 %4)
|
||||
|
||||
ret <vscale x 8 x float> %a
|
||||
}
|
||||
|
||||
declare <vscale x 16 x float> @llvm.riscv.vfwnmsac.nxv16f32.f16(
|
||||
<vscale x 16 x float>,
|
||||
half,
|
||||
<vscale x 16 x half>,
|
||||
i32);
|
||||
|
||||
define <vscale x 16 x float> @intrinsic_vfwnmsac_vf_nxv16f32_f16_nxv16f16(<vscale x 16 x float> %0, half %1, <vscale x 16 x half> %2, i32 %3) nounwind {
|
||||
; CHECK-LABEL: intrinsic_vfwnmsac_vf_nxv16f32_f16_nxv16f16:
|
||||
; CHECK: # %bb.0: # %entry
|
||||
; CHECK-NEXT: vsetvli a3, zero, e16,m4,ta,mu
|
||||
; CHECK-NEXT: vle16.v v28, (a1)
|
||||
; CHECK-NEXT: fmv.h.x ft0, a0
|
||||
; CHECK-NEXT: vsetvli a0, a2, e16,m4,ta,mu
|
||||
; CHECK-NEXT: vfwnmsac.vf v16, ft0, v28
|
||||
; CHECK-NEXT: jalr zero, 0(ra)
|
||||
entry:
|
||||
%a = call <vscale x 16 x float> @llvm.riscv.vfwnmsac.nxv16f32.f16(
|
||||
<vscale x 16 x float> %0,
|
||||
half %1,
|
||||
<vscale x 16 x half> %2,
|
||||
i32 %3)
|
||||
|
||||
ret <vscale x 16 x float> %a
|
||||
}
|
||||
|
||||
declare <vscale x 16 x float> @llvm.riscv.vfwnmsac.mask.nxv16f32.f16(
|
||||
<vscale x 16 x float>,
|
||||
half,
|
||||
<vscale x 16 x half>,
|
||||
<vscale x 16 x i1>,
|
||||
i32);
|
||||
|
||||
define <vscale x 16 x float> @intrinsic_vfwnmsac_mask_vf_nxv16f32_f16_nxv16f16(<vscale x 16 x float> %0, half %1, <vscale x 16 x half> %2, <vscale x 16 x i1> %3, i32 %4) nounwind {
|
||||
; CHECK-LABEL: intrinsic_vfwnmsac_mask_vf_nxv16f32_f16_nxv16f16:
|
||||
; CHECK: # %bb.0: # %entry
|
||||
; CHECK-NEXT: vsetvli a3, zero, e16,m4,ta,mu
|
||||
; CHECK-NEXT: vle16.v v28, (a1)
|
||||
; CHECK-NEXT: fmv.h.x ft0, a0
|
||||
; CHECK-NEXT: vsetvli a0, a2, e16,m4,ta,mu
|
||||
; CHECK-NEXT: vfwnmsac.vf v16, ft0, v28, v0.t
|
||||
; CHECK-NEXT: jalr zero, 0(ra)
|
||||
entry:
|
||||
%a = call <vscale x 16 x float> @llvm.riscv.vfwnmsac.mask.nxv16f32.f16(
|
||||
<vscale x 16 x float> %0,
|
||||
half %1,
|
||||
<vscale x 16 x half> %2,
|
||||
<vscale x 16 x i1> %3,
|
||||
i32 %4)
|
||||
|
||||
ret <vscale x 16 x float> %a
|
||||
}
|
||||
868
test/CodeGen/RISCV/rvv/vfwnmsac-rv64.ll
Normal file
868
test/CodeGen/RISCV/rvv/vfwnmsac-rv64.ll
Normal file
@ -0,0 +1,868 @@
|
||||
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
|
||||
; RUN: llc -mtriple=riscv64 -mattr=+experimental-v,+d,+experimental-zfh -verify-machineinstrs \
|
||||
; RUN: --riscv-no-aliases < %s | FileCheck %s
|
||||
declare <vscale x 1 x float> @llvm.riscv.vfwnmsac.nxv1f32.nxv1f16(
|
||||
<vscale x 1 x float>,
|
||||
<vscale x 1 x half>,
|
||||
<vscale x 1 x half>,
|
||||
i64);
|
||||
|
||||
define <vscale x 1 x float> @intrinsic_vfwnmsac_vv_nxv1f32_nxv1f16_nxv1f16(<vscale x 1 x float> %0, <vscale x 1 x half> %1, <vscale x 1 x half> %2, i64 %3) nounwind {
|
||||
; CHECK-LABEL: intrinsic_vfwnmsac_vv_nxv1f32_nxv1f16_nxv1f16:
|
||||
; CHECK: # %bb.0: # %entry
|
||||
; CHECK-NEXT: vsetvli a0, a0, e16,mf4,ta,mu
|
||||
; CHECK-NEXT: vfwnmsac.vv v16, v17, v18
|
||||
; CHECK-NEXT: jalr zero, 0(ra)
|
||||
entry:
|
||||
%a = call <vscale x 1 x float> @llvm.riscv.vfwnmsac.nxv1f32.nxv1f16(
|
||||
<vscale x 1 x float> %0,
|
||||
<vscale x 1 x half> %1,
|
||||
<vscale x 1 x half> %2,
|
||||
i64 %3)
|
||||
|
||||
ret <vscale x 1 x float> %a
|
||||
}
|
||||
|
||||
declare <vscale x 1 x float> @llvm.riscv.vfwnmsac.mask.nxv1f32.nxv1f16(
|
||||
<vscale x 1 x float>,
|
||||
<vscale x 1 x half>,
|
||||
<vscale x 1 x half>,
|
||||
<vscale x 1 x i1>,
|
||||
i64);
|
||||
|
||||
define <vscale x 1 x float> @intrinsic_vfwnmsac_mask_vv_nxv1f32_nxv1f16_nxv1f16(<vscale x 1 x float> %0, <vscale x 1 x half> %1, <vscale x 1 x half> %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
|
||||
; CHECK-LABEL: intrinsic_vfwnmsac_mask_vv_nxv1f32_nxv1f16_nxv1f16:
|
||||
; CHECK: # %bb.0: # %entry
|
||||
; CHECK-NEXT: vsetvli a0, a0, e16,mf4,ta,mu
|
||||
; CHECK-NEXT: vfwnmsac.vv v16, v17, v18, v0.t
|
||||
; CHECK-NEXT: jalr zero, 0(ra)
|
||||
entry:
|
||||
%a = call <vscale x 1 x float> @llvm.riscv.vfwnmsac.mask.nxv1f32.nxv1f16(
|
||||
<vscale x 1 x float> %0,
|
||||
<vscale x 1 x half> %1,
|
||||
<vscale x 1 x half> %2,
|
||||
<vscale x 1 x i1> %3,
|
||||
i64 %4)
|
||||
|
||||
ret <vscale x 1 x float> %a
|
||||
}
|
||||
|
||||
declare <vscale x 2 x float> @llvm.riscv.vfwnmsac.nxv2f32.nxv2f16(
|
||||
<vscale x 2 x float>,
|
||||
<vscale x 2 x half>,
|
||||
<vscale x 2 x half>,
|
||||
i64);
|
||||
|
||||
define <vscale x 2 x float> @intrinsic_vfwnmsac_vv_nxv2f32_nxv2f16_nxv2f16(<vscale x 2 x float> %0, <vscale x 2 x half> %1, <vscale x 2 x half> %2, i64 %3) nounwind {
|
||||
; CHECK-LABEL: intrinsic_vfwnmsac_vv_nxv2f32_nxv2f16_nxv2f16:
|
||||
; CHECK: # %bb.0: # %entry
|
||||
; CHECK-NEXT: vsetvli a0, a0, e16,mf2,ta,mu
|
||||
; CHECK-NEXT: vfwnmsac.vv v16, v17, v18
|
||||
; CHECK-NEXT: jalr zero, 0(ra)
|
||||
entry:
|
||||
%a = call <vscale x 2 x float> @llvm.riscv.vfwnmsac.nxv2f32.nxv2f16(
|
||||
<vscale x 2 x float> %0,
|
||||
<vscale x 2 x half> %1,
|
||||
<vscale x 2 x half> %2,
|
||||
i64 %3)
|
||||
|
||||
ret <vscale x 2 x float> %a
|
||||
}
|
||||
|
||||
declare <vscale x 2 x float> @llvm.riscv.vfwnmsac.mask.nxv2f32.nxv2f16(
|
||||
<vscale x 2 x float>,
|
||||
<vscale x 2 x half>,
|
||||
<vscale x 2 x half>,
|
||||
<vscale x 2 x i1>,
|
||||
i64);
|
||||
|
||||
define <vscale x 2 x float> @intrinsic_vfwnmsac_mask_vv_nxv2f32_nxv2f16_nxv2f16(<vscale x 2 x float> %0, <vscale x 2 x half> %1, <vscale x 2 x half> %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
|
||||
; CHECK-LABEL: intrinsic_vfwnmsac_mask_vv_nxv2f32_nxv2f16_nxv2f16:
|
||||
; CHECK: # %bb.0: # %entry
|
||||
; CHECK-NEXT: vsetvli a0, a0, e16,mf2,ta,mu
|
||||
; CHECK-NEXT: vfwnmsac.vv v16, v17, v18, v0.t
|
||||
; CHECK-NEXT: jalr zero, 0(ra)
|
||||
entry:
|
||||
%a = call <vscale x 2 x float> @llvm.riscv.vfwnmsac.mask.nxv2f32.nxv2f16(
|
||||
<vscale x 2 x float> %0,
|
||||
<vscale x 2 x half> %1,
|
||||
<vscale x 2 x half> %2,
|
||||
<vscale x 2 x i1> %3,
|
||||
i64 %4)
|
||||
|
||||
ret <vscale x 2 x float> %a
|
||||
}
|
||||
|
||||
declare <vscale x 4 x float> @llvm.riscv.vfwnmsac.nxv4f32.nxv4f16(
|
||||
<vscale x 4 x float>,
|
||||
<vscale x 4 x half>,
|
||||
<vscale x 4 x half>,
|
||||
i64);
|
||||
|
||||
define <vscale x 4 x float> @intrinsic_vfwnmsac_vv_nxv4f32_nxv4f16_nxv4f16(<vscale x 4 x float> %0, <vscale x 4 x half> %1, <vscale x 4 x half> %2, i64 %3) nounwind {
|
||||
; CHECK-LABEL: intrinsic_vfwnmsac_vv_nxv4f32_nxv4f16_nxv4f16:
|
||||
; CHECK: # %bb.0: # %entry
|
||||
; CHECK-NEXT: vsetvli a0, a0, e16,m1,ta,mu
|
||||
; CHECK-NEXT: vfwnmsac.vv v16, v18, v19
|
||||
; CHECK-NEXT: jalr zero, 0(ra)
|
||||
entry:
|
||||
%a = call <vscale x 4 x float> @llvm.riscv.vfwnmsac.nxv4f32.nxv4f16(
|
||||
<vscale x 4 x float> %0,
|
||||
<vscale x 4 x half> %1,
|
||||
<vscale x 4 x half> %2,
|
||||
i64 %3)
|
||||
|
||||
ret <vscale x 4 x float> %a
|
||||
}
|
||||
|
||||
declare <vscale x 4 x float> @llvm.riscv.vfwnmsac.mask.nxv4f32.nxv4f16(
|
||||
<vscale x 4 x float>,
|
||||
<vscale x 4 x half>,
|
||||
<vscale x 4 x half>,
|
||||
<vscale x 4 x i1>,
|
||||
i64);
|
||||
|
||||
define <vscale x 4 x float> @intrinsic_vfwnmsac_mask_vv_nxv4f32_nxv4f16_nxv4f16(<vscale x 4 x float> %0, <vscale x 4 x half> %1, <vscale x 4 x half> %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
|
||||
; CHECK-LABEL: intrinsic_vfwnmsac_mask_vv_nxv4f32_nxv4f16_nxv4f16:
|
||||
; CHECK: # %bb.0: # %entry
|
||||
; CHECK-NEXT: vsetvli a0, a0, e16,m1,ta,mu
|
||||
; CHECK-NEXT: vfwnmsac.vv v16, v18, v19, v0.t
|
||||
; CHECK-NEXT: jalr zero, 0(ra)
|
||||
entry:
|
||||
%a = call <vscale x 4 x float> @llvm.riscv.vfwnmsac.mask.nxv4f32.nxv4f16(
|
||||
<vscale x 4 x float> %0,
|
||||
<vscale x 4 x half> %1,
|
||||
<vscale x 4 x half> %2,
|
||||
<vscale x 4 x i1> %3,
|
||||
i64 %4)
|
||||
|
||||
ret <vscale x 4 x float> %a
|
||||
}
|
||||
|
||||
declare <vscale x 8 x float> @llvm.riscv.vfwnmsac.nxv8f32.nxv8f16(
|
||||
<vscale x 8 x float>,
|
||||
<vscale x 8 x half>,
|
||||
<vscale x 8 x half>,
|
||||
i64);
|
||||
|
||||
define <vscale x 8 x float> @intrinsic_vfwnmsac_vv_nxv8f32_nxv8f16_nxv8f16(<vscale x 8 x float> %0, <vscale x 8 x half> %1, <vscale x 8 x half> %2, i64 %3) nounwind {
|
||||
; CHECK-LABEL: intrinsic_vfwnmsac_vv_nxv8f32_nxv8f16_nxv8f16:
|
||||
; CHECK: # %bb.0: # %entry
|
||||
; CHECK-NEXT: vsetvli a0, a0, e16,m2,ta,mu
|
||||
; CHECK-NEXT: vfwnmsac.vv v16, v20, v22
|
||||
; CHECK-NEXT: jalr zero, 0(ra)
|
||||
entry:
|
||||
%a = call <vscale x 8 x float> @llvm.riscv.vfwnmsac.nxv8f32.nxv8f16(
|
||||
<vscale x 8 x float> %0,
|
||||
<vscale x 8 x half> %1,
|
||||
<vscale x 8 x half> %2,
|
||||
i64 %3)
|
||||
|
||||
ret <vscale x 8 x float> %a
|
||||
}
|
||||
|
||||
declare <vscale x 8 x float> @llvm.riscv.vfwnmsac.mask.nxv8f32.nxv8f16(
|
||||
<vscale x 8 x float>,
|
||||
<vscale x 8 x half>,
|
||||
<vscale x 8 x half>,
|
||||
<vscale x 8 x i1>,
|
||||
i64);
|
||||
|
||||
define <vscale x 8 x float> @intrinsic_vfwnmsac_mask_vv_nxv8f32_nxv8f16_nxv8f16(<vscale x 8 x float> %0, <vscale x 8 x half> %1, <vscale x 8 x half> %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
|
||||
; CHECK-LABEL: intrinsic_vfwnmsac_mask_vv_nxv8f32_nxv8f16_nxv8f16:
|
||||
; CHECK: # %bb.0: # %entry
|
||||
; CHECK-NEXT: vsetvli a0, a0, e16,m2,ta,mu
|
||||
; CHECK-NEXT: vfwnmsac.vv v16, v20, v22, v0.t
|
||||
; CHECK-NEXT: jalr zero, 0(ra)
|
||||
entry:
|
||||
%a = call <vscale x 8 x float> @llvm.riscv.vfwnmsac.mask.nxv8f32.nxv8f16(
|
||||
<vscale x 8 x float> %0,
|
||||
<vscale x 8 x half> %1,
|
||||
<vscale x 8 x half> %2,
|
||||
<vscale x 8 x i1> %3,
|
||||
i64 %4)
|
||||
|
||||
ret <vscale x 8 x float> %a
|
||||
}
|
||||
|
||||
declare <vscale x 16 x float> @llvm.riscv.vfwnmsac.nxv16f32.nxv16f16(
|
||||
<vscale x 16 x float>,
|
||||
<vscale x 16 x half>,
|
||||
<vscale x 16 x half>,
|
||||
i64);
|
||||
|
||||
define <vscale x 16 x float> @intrinsic_vfwnmsac_vv_nxv16f32_nxv16f16_nxv16f16(<vscale x 16 x float> %0, <vscale x 16 x half> %1, <vscale x 16 x half> %2, i64 %3) nounwind {
|
||||
; CHECK-LABEL: intrinsic_vfwnmsac_vv_nxv16f32_nxv16f16_nxv16f16:
|
||||
; CHECK: # %bb.0: # %entry
|
||||
; CHECK-NEXT: vsetvli a3, zero, e16,m4,ta,mu
|
||||
; CHECK-NEXT: vle16.v v28, (a1)
|
||||
; CHECK-NEXT: vle16.v v8, (a0)
|
||||
; CHECK-NEXT: vsetvli a0, a2, e16,m4,ta,mu
|
||||
; CHECK-NEXT: vfwnmsac.vv v16, v8, v28
|
||||
; CHECK-NEXT: jalr zero, 0(ra)
|
||||
entry:
|
||||
%a = call <vscale x 16 x float> @llvm.riscv.vfwnmsac.nxv16f32.nxv16f16(
|
||||
<vscale x 16 x float> %0,
|
||||
<vscale x 16 x half> %1,
|
||||
<vscale x 16 x half> %2,
|
||||
i64 %3)
|
||||
|
||||
ret <vscale x 16 x float> %a
|
||||
}
|
||||
|
||||
declare <vscale x 16 x float> @llvm.riscv.vfwnmsac.mask.nxv16f32.nxv16f16(
|
||||
<vscale x 16 x float>,
|
||||
<vscale x 16 x half>,
|
||||
<vscale x 16 x half>,
|
||||
<vscale x 16 x i1>,
|
||||
i64);
|
||||
|
||||
define <vscale x 16 x float> @intrinsic_vfwnmsac_mask_vv_nxv16f32_nxv16f16_nxv16f16(<vscale x 16 x float> %0, <vscale x 16 x half> %1, <vscale x 16 x half> %2, <vscale x 16 x i1> %3, i64 %4) nounwind {
|
||||
; CHECK-LABEL: intrinsic_vfwnmsac_mask_vv_nxv16f32_nxv16f16_nxv16f16:
|
||||
; CHECK: # %bb.0: # %entry
|
||||
; CHECK-NEXT: vsetvli a3, zero, e16,m4,ta,mu
|
||||
; CHECK-NEXT: vle16.v v28, (a1)
|
||||
; CHECK-NEXT: vle16.v v8, (a0)
|
||||
; CHECK-NEXT: vsetvli a0, a2, e16,m4,ta,mu
|
||||
; CHECK-NEXT: vfwnmsac.vv v16, v8, v28, v0.t
|
||||
; CHECK-NEXT: jalr zero, 0(ra)
|
||||
entry:
|
||||
%a = call <vscale x 16 x float> @llvm.riscv.vfwnmsac.mask.nxv16f32.nxv16f16(
|
||||
<vscale x 16 x float> %0,
|
||||
<vscale x 16 x half> %1,
|
||||
<vscale x 16 x half> %2,
|
||||
<vscale x 16 x i1> %3,
|
||||
i64 %4)
|
||||
|
||||
ret <vscale x 16 x float> %a
|
||||
}
|
||||
|
||||
declare <vscale x 1 x double> @llvm.riscv.vfwnmsac.nxv1f64.nxv1f32(
|
||||
<vscale x 1 x double>,
|
||||
<vscale x 1 x float>,
|
||||
<vscale x 1 x float>,
|
||||
i64);
|
||||
|
||||
define <vscale x 1 x double> @intrinsic_vfwnmsac_vv_nxv1f64_nxv1f32_nxv1f32(<vscale x 1 x double> %0, <vscale x 1 x float> %1, <vscale x 1 x float> %2, i64 %3) nounwind {
|
||||
; CHECK-LABEL: intrinsic_vfwnmsac_vv_nxv1f64_nxv1f32_nxv1f32:
|
||||
; CHECK: # %bb.0: # %entry
|
||||
; CHECK-NEXT: vsetvli a0, a0, e32,mf2,ta,mu
|
||||
; CHECK-NEXT: vfwnmsac.vv v16, v17, v18
|
||||
; CHECK-NEXT: jalr zero, 0(ra)
|
||||
entry:
|
||||
%a = call <vscale x 1 x double> @llvm.riscv.vfwnmsac.nxv1f64.nxv1f32(
|
||||
<vscale x 1 x double> %0,
|
||||
<vscale x 1 x float> %1,
|
||||
<vscale x 1 x float> %2,
|
||||
i64 %3)
|
||||
|
||||
ret <vscale x 1 x double> %a
|
||||
}
|
||||
|
||||
declare <vscale x 1 x double> @llvm.riscv.vfwnmsac.mask.nxv1f64.nxv1f32(
|
||||
<vscale x 1 x double>,
|
||||
<vscale x 1 x float>,
|
||||
<vscale x 1 x float>,
|
||||
<vscale x 1 x i1>,
|
||||
i64);
|
||||
|
||||
define <vscale x 1 x double> @intrinsic_vfwnmsac_mask_vv_nxv1f64_nxv1f32_nxv1f32(<vscale x 1 x double> %0, <vscale x 1 x float> %1, <vscale x 1 x float> %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
|
||||
; CHECK-LABEL: intrinsic_vfwnmsac_mask_vv_nxv1f64_nxv1f32_nxv1f32:
|
||||
; CHECK: # %bb.0: # %entry
|
||||
; CHECK-NEXT: vsetvli a0, a0, e32,mf2,ta,mu
|
||||
; CHECK-NEXT: vfwnmsac.vv v16, v17, v18, v0.t
|
||||
; CHECK-NEXT: jalr zero, 0(ra)
|
||||
entry:
|
||||
%a = call <vscale x 1 x double> @llvm.riscv.vfwnmsac.mask.nxv1f64.nxv1f32(
|
||||
<vscale x 1 x double> %0,
|
||||
<vscale x 1 x float> %1,
|
||||
<vscale x 1 x float> %2,
|
||||
<vscale x 1 x i1> %3,
|
||||
i64 %4)
|
||||
|
||||
ret <vscale x 1 x double> %a
|
||||
}
|
||||
|
||||
declare <vscale x 2 x double> @llvm.riscv.vfwnmsac.nxv2f64.nxv2f32(
|
||||
<vscale x 2 x double>,
|
||||
<vscale x 2 x float>,
|
||||
<vscale x 2 x float>,
|
||||
i64);
|
||||
|
||||
define <vscale x 2 x double> @intrinsic_vfwnmsac_vv_nxv2f64_nxv2f32_nxv2f32(<vscale x 2 x double> %0, <vscale x 2 x float> %1, <vscale x 2 x float> %2, i64 %3) nounwind {
|
||||
; CHECK-LABEL: intrinsic_vfwnmsac_vv_nxv2f64_nxv2f32_nxv2f32:
|
||||
; CHECK: # %bb.0: # %entry
|
||||
; CHECK-NEXT: vsetvli a0, a0, e32,m1,ta,mu
|
||||
; CHECK-NEXT: vfwnmsac.vv v16, v18, v19
|
||||
; CHECK-NEXT: jalr zero, 0(ra)
|
||||
entry:
|
||||
%a = call <vscale x 2 x double> @llvm.riscv.vfwnmsac.nxv2f64.nxv2f32(
|
||||
<vscale x 2 x double> %0,
|
||||
<vscale x 2 x float> %1,
|
||||
<vscale x 2 x float> %2,
|
||||
i64 %3)
|
||||
|
||||
ret <vscale x 2 x double> %a
|
||||
}
|
||||
|
||||
declare <vscale x 2 x double> @llvm.riscv.vfwnmsac.mask.nxv2f64.nxv2f32(
|
||||
<vscale x 2 x double>,
|
||||
<vscale x 2 x float>,
|
||||
<vscale x 2 x float>,
|
||||
<vscale x 2 x i1>,
|
||||
i64);
|
||||
|
||||
define <vscale x 2 x double> @intrinsic_vfwnmsac_mask_vv_nxv2f64_nxv2f32_nxv2f32(<vscale x 2 x double> %0, <vscale x 2 x float> %1, <vscale x 2 x float> %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
|
||||
; CHECK-LABEL: intrinsic_vfwnmsac_mask_vv_nxv2f64_nxv2f32_nxv2f32:
|
||||
; CHECK: # %bb.0: # %entry
|
||||
; CHECK-NEXT: vsetvli a0, a0, e32,m1,ta,mu
|
||||
; CHECK-NEXT: vfwnmsac.vv v16, v18, v19, v0.t
|
||||
; CHECK-NEXT: jalr zero, 0(ra)
|
||||
entry:
|
||||
%a = call <vscale x 2 x double> @llvm.riscv.vfwnmsac.mask.nxv2f64.nxv2f32(
|
||||
<vscale x 2 x double> %0,
|
||||
<vscale x 2 x float> %1,
|
||||
<vscale x 2 x float> %2,
|
||||
<vscale x 2 x i1> %3,
|
||||
i64 %4)
|
||||
|
||||
ret <vscale x 2 x double> %a
|
||||
}
|
||||
|
||||
declare <vscale x 4 x double> @llvm.riscv.vfwnmsac.nxv4f64.nxv4f32(
|
||||
<vscale x 4 x double>,
|
||||
<vscale x 4 x float>,
|
||||
<vscale x 4 x float>,
|
||||
i64);
|
||||
|
||||
define <vscale x 4 x double> @intrinsic_vfwnmsac_vv_nxv4f64_nxv4f32_nxv4f32(<vscale x 4 x double> %0, <vscale x 4 x float> %1, <vscale x 4 x float> %2, i64 %3) nounwind {
|
||||
; CHECK-LABEL: intrinsic_vfwnmsac_vv_nxv4f64_nxv4f32_nxv4f32:
|
||||
; CHECK: # %bb.0: # %entry
|
||||
; CHECK-NEXT: vsetvli a0, a0, e32,m2,ta,mu
|
||||
; CHECK-NEXT: vfwnmsac.vv v16, v20, v22
|
||||
; CHECK-NEXT: jalr zero, 0(ra)
|
||||
entry:
|
||||
%a = call <vscale x 4 x double> @llvm.riscv.vfwnmsac.nxv4f64.nxv4f32(
|
||||
<vscale x 4 x double> %0,
|
||||
<vscale x 4 x float> %1,
|
||||
<vscale x 4 x float> %2,
|
||||
i64 %3)
|
||||
|
||||
ret <vscale x 4 x double> %a
|
||||
}
|
||||
|
||||
declare <vscale x 4 x double> @llvm.riscv.vfwnmsac.mask.nxv4f64.nxv4f32(
|
||||
<vscale x 4 x double>,
|
||||
<vscale x 4 x float>,
|
||||
<vscale x 4 x float>,
|
||||
<vscale x 4 x i1>,
|
||||
i64);
|
||||
|
||||
define <vscale x 4 x double> @intrinsic_vfwnmsac_mask_vv_nxv4f64_nxv4f32_nxv4f32(<vscale x 4 x double> %0, <vscale x 4 x float> %1, <vscale x 4 x float> %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
|
||||
; CHECK-LABEL: intrinsic_vfwnmsac_mask_vv_nxv4f64_nxv4f32_nxv4f32:
|
||||
; CHECK: # %bb.0: # %entry
|
||||
; CHECK-NEXT: vsetvli a0, a0, e32,m2,ta,mu
|
||||
; CHECK-NEXT: vfwnmsac.vv v16, v20, v22, v0.t
|
||||
; CHECK-NEXT: jalr zero, 0(ra)
|
||||
entry:
|
||||
%a = call <vscale x 4 x double> @llvm.riscv.vfwnmsac.mask.nxv4f64.nxv4f32(
|
||||
<vscale x 4 x double> %0,
|
||||
<vscale x 4 x float> %1,
|
||||
<vscale x 4 x float> %2,
|
||||
<vscale x 4 x i1> %3,
|
||||
i64 %4)
|
||||
|
||||
ret <vscale x 4 x double> %a
|
||||
}
|
||||
|
||||
declare <vscale x 8 x double> @llvm.riscv.vfwnmsac.nxv8f64.nxv8f32(
|
||||
<vscale x 8 x double>,
|
||||
<vscale x 8 x float>,
|
||||
<vscale x 8 x float>,
|
||||
i64);
|
||||
|
||||
define <vscale x 8 x double> @intrinsic_vfwnmsac_vv_nxv8f64_nxv8f32_nxv8f32(<vscale x 8 x double> %0, <vscale x 8 x float> %1, <vscale x 8 x float> %2, i64 %3) nounwind {
|
||||
; CHECK-LABEL: intrinsic_vfwnmsac_vv_nxv8f64_nxv8f32_nxv8f32:
|
||||
; CHECK: # %bb.0: # %entry
|
||||
; CHECK-NEXT: vsetvli a3, zero, e32,m4,ta,mu
|
||||
; CHECK-NEXT: vle32.v v28, (a1)
|
||||
; CHECK-NEXT: vle32.v v8, (a0)
|
||||
; CHECK-NEXT: vsetvli a0, a2, e32,m4,ta,mu
|
||||
; CHECK-NEXT: vfwnmsac.vv v16, v8, v28
|
||||
; CHECK-NEXT: jalr zero, 0(ra)
|
||||
entry:
|
||||
%a = call <vscale x 8 x double> @llvm.riscv.vfwnmsac.nxv8f64.nxv8f32(
|
||||
<vscale x 8 x double> %0,
|
||||
<vscale x 8 x float> %1,
|
||||
<vscale x 8 x float> %2,
|
||||
i64 %3)
|
||||
|
||||
ret <vscale x 8 x double> %a
|
||||
}
|
||||
|
||||
declare <vscale x 8 x double> @llvm.riscv.vfwnmsac.mask.nxv8f64.nxv8f32(
|
||||
<vscale x 8 x double>,
|
||||
<vscale x 8 x float>,
|
||||
<vscale x 8 x float>,
|
||||
<vscale x 8 x i1>,
|
||||
i64);
|
||||
|
||||
define <vscale x 8 x double> @intrinsic_vfwnmsac_mask_vv_nxv8f64_nxv8f32_nxv8f32(<vscale x 8 x double> %0, <vscale x 8 x float> %1, <vscale x 8 x float> %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
|
||||
; CHECK-LABEL: intrinsic_vfwnmsac_mask_vv_nxv8f64_nxv8f32_nxv8f32:
|
||||
; CHECK: # %bb.0: # %entry
|
||||
; CHECK-NEXT: vsetvli a3, zero, e32,m4,ta,mu
|
||||
; CHECK-NEXT: vle32.v v28, (a1)
|
||||
; CHECK-NEXT: vle32.v v8, (a0)
|
||||
; CHECK-NEXT: vsetvli a0, a2, e32,m4,ta,mu
|
||||
; CHECK-NEXT: vfwnmsac.vv v16, v8, v28, v0.t
|
||||
; CHECK-NEXT: jalr zero, 0(ra)
|
||||
entry:
|
||||
%a = call <vscale x 8 x double> @llvm.riscv.vfwnmsac.mask.nxv8f64.nxv8f32(
|
||||
<vscale x 8 x double> %0,
|
||||
<vscale x 8 x float> %1,
|
||||
<vscale x 8 x float> %2,
|
||||
<vscale x 8 x i1> %3,
|
||||
i64 %4)
|
||||
|
||||
ret <vscale x 8 x double> %a
|
||||
}
|
||||
|
||||
declare <vscale x 1 x float> @llvm.riscv.vfwnmsac.nxv1f32.f16(
|
||||
<vscale x 1 x float>,
|
||||
half,
|
||||
<vscale x 1 x half>,
|
||||
i64);
|
||||
|
||||
define <vscale x 1 x float> @intrinsic_vfwnmsac_vf_nxv1f32_f16_nxv1f16(<vscale x 1 x float> %0, half %1, <vscale x 1 x half> %2, i64 %3) nounwind {
|
||||
; CHECK-LABEL: intrinsic_vfwnmsac_vf_nxv1f32_f16_nxv1f16:
|
||||
; CHECK: # %bb.0: # %entry
|
||||
; CHECK-NEXT: fmv.h.x ft0, a0
|
||||
; CHECK-NEXT: vsetvli a0, a1, e16,mf4,ta,mu
|
||||
; CHECK-NEXT: vfwnmsac.vf v16, ft0, v17
|
||||
; CHECK-NEXT: jalr zero, 0(ra)
|
||||
entry:
|
||||
%a = call <vscale x 1 x float> @llvm.riscv.vfwnmsac.nxv1f32.f16(
|
||||
<vscale x 1 x float> %0,
|
||||
half %1,
|
||||
<vscale x 1 x half> %2,
|
||||
i64 %3)
|
||||
|
||||
ret <vscale x 1 x float> %a
|
||||
}
|
||||
|
||||
declare <vscale x 1 x float> @llvm.riscv.vfwnmsac.mask.nxv1f32.f16(
|
||||
<vscale x 1 x float>,
|
||||
half,
|
||||
<vscale x 1 x half>,
|
||||
<vscale x 1 x i1>,
|
||||
i64);
|
||||
|
||||
define <vscale x 1 x float> @intrinsic_vfwnmsac_mask_vf_nxv1f32_f16_nxv1f16(<vscale x 1 x float> %0, half %1, <vscale x 1 x half> %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
|
||||
; CHECK-LABEL: intrinsic_vfwnmsac_mask_vf_nxv1f32_f16_nxv1f16:
|
||||
; CHECK: # %bb.0: # %entry
|
||||
; CHECK-NEXT: fmv.h.x ft0, a0
|
||||
; CHECK-NEXT: vsetvli a0, a1, e16,mf4,ta,mu
|
||||
; CHECK-NEXT: vfwnmsac.vf v16, ft0, v17, v0.t
|
||||
; CHECK-NEXT: jalr zero, 0(ra)
|
||||
entry:
|
||||
%a = call <vscale x 1 x float> @llvm.riscv.vfwnmsac.mask.nxv1f32.f16(
|
||||
<vscale x 1 x float> %0,
|
||||
half %1,
|
||||
<vscale x 1 x half> %2,
|
||||
<vscale x 1 x i1> %3,
|
||||
i64 %4)
|
||||
|
||||
ret <vscale x 1 x float> %a
|
||||
}
|
||||
|
||||
declare <vscale x 2 x float> @llvm.riscv.vfwnmsac.nxv2f32.f16(
|
||||
<vscale x 2 x float>,
|
||||
half,
|
||||
<vscale x 2 x half>,
|
||||
i64);
|
||||
|
||||
define <vscale x 2 x float> @intrinsic_vfwnmsac_vf_nxv2f32_f16_nxv2f16(<vscale x 2 x float> %0, half %1, <vscale x 2 x half> %2, i64 %3) nounwind {
|
||||
; CHECK-LABEL: intrinsic_vfwnmsac_vf_nxv2f32_f16_nxv2f16:
|
||||
; CHECK: # %bb.0: # %entry
|
||||
; CHECK-NEXT: fmv.h.x ft0, a0
|
||||
; CHECK-NEXT: vsetvli a0, a1, e16,mf2,ta,mu
|
||||
; CHECK-NEXT: vfwnmsac.vf v16, ft0, v17
|
||||
; CHECK-NEXT: jalr zero, 0(ra)
|
||||
entry:
|
||||
%a = call <vscale x 2 x float> @llvm.riscv.vfwnmsac.nxv2f32.f16(
|
||||
<vscale x 2 x float> %0,
|
||||
half %1,
|
||||
<vscale x 2 x half> %2,
|
||||
i64 %3)
|
||||
|
||||
ret <vscale x 2 x float> %a
|
||||
}
|
||||
|
||||
declare <vscale x 2 x float> @llvm.riscv.vfwnmsac.mask.nxv2f32.f16(
|
||||
<vscale x 2 x float>,
|
||||
half,
|
||||
<vscale x 2 x half>,
|
||||
<vscale x 2 x i1>,
|
||||
i64);
|
||||
|
||||
define <vscale x 2 x float> @intrinsic_vfwnmsac_mask_vf_nxv2f32_f16_nxv2f16(<vscale x 2 x float> %0, half %1, <vscale x 2 x half> %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
|
||||
; CHECK-LABEL: intrinsic_vfwnmsac_mask_vf_nxv2f32_f16_nxv2f16:
|
||||
; CHECK: # %bb.0: # %entry
|
||||
; CHECK-NEXT: fmv.h.x ft0, a0
|
||||
; CHECK-NEXT: vsetvli a0, a1, e16,mf2,ta,mu
|
||||
; CHECK-NEXT: vfwnmsac.vf v16, ft0, v17, v0.t
|
||||
; CHECK-NEXT: jalr zero, 0(ra)
|
||||
entry:
|
||||
%a = call <vscale x 2 x float> @llvm.riscv.vfwnmsac.mask.nxv2f32.f16(
|
||||
<vscale x 2 x float> %0,
|
||||
half %1,
|
||||
<vscale x 2 x half> %2,
|
||||
<vscale x 2 x i1> %3,
|
||||
i64 %4)
|
||||
|
||||
ret <vscale x 2 x float> %a
|
||||
}
|
||||
|
||||
declare <vscale x 4 x float> @llvm.riscv.vfwnmsac.nxv4f32.f16(
|
||||
<vscale x 4 x float>,
|
||||
half,
|
||||
<vscale x 4 x half>,
|
||||
i64);
|
||||
|
||||
define <vscale x 4 x float> @intrinsic_vfwnmsac_vf_nxv4f32_f16_nxv4f16(<vscale x 4 x float> %0, half %1, <vscale x 4 x half> %2, i64 %3) nounwind {
|
||||
; CHECK-LABEL: intrinsic_vfwnmsac_vf_nxv4f32_f16_nxv4f16:
|
||||
; CHECK: # %bb.0: # %entry
|
||||
; CHECK-NEXT: fmv.h.x ft0, a0
|
||||
; CHECK-NEXT: vsetvli a0, a1, e16,m1,ta,mu
|
||||
; CHECK-NEXT: vfwnmsac.vf v16, ft0, v18
|
||||
; CHECK-NEXT: jalr zero, 0(ra)
|
||||
entry:
|
||||
%a = call <vscale x 4 x float> @llvm.riscv.vfwnmsac.nxv4f32.f16(
|
||||
<vscale x 4 x float> %0,
|
||||
half %1,
|
||||
<vscale x 4 x half> %2,
|
||||
i64 %3)
|
||||
|
||||
ret <vscale x 4 x float> %a
|
||||
}
|
||||
|
||||
declare <vscale x 4 x float> @llvm.riscv.vfwnmsac.mask.nxv4f32.f16(
|
||||
<vscale x 4 x float>,
|
||||
half,
|
||||
<vscale x 4 x half>,
|
||||
<vscale x 4 x i1>,
|
||||
i64);
|
||||
|
||||
define <vscale x 4 x float> @intrinsic_vfwnmsac_mask_vf_nxv4f32_f16_nxv4f16(<vscale x 4 x float> %0, half %1, <vscale x 4 x half> %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
|
||||
; CHECK-LABEL: intrinsic_vfwnmsac_mask_vf_nxv4f32_f16_nxv4f16:
|
||||
; CHECK: # %bb.0: # %entry
|
||||
; CHECK-NEXT: fmv.h.x ft0, a0
|
||||
; CHECK-NEXT: vsetvli a0, a1, e16,m1,ta,mu
|
||||
; CHECK-NEXT: vfwnmsac.vf v16, ft0, v18, v0.t
|
||||
; CHECK-NEXT: jalr zero, 0(ra)
|
||||
entry:
|
||||
%a = call <vscale x 4 x float> @llvm.riscv.vfwnmsac.mask.nxv4f32.f16(
|
||||
<vscale x 4 x float> %0,
|
||||
half %1,
|
||||
<vscale x 4 x half> %2,
|
||||
<vscale x 4 x i1> %3,
|
||||
i64 %4)
|
||||
|
||||
ret <vscale x 4 x float> %a
|
||||
}
|
||||
|
||||
declare <vscale x 8 x float> @llvm.riscv.vfwnmsac.nxv8f32.f16(
|
||||
<vscale x 8 x float>,
|
||||
half,
|
||||
<vscale x 8 x half>,
|
||||
i64);
|
||||
|
||||
define <vscale x 8 x float> @intrinsic_vfwnmsac_vf_nxv8f32_f16_nxv8f16(<vscale x 8 x float> %0, half %1, <vscale x 8 x half> %2, i64 %3) nounwind {
|
||||
; CHECK-LABEL: intrinsic_vfwnmsac_vf_nxv8f32_f16_nxv8f16:
|
||||
; CHECK: # %bb.0: # %entry
|
||||
; CHECK-NEXT: fmv.h.x ft0, a0
|
||||
; CHECK-NEXT: vsetvli a0, a1, e16,m2,ta,mu
|
||||
; CHECK-NEXT: vfwnmsac.vf v16, ft0, v20
|
||||
; CHECK-NEXT: jalr zero, 0(ra)
|
||||
entry:
|
||||
%a = call <vscale x 8 x float> @llvm.riscv.vfwnmsac.nxv8f32.f16(
|
||||
<vscale x 8 x float> %0,
|
||||
half %1,
|
||||
<vscale x 8 x half> %2,
|
||||
i64 %3)
|
||||
|
||||
ret <vscale x 8 x float> %a
|
||||
}
|
||||
|
||||
declare <vscale x 8 x float> @llvm.riscv.vfwnmsac.mask.nxv8f32.f16(
|
||||
<vscale x 8 x float>,
|
||||
half,
|
||||
<vscale x 8 x half>,
|
||||
<vscale x 8 x i1>,
|
||||
i64);
|
||||
|
||||
define <vscale x 8 x float> @intrinsic_vfwnmsac_mask_vf_nxv8f32_f16_nxv8f16(<vscale x 8 x float> %0, half %1, <vscale x 8 x half> %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
|
||||
; CHECK-LABEL: intrinsic_vfwnmsac_mask_vf_nxv8f32_f16_nxv8f16:
|
||||
; CHECK: # %bb.0: # %entry
|
||||
; CHECK-NEXT: fmv.h.x ft0, a0
|
||||
; CHECK-NEXT: vsetvli a0, a1, e16,m2,ta,mu
|
||||
; CHECK-NEXT: vfwnmsac.vf v16, ft0, v20, v0.t
|
||||
; CHECK-NEXT: jalr zero, 0(ra)
|
||||
entry:
|
||||
%a = call <vscale x 8 x float> @llvm.riscv.vfwnmsac.mask.nxv8f32.f16(
|
||||
<vscale x 8 x float> %0,
|
||||
half %1,
|
||||
<vscale x 8 x half> %2,
|
||||
<vscale x 8 x i1> %3,
|
||||
i64 %4)
|
||||
|
||||
ret <vscale x 8 x float> %a
|
||||
}
|
||||
|
||||
declare <vscale x 16 x float> @llvm.riscv.vfwnmsac.nxv16f32.f16(
|
||||
<vscale x 16 x float>,
|
||||
half,
|
||||
<vscale x 16 x half>,
|
||||
i64);
|
||||
|
||||
define <vscale x 16 x float> @intrinsic_vfwnmsac_vf_nxv16f32_f16_nxv16f16(<vscale x 16 x float> %0, half %1, <vscale x 16 x half> %2, i64 %3) nounwind {
|
||||
; CHECK-LABEL: intrinsic_vfwnmsac_vf_nxv16f32_f16_nxv16f16:
|
||||
; CHECK: # %bb.0: # %entry
|
||||
; CHECK-NEXT: vsetvli a3, zero, e16,m4,ta,mu
|
||||
; CHECK-NEXT: vle16.v v28, (a1)
|
||||
; CHECK-NEXT: fmv.h.x ft0, a0
|
||||
; CHECK-NEXT: vsetvli a0, a2, e16,m4,ta,mu
|
||||
; CHECK-NEXT: vfwnmsac.vf v16, ft0, v28
|
||||
; CHECK-NEXT: jalr zero, 0(ra)
|
||||
entry:
|
||||
%a = call <vscale x 16 x float> @llvm.riscv.vfwnmsac.nxv16f32.f16(
|
||||
<vscale x 16 x float> %0,
|
||||
half %1,
|
||||
<vscale x 16 x half> %2,
|
||||
i64 %3)
|
||||
|
||||
ret <vscale x 16 x float> %a
|
||||
}
|
||||
|
||||
declare <vscale x 16 x float> @llvm.riscv.vfwnmsac.mask.nxv16f32.f16(
|
||||
<vscale x 16 x float>,
|
||||
half,
|
||||
<vscale x 16 x half>,
|
||||
<vscale x 16 x i1>,
|
||||
i64);
|
||||
|
||||
define <vscale x 16 x float> @intrinsic_vfwnmsac_mask_vf_nxv16f32_f16_nxv16f16(<vscale x 16 x float> %0, half %1, <vscale x 16 x half> %2, <vscale x 16 x i1> %3, i64 %4) nounwind {
|
||||
; CHECK-LABEL: intrinsic_vfwnmsac_mask_vf_nxv16f32_f16_nxv16f16:
|
||||
; CHECK: # %bb.0: # %entry
|
||||
; CHECK-NEXT: vsetvli a3, zero, e16,m4,ta,mu
|
||||
; CHECK-NEXT: vle16.v v28, (a1)
|
||||
; CHECK-NEXT: fmv.h.x ft0, a0
|
||||
; CHECK-NEXT: vsetvli a0, a2, e16,m4,ta,mu
|
||||
; CHECK-NEXT: vfwnmsac.vf v16, ft0, v28, v0.t
|
||||
; CHECK-NEXT: jalr zero, 0(ra)
|
||||
entry:
|
||||
%a = call <vscale x 16 x float> @llvm.riscv.vfwnmsac.mask.nxv16f32.f16(
|
||||
<vscale x 16 x float> %0,
|
||||
half %1,
|
||||
<vscale x 16 x half> %2,
|
||||
<vscale x 16 x i1> %3,
|
||||
i64 %4)
|
||||
|
||||
ret <vscale x 16 x float> %a
|
||||
}
|
||||
|
||||
declare <vscale x 1 x double> @llvm.riscv.vfwnmsac.nxv1f64.f32(
|
||||
<vscale x 1 x double>,
|
||||
float,
|
||||
<vscale x 1 x float>,
|
||||
i64);
|
||||
|
||||
define <vscale x 1 x double> @intrinsic_vfwnmsac_vf_nxv1f64_f32_nxv1f32(<vscale x 1 x double> %0, float %1, <vscale x 1 x float> %2, i64 %3) nounwind {
|
||||
; CHECK-LABEL: intrinsic_vfwnmsac_vf_nxv1f64_f32_nxv1f32:
|
||||
; CHECK: # %bb.0: # %entry
|
||||
; CHECK-NEXT: fmv.w.x ft0, a0
|
||||
; CHECK-NEXT: vsetvli a0, a1, e32,mf2,ta,mu
|
||||
; CHECK-NEXT: vfwnmsac.vf v16, ft0, v17
|
||||
; CHECK-NEXT: jalr zero, 0(ra)
|
||||
entry:
|
||||
%a = call <vscale x 1 x double> @llvm.riscv.vfwnmsac.nxv1f64.f32(
|
||||
<vscale x 1 x double> %0,
|
||||
float %1,
|
||||
<vscale x 1 x float> %2,
|
||||
i64 %3)
|
||||
|
||||
ret <vscale x 1 x double> %a
|
||||
}
|
||||
|
||||
declare <vscale x 1 x double> @llvm.riscv.vfwnmsac.mask.nxv1f64.f32(
|
||||
<vscale x 1 x double>,
|
||||
float,
|
||||
<vscale x 1 x float>,
|
||||
<vscale x 1 x i1>,
|
||||
i64);
|
||||
|
||||
define <vscale x 1 x double> @intrinsic_vfwnmsac_mask_vf_nxv1f64_f32_nxv1f32(<vscale x 1 x double> %0, float %1, <vscale x 1 x float> %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
|
||||
; CHECK-LABEL: intrinsic_vfwnmsac_mask_vf_nxv1f64_f32_nxv1f32:
|
||||
; CHECK: # %bb.0: # %entry
|
||||
; CHECK-NEXT: fmv.w.x ft0, a0
|
||||
; CHECK-NEXT: vsetvli a0, a1, e32,mf2,ta,mu
|
||||
; CHECK-NEXT: vfwnmsac.vf v16, ft0, v17, v0.t
|
||||
; CHECK-NEXT: jalr zero, 0(ra)
|
||||
entry:
|
||||
%a = call <vscale x 1 x double> @llvm.riscv.vfwnmsac.mask.nxv1f64.f32(
|
||||
<vscale x 1 x double> %0,
|
||||
float %1,
|
||||
<vscale x 1 x float> %2,
|
||||
<vscale x 1 x i1> %3,
|
||||
i64 %4)
|
||||
|
||||
ret <vscale x 1 x double> %a
|
||||
}
|
||||
|
||||
declare <vscale x 2 x double> @llvm.riscv.vfwnmsac.nxv2f64.f32(
|
||||
<vscale x 2 x double>,
|
||||
float,
|
||||
<vscale x 2 x float>,
|
||||
i64);
|
||||
|
||||
define <vscale x 2 x double> @intrinsic_vfwnmsac_vf_nxv2f64_f32_nxv2f32(<vscale x 2 x double> %0, float %1, <vscale x 2 x float> %2, i64 %3) nounwind {
|
||||
; CHECK-LABEL: intrinsic_vfwnmsac_vf_nxv2f64_f32_nxv2f32:
|
||||
; CHECK: # %bb.0: # %entry
|
||||
; CHECK-NEXT: fmv.w.x ft0, a0
|
||||
; CHECK-NEXT: vsetvli a0, a1, e32,m1,ta,mu
|
||||
; CHECK-NEXT: vfwnmsac.vf v16, ft0, v18
|
||||
; CHECK-NEXT: jalr zero, 0(ra)
|
||||
entry:
|
||||
%a = call <vscale x 2 x double> @llvm.riscv.vfwnmsac.nxv2f64.f32(
|
||||
<vscale x 2 x double> %0,
|
||||
float %1,
|
||||
<vscale x 2 x float> %2,
|
||||
i64 %3)
|
||||
|
||||
ret <vscale x 2 x double> %a
|
||||
}
|
||||
|
||||
declare <vscale x 2 x double> @llvm.riscv.vfwnmsac.mask.nxv2f64.f32(
|
||||
<vscale x 2 x double>,
|
||||
float,
|
||||
<vscale x 2 x float>,
|
||||
<vscale x 2 x i1>,
|
||||
i64);
|
||||
|
||||
define <vscale x 2 x double> @intrinsic_vfwnmsac_mask_vf_nxv2f64_f32_nxv2f32(<vscale x 2 x double> %0, float %1, <vscale x 2 x float> %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
|
||||
; CHECK-LABEL: intrinsic_vfwnmsac_mask_vf_nxv2f64_f32_nxv2f32:
|
||||
; CHECK: # %bb.0: # %entry
|
||||
; CHECK-NEXT: fmv.w.x ft0, a0
|
||||
; CHECK-NEXT: vsetvli a0, a1, e32,m1,ta,mu
|
||||
; CHECK-NEXT: vfwnmsac.vf v16, ft0, v18, v0.t
|
||||
; CHECK-NEXT: jalr zero, 0(ra)
|
||||
entry:
|
||||
%a = call <vscale x 2 x double> @llvm.riscv.vfwnmsac.mask.nxv2f64.f32(
|
||||
<vscale x 2 x double> %0,
|
||||
float %1,
|
||||
<vscale x 2 x float> %2,
|
||||
<vscale x 2 x i1> %3,
|
||||
i64 %4)
|
||||
|
||||
ret <vscale x 2 x double> %a
|
||||
}
|
||||
|
||||
declare <vscale x 4 x double> @llvm.riscv.vfwnmsac.nxv4f64.f32(
|
||||
<vscale x 4 x double>,
|
||||
float,
|
||||
<vscale x 4 x float>,
|
||||
i64);
|
||||
|
||||
define <vscale x 4 x double> @intrinsic_vfwnmsac_vf_nxv4f64_f32_nxv4f32(<vscale x 4 x double> %0, float %1, <vscale x 4 x float> %2, i64 %3) nounwind {
|
||||
; CHECK-LABEL: intrinsic_vfwnmsac_vf_nxv4f64_f32_nxv4f32:
|
||||
; CHECK: # %bb.0: # %entry
|
||||
; CHECK-NEXT: fmv.w.x ft0, a0
|
||||
; CHECK-NEXT: vsetvli a0, a1, e32,m2,ta,mu
|
||||
; CHECK-NEXT: vfwnmsac.vf v16, ft0, v20
|
||||
; CHECK-NEXT: jalr zero, 0(ra)
|
||||
entry:
|
||||
%a = call <vscale x 4 x double> @llvm.riscv.vfwnmsac.nxv4f64.f32(
|
||||
<vscale x 4 x double> %0,
|
||||
float %1,
|
||||
<vscale x 4 x float> %2,
|
||||
i64 %3)
|
||||
|
||||
ret <vscale x 4 x double> %a
|
||||
}
|
||||
|
||||
declare <vscale x 4 x double> @llvm.riscv.vfwnmsac.mask.nxv4f64.f32(
|
||||
<vscale x 4 x double>,
|
||||
float,
|
||||
<vscale x 4 x float>,
|
||||
<vscale x 4 x i1>,
|
||||
i64);
|
||||
|
||||
define <vscale x 4 x double> @intrinsic_vfwnmsac_mask_vf_nxv4f64_f32_nxv4f32(<vscale x 4 x double> %0, float %1, <vscale x 4 x float> %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
|
||||
; CHECK-LABEL: intrinsic_vfwnmsac_mask_vf_nxv4f64_f32_nxv4f32:
|
||||
; CHECK: # %bb.0: # %entry
|
||||
; CHECK-NEXT: fmv.w.x ft0, a0
|
||||
; CHECK-NEXT: vsetvli a0, a1, e32,m2,ta,mu
|
||||
; CHECK-NEXT: vfwnmsac.vf v16, ft0, v20, v0.t
|
||||
; CHECK-NEXT: jalr zero, 0(ra)
|
||||
entry:
|
||||
%a = call <vscale x 4 x double> @llvm.riscv.vfwnmsac.mask.nxv4f64.f32(
|
||||
<vscale x 4 x double> %0,
|
||||
float %1,
|
||||
<vscale x 4 x float> %2,
|
||||
<vscale x 4 x i1> %3,
|
||||
i64 %4)
|
||||
|
||||
ret <vscale x 4 x double> %a
|
||||
}
|
||||
|
||||
declare <vscale x 8 x double> @llvm.riscv.vfwnmsac.nxv8f64.f32(
|
||||
<vscale x 8 x double>,
|
||||
float,
|
||||
<vscale x 8 x float>,
|
||||
i64);
|
||||
|
||||
define <vscale x 8 x double> @intrinsic_vfwnmsac_vf_nxv8f64_f32_nxv8f32(<vscale x 8 x double> %0, float %1, <vscale x 8 x float> %2, i64 %3) nounwind {
|
||||
; CHECK-LABEL: intrinsic_vfwnmsac_vf_nxv8f64_f32_nxv8f32:
|
||||
; CHECK: # %bb.0: # %entry
|
||||
; CHECK-NEXT: vsetvli a3, zero, e32,m4,ta,mu
|
||||
; CHECK-NEXT: vle32.v v28, (a1)
|
||||
; CHECK-NEXT: fmv.w.x ft0, a0
|
||||
; CHECK-NEXT: vsetvli a0, a2, e32,m4,ta,mu
|
||||
; CHECK-NEXT: vfwnmsac.vf v16, ft0, v28
|
||||
; CHECK-NEXT: jalr zero, 0(ra)
|
||||
entry:
|
||||
%a = call <vscale x 8 x double> @llvm.riscv.vfwnmsac.nxv8f64.f32(
|
||||
<vscale x 8 x double> %0,
|
||||
float %1,
|
||||
<vscale x 8 x float> %2,
|
||||
i64 %3)
|
||||
|
||||
ret <vscale x 8 x double> %a
|
||||
}
|
||||
|
||||
declare <vscale x 8 x double> @llvm.riscv.vfwnmsac.mask.nxv8f64.f32(
|
||||
<vscale x 8 x double>,
|
||||
float,
|
||||
<vscale x 8 x float>,
|
||||
<vscale x 8 x i1>,
|
||||
i64);
|
||||
|
||||
define <vscale x 8 x double> @intrinsic_vfwnmsac_mask_vf_nxv8f64_f32_nxv8f32(<vscale x 8 x double> %0, float %1, <vscale x 8 x float> %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
|
||||
; CHECK-LABEL: intrinsic_vfwnmsac_mask_vf_nxv8f64_f32_nxv8f32:
|
||||
; CHECK: # %bb.0: # %entry
|
||||
; CHECK-NEXT: vsetvli a3, zero, e32,m4,ta,mu
|
||||
; CHECK-NEXT: vle32.v v28, (a1)
|
||||
; CHECK-NEXT: fmv.w.x ft0, a0
|
||||
; CHECK-NEXT: vsetvli a0, a2, e32,m4,ta,mu
|
||||
; CHECK-NEXT: vfwnmsac.vf v16, ft0, v28, v0.t
|
||||
; CHECK-NEXT: jalr zero, 0(ra)
|
||||
entry:
|
||||
%a = call <vscale x 8 x double> @llvm.riscv.vfwnmsac.mask.nxv8f64.f32(
|
||||
<vscale x 8 x double> %0,
|
||||
float %1,
|
||||
<vscale x 8 x float> %2,
|
||||
<vscale x 8 x i1> %3,
|
||||
i64 %4)
|
||||
|
||||
ret <vscale x 8 x double> %a
|
||||
}
|
||||
Loading…
Reference in New Issue
Block a user