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[x86] fix formatting; NFC
llvm-svn: 288045
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4f50e2021b
commit
07d0147189
@ -30007,7 +30007,7 @@ static SDValue combineOr(SDNode *N, SelectionDAG &DAG,
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return SDValue();
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}
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// Generate NEG and CMOV for integer abs.
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/// Generate NEG and CMOV for integer abs.
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static SDValue combineIntegerAbs(SDNode *N, SelectionDAG &DAG) {
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EVT VT = N->getValueType(0);
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@ -30023,21 +30023,19 @@ static SDValue combineIntegerAbs(SDNode *N, SelectionDAG &DAG) {
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// Check pattern of XOR(ADD(X,Y), Y) where Y is SRA(X, size(X)-1)
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// and change it to SUB and CMOV.
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if (VT.isInteger() && N->getOpcode() == ISD::XOR &&
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N0.getOpcode() == ISD::ADD &&
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N0.getOperand(1) == N1 &&
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N1.getOpcode() == ISD::SRA &&
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N1.getOperand(0) == N0.getOperand(0))
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if (ConstantSDNode *Y1C = dyn_cast<ConstantSDNode>(N1.getOperand(1)))
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if (Y1C->getAPIntValue() == VT.getSizeInBits()-1) {
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N0.getOpcode() == ISD::ADD && N0.getOperand(1) == N1 &&
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N1.getOpcode() == ISD::SRA && N1.getOperand(0) == N0.getOperand(0)) {
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auto *Y1C = dyn_cast<ConstantSDNode>(N1.getOperand(1));
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if (Y1C && Y1C->getAPIntValue() == VT.getSizeInBits() - 1) {
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// Generate SUB & CMOV.
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SDValue Neg = DAG.getNode(X86ISD::SUB, DL, DAG.getVTList(VT, MVT::i32),
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DAG.getConstant(0, DL, VT), N0.getOperand(0));
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SDValue Ops[] = {N0.getOperand(0), Neg,
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DAG.getConstant(X86::COND_GE, DL, MVT::i8),
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SDValue(Neg.getNode(), 1)};
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return DAG.getNode(X86ISD::CMOV, DL, DAG.getVTList(VT, MVT::Glue), Ops);
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}
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}
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return SDValue();
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}
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