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Thread MCSubtargetInfo through Target::createMCAsmBackend

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Currently it's not possible to access MCSubtargetInfo from a TgtMCAsmBackend. 
D20830 threaded an MCSubtargetInfo reference through 
MCAsmBackend::relaxInstruction, but this isn't the only function that would 
benefit from access. This patch removes the Triple and CPUString arguments 
from createMCAsmBackend and replaces them with MCSubtargetInfo.

This patch just changes the interface without making any intentional 
functional changes. Once in, several cleanups are possible:
* Get rid of the awkward MCSubtargetInfo handling in ARMAsmBackend
* Support 16-bit instructions when valid in MipsAsmBackend::writeNopData
* Get rid of the CPU string parsing in X86AsmBackend and just use a SubtargetFeature for HasNopl
* Emit 16-bit nops in RISCVAsmBackend::writeNopData if the compressed instruction set extension is enabled (see D41221)

This change initially exposed PR35686, which has since been resolved in r321026.

Differential Revision: https://reviews.llvm.org/D41349

llvm-svn: 321692
This commit is contained in:
Alex Bradbury 2018-01-03 08:53:05 +00:00
parent cffbe7b56d
commit 07f78926fb
30 changed files with 116 additions and 101 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

17
include/llvm/Support/TargetRegistry.h
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@ -123,8 +123,8 @@ public:
using AsmPrinterCtorTy = AsmPrinter *(*)( using AsmPrinterCtorTy = AsmPrinter *(*)(
TargetMachine &TM, std::unique_ptr<MCStreamer> &&Streamer); TargetMachine &TM, std::unique_ptr<MCStreamer> &&Streamer);
using MCAsmBackendCtorTy = MCAsmBackend *(*)(const Target &T, using MCAsmBackendCtorTy = MCAsmBackend *(*)(const Target &T,
const MCSubtargetInfo &STI,
const MCRegisterInfo &MRI, const MCRegisterInfo &MRI,
const Triple &TT, StringRef CPU,
const MCTargetOptions &Options); const MCTargetOptions &Options);
using MCAsmParserCtorTy = MCTargetAsmParser *(*)( using MCAsmParserCtorTy = MCTargetAsmParser *(*)(
const MCSubtargetInfo &STI, MCAsmParser &P, const MCInstrInfo &MII, const MCSubtargetInfo &STI, MCAsmParser &P, const MCInstrInfo &MII,
@ -383,13 +383,12 @@ public:
/// createMCAsmBackend - Create a target specific assembly parser. /// createMCAsmBackend - Create a target specific assembly parser.
/// ///
/// \param TheTriple The target triple string. /// \param TheTriple The target triple string.
MCAsmBackend *createMCAsmBackend(const MCRegisterInfo &MRI, MCAsmBackend *createMCAsmBackend(const MCSubtargetInfo &STI,
StringRef TheTriple, StringRef CPU, const MCRegisterInfo &MRI,
const MCTargetOptions &Options) const MCTargetOptions &Options) const {
const {
if (!MCAsmBackendCtorFn) if (!MCAsmBackendCtorFn)
return nullptr; return nullptr;
return MCAsmBackendCtorFn(*this, MRI, Triple(TheTriple), CPU, Options); return MCAsmBackendCtorFn(*this, STI, MRI, Options);
} }
/// createMCAsmParser - Create a target specific assembly parser. /// createMCAsmParser - Create a target specific assembly parser.
@ -1106,10 +1105,10 @@ template <class MCAsmBackendImpl> struct RegisterMCAsmBackend {
} }
private: private:
static MCAsmBackend *Allocator(const Target &T, const MCRegisterInfo &MRI, static MCAsmBackend *Allocator(const Target &T, const MCSubtargetInfo &STI,
const Triple &TheTriple, StringRef CPU, const MCRegisterInfo &MRI,
const MCTargetOptions &Options) { const MCTargetOptions &Options) {
return new MCAsmBackendImpl(T, MRI, TheTriple, CPU); return new MCAsmBackendImpl(T, STI, MRI);
} }
}; };

11
lib/CodeGen/LLVMTargetMachine.cpp
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@ -136,8 +136,7 @@ bool LLVMTargetMachine::addAsmPrinter(PassManagerBase &PM,
MCE = getTarget().createMCCodeEmitter(MII, MRI, Context); MCE = getTarget().createMCCodeEmitter(MII, MRI, Context);
MCAsmBackend *MAB = MCAsmBackend *MAB =
getTarget().createMCAsmBackend(MRI, getTargetTriple().str(), TargetCPU, getTarget().createMCAsmBackend(STI, MRI, Options.MCOptions);
Options.MCOptions);
auto FOut = llvm::make_unique<formatted_raw_ostream>(Out); auto FOut = llvm::make_unique<formatted_raw_ostream>(Out);
MCStreamer *S = getTarget().createAsmStreamer( MCStreamer *S = getTarget().createAsmStreamer(
Context, std::move(FOut), Options.MCOptions.AsmVerbose, Context, std::move(FOut), Options.MCOptions.AsmVerbose,
@ -151,8 +150,7 @@ bool LLVMTargetMachine::addAsmPrinter(PassManagerBase &PM,
// emission fails. // emission fails.
MCCodeEmitter *MCE = getTarget().createMCCodeEmitter(MII, MRI, Context); MCCodeEmitter *MCE = getTarget().createMCCodeEmitter(MII, MRI, Context);
MCAsmBackend *MAB = MCAsmBackend *MAB =
getTarget().createMCAsmBackend(MRI, getTargetTriple().str(), TargetCPU, getTarget().createMCAsmBackend(STI, MRI, Options.MCOptions);
Options.MCOptions);
if (!MCE || !MAB) if (!MCE || !MAB)
return true; return true;
@ -225,17 +223,16 @@ bool LLVMTargetMachine::addPassesToEmitMC(PassManagerBase &PM, MCContext *&Ctx,
// Create the code emitter for the target if it exists. If not, .o file // Create the code emitter for the target if it exists. If not, .o file
// emission fails. // emission fails.
const MCSubtargetInfo &STI = *getMCSubtargetInfo();
const MCRegisterInfo &MRI = *getMCRegisterInfo(); const MCRegisterInfo &MRI = *getMCRegisterInfo();
MCCodeEmitter *MCE = MCCodeEmitter *MCE =
getTarget().createMCCodeEmitter(*getMCInstrInfo(), MRI, *Ctx); getTarget().createMCCodeEmitter(*getMCInstrInfo(), MRI, *Ctx);
MCAsmBackend *MAB = MCAsmBackend *MAB =
getTarget().createMCAsmBackend(MRI, getTargetTriple().str(), TargetCPU, getTarget().createMCAsmBackend(STI, MRI, Options.MCOptions);
Options.MCOptions);
if (!MCE || !MAB) if (!MCE || !MAB)
return true; return true;
const Triple &T = getTargetTriple(); const Triple &T = getTargetTriple();
const MCSubtargetInfo &STI = *getMCSubtargetInfo();
std::unique_ptr<MCStreamer> AsmStreamer(getTarget().createMCObjectStreamer( std::unique_ptr<MCStreamer> AsmStreamer(getTarget().createMCObjectStreamer(
T, *Ctx, std::unique_ptr<MCAsmBackend>(MAB), Out, T, *Ctx, std::unique_ptr<MCAsmBackend>(MAB), Out,
std::unique_ptr<MCCodeEmitter>(MCE), STI, Options.MCOptions.MCRelaxAll, std::unique_ptr<MCCodeEmitter>(MCE), STI, Options.MCOptions.MCRelaxAll,

8
lib/Target/AArch64/MCTargetDesc/AArch64AsmBackend.cpp
View File

@ -605,10 +605,10 @@ public:
} }
MCAsmBackend *llvm::createAArch64leAsmBackend(const Target &T, MCAsmBackend *llvm::createAArch64leAsmBackend(const Target &T,
const MCSubtargetInfo &STI,
const MCRegisterInfo &MRI, const MCRegisterInfo &MRI,
const Triple &TheTriple,
StringRef CPU,
const MCTargetOptions &Options) { const MCTargetOptions &Options) {
const Triple &TheTriple = STI.getTargetTriple();
if (TheTriple.isOSBinFormatMachO()) if (TheTriple.isOSBinFormatMachO())
return new DarwinAArch64AsmBackend(T, TheTriple, MRI); return new DarwinAArch64AsmBackend(T, TheTriple, MRI);
@ -624,10 +624,10 @@ MCAsmBackend *llvm::createAArch64leAsmBackend(const Target &T,
} }
MCAsmBackend *llvm::createAArch64beAsmBackend(const Target &T, MCAsmBackend *llvm::createAArch64beAsmBackend(const Target &T,
const MCSubtargetInfo &STI,
const MCRegisterInfo &MRI, const MCRegisterInfo &MRI,
const Triple &TheTriple,
StringRef CPU,
const MCTargetOptions &Options) { const MCTargetOptions &Options) {
const Triple &TheTriple = STI.getTargetTriple();
assert(TheTriple.isOSBinFormatELF() && assert(TheTriple.isOSBinFormatELF() &&
"Big endian is only supported for ELF targets!"); "Big endian is only supported for ELF targets!");
uint8_t OSABI = MCELFObjectTargetWriter::getOSABI(TheTriple.getOS()); uint8_t OSABI = MCELFObjectTargetWriter::getOSABI(TheTriple.getOS());

4
lib/Target/AArch64/MCTargetDesc/AArch64MCTargetDesc.h
View File

@ -45,12 +45,12 @@ MCCodeEmitter *createAArch64MCCodeEmitter(const MCInstrInfo &MCII,
const MCRegisterInfo &MRI, const MCRegisterInfo &MRI,
MCContext &Ctx); MCContext &Ctx);
MCAsmBackend *createAArch64leAsmBackend(const Target &T, MCAsmBackend *createAArch64leAsmBackend(const Target &T,
const MCSubtargetInfo &STI,
const MCRegisterInfo &MRI, const MCRegisterInfo &MRI,
const Triple &TT, StringRef CPU,
const MCTargetOptions &Options); const MCTargetOptions &Options);
MCAsmBackend *createAArch64beAsmBackend(const Target &T, MCAsmBackend *createAArch64beAsmBackend(const Target &T,
const MCSubtargetInfo &STI,
const MCRegisterInfo &MRI, const MCRegisterInfo &MRI,
const Triple &TT, StringRef CPU,
const MCTargetOptions &Options); const MCTargetOptions &Options);
std::unique_ptr<MCObjectWriter> std::unique_ptr<MCObjectWriter>

4
lib/Target/AMDGPU/MCTargetDesc/AMDGPUAsmBackend.cpp
View File

@ -198,9 +198,9 @@ public:
} // end anonymous namespace } // end anonymous namespace
MCAsmBackend *llvm::createAMDGPUAsmBackend(const Target &T, MCAsmBackend *llvm::createAMDGPUAsmBackend(const Target &T,
const MCSubtargetInfo &STI,
const MCRegisterInfo &MRI, const MCRegisterInfo &MRI,
const Triple &TT, StringRef CPU,
const MCTargetOptions &Options) { const MCTargetOptions &Options) {
// Use 64-bit ELF for amdgcn // Use 64-bit ELF for amdgcn
return new ELFAMDGPUAsmBackend(T, TT); return new ELFAMDGPUAsmBackend(T, STI.getTargetTriple());
} }

5
lib/Target/AMDGPU/MCTargetDesc/AMDGPUMCTargetDesc.h
View File

@ -45,8 +45,9 @@ MCCodeEmitter *createSIMCCodeEmitter(const MCInstrInfo &MCII,
const MCRegisterInfo &MRI, const MCRegisterInfo &MRI,
MCContext &Ctx); MCContext &Ctx);
MCAsmBackend *createAMDGPUAsmBackend(const Target &T, const MCRegisterInfo &MRI, MCAsmBackend *createAMDGPUAsmBackend(const Target &T,
const Triple &TT, StringRef CPU, const MCSubtargetInfo &STI,
const MCRegisterInfo &MRI,
const MCTargetOptions &Options); const MCTargetOptions &Options);
std::unique_ptr<MCObjectWriter> std::unique_ptr<MCObjectWriter>

20
lib/Target/ARM/MCTargetDesc/ARMAsmBackend.cpp
View File

@ -1176,29 +1176,33 @@ MCAsmBackend *llvm::createARMAsmBackend(const Target &T,
} }
MCAsmBackend *llvm::createARMLEAsmBackend(const Target &T, MCAsmBackend *llvm::createARMLEAsmBackend(const Target &T,
const MCSubtargetInfo &STI,
const MCRegisterInfo &MRI, const MCRegisterInfo &MRI,
const Triple &TT, StringRef CPU,
const MCTargetOptions &Options) { const MCTargetOptions &Options) {
return createARMAsmBackend(T, MRI, TT, CPU, Options, true); return createARMAsmBackend(T, MRI, STI.getTargetTriple(), STI.getCPU(),
Options, true);
} }
MCAsmBackend *llvm::createARMBEAsmBackend(const Target &T, MCAsmBackend *llvm::createARMBEAsmBackend(const Target &T,
const MCSubtargetInfo &STI,
const MCRegisterInfo &MRI, const MCRegisterInfo &MRI,
const Triple &TT, StringRef CPU,
const MCTargetOptions &Options) { const MCTargetOptions &Options) {
return createARMAsmBackend(T, MRI, TT, CPU, Options, false); return createARMAsmBackend(T, MRI, STI.getTargetTriple(), STI.getCPU(),
Options, false);
} }
MCAsmBackend *llvm::createThumbLEAsmBackend(const Target &T, MCAsmBackend *llvm::createThumbLEAsmBackend(const Target &T,
const MCSubtargetInfo &STI,
const MCRegisterInfo &MRI, const MCRegisterInfo &MRI,
const Triple &TT, StringRef CPU,
const MCTargetOptions &Options) { const MCTargetOptions &Options) {
return createARMAsmBackend(T, MRI, TT, CPU, Options, true); return createARMAsmBackend(T, MRI, STI.getTargetTriple(), STI.getCPU(),
Options, true);
} }
MCAsmBackend *llvm::createThumbBEAsmBackend(const Target &T, MCAsmBackend *llvm::createThumbBEAsmBackend(const Target &T,
const MCSubtargetInfo &STI,
const MCRegisterInfo &MRI, const MCRegisterInfo &MRI,
const Triple &TT, StringRef CPU,
const MCTargetOptions &Options) { const MCTargetOptions &Options) {
return createARMAsmBackend(T, MRI, TT, CPU, Options, false); return createARMAsmBackend(T, MRI, STI.getTargetTriple(), STI.getCPU(),
Options, false);
} }

12
lib/Target/ARM/MCTargetDesc/ARMMCTargetDesc.h
View File

@ -73,22 +73,22 @@ MCAsmBackend *createARMAsmBackend(const Target &T, const MCRegisterInfo &MRI,
const MCTargetOptions &Options, const MCTargetOptions &Options,
bool IsLittleEndian); bool IsLittleEndian);
MCAsmBackend *createARMLEAsmBackend(const Target &T, const MCRegisterInfo &MRI, MCAsmBackend *createARMLEAsmBackend(const Target &T, const MCSubtargetInfo &STI,
const Triple &TT, StringRef CPU, const MCRegisterInfo &MRI,
const MCTargetOptions &Options); const MCTargetOptions &Options);
MCAsmBackend *createARMBEAsmBackend(const Target &T, const MCRegisterInfo &MRI, MCAsmBackend *createARMBEAsmBackend(const Target &T, const MCSubtargetInfo &STI,
const Triple &TT, StringRef CPU, const MCRegisterInfo &MRI,
const MCTargetOptions &Options); const MCTargetOptions &Options);
MCAsmBackend *createThumbLEAsmBackend(const Target &T, MCAsmBackend *createThumbLEAsmBackend(const Target &T,
const MCSubtargetInfo &STI,
const MCRegisterInfo &MRI, const MCRegisterInfo &MRI,
const Triple &TT, StringRef CPU,
const MCTargetOptions &Options); const MCTargetOptions &Options);
MCAsmBackend *createThumbBEAsmBackend(const Target &T, MCAsmBackend *createThumbBEAsmBackend(const Target &T,
const MCSubtargetInfo &STI,
const MCRegisterInfo &MRI, const MCRegisterInfo &MRI,
const Triple &TT, StringRef CPU,
const MCTargetOptions &Options); const MCTargetOptions &Options);
// Construct a PE/COFF machine code streamer which will generate a PE/COFF // Construct a PE/COFF machine code streamer which will generate a PE/COFF

8
lib/Target/BPF/MCTargetDesc/BPFAsmBackend.cpp
View File

@ -104,15 +104,15 @@ BPFAsmBackend::createObjectWriter(raw_pwrite_stream &OS) const {
} }
MCAsmBackend *llvm::createBPFAsmBackend(const Target &T, MCAsmBackend *llvm::createBPFAsmBackend(const Target &T,
const MCSubtargetInfo &STI,
const MCRegisterInfo &MRI, const MCRegisterInfo &MRI,
const Triple &TT, StringRef CPU, const MCTargetOptions &) {
const MCTargetOptions&) {
return new BPFAsmBackend(/*IsLittleEndian=*/true); return new BPFAsmBackend(/*IsLittleEndian=*/true);
} }
MCAsmBackend *llvm::createBPFbeAsmBackend(const Target &T, MCAsmBackend *llvm::createBPFbeAsmBackend(const Target &T,
const MCSubtargetInfo &STI,
const MCRegisterInfo &MRI, const MCRegisterInfo &MRI,
const Triple &TT, StringRef CPU, const MCTargetOptions &) {
const MCTargetOptions&) {
return new BPFAsmBackend(/*IsLittleEndian=*/false); return new BPFAsmBackend(/*IsLittleEndian=*/false);
} }

8
lib/Target/BPF/MCTargetDesc/BPFMCTargetDesc.h
View File

@ -45,11 +45,11 @@ MCCodeEmitter *createBPFbeMCCodeEmitter(const MCInstrInfo &MCII,
const MCRegisterInfo &MRI, const MCRegisterInfo &MRI,
MCContext &Ctx); MCContext &Ctx);
MCAsmBackend *createBPFAsmBackend(const Target &T, const MCRegisterInfo &MRI, MCAsmBackend *createBPFAsmBackend(const Target &T, const MCSubtargetInfo &STI,
const Triple &TT, StringRef CPU, const MCRegisterInfo &MRI,
const MCTargetOptions &Options); const MCTargetOptions &Options);
MCAsmBackend *createBPFbeAsmBackend(const Target &T, const MCRegisterInfo &MRI, MCAsmBackend *createBPFbeAsmBackend(const Target &T, const MCSubtargetInfo &STI,
const Triple &TT, StringRef CPU, const MCRegisterInfo &MRI,
const MCTargetOptions &Options); const MCTargetOptions &Options);
std::unique_ptr<MCObjectWriter> createBPFELFObjectWriter(raw_pwrite_stream &OS, std::unique_ptr<MCObjectWriter> createBPFELFObjectWriter(raw_pwrite_stream &OS,

9
lib/Target/Hexagon/MCTargetDesc/HexagonAsmBackend.cpp
View File

@ -765,11 +765,12 @@ public:
// MCAsmBackend // MCAsmBackend
MCAsmBackend *llvm::createHexagonAsmBackend(Target const &T, MCAsmBackend *llvm::createHexagonAsmBackend(Target const &T,
MCRegisterInfo const & /*MRI*/, const MCSubtargetInfo &STI,
const Triple &TT, StringRef CPU, MCRegisterInfo const & /*MRI*/,
const MCTargetOptions &Options) { const MCTargetOptions &Options) {
const Triple &TT = STI.getTargetTriple();
uint8_t OSABI = MCELFObjectTargetWriter::getOSABI(TT.getOS()); uint8_t OSABI = MCELFObjectTargetWriter::getOSABI(TT.getOS());
StringRef CPUString = Hexagon_MC::selectHexagonCPU(CPU); StringRef CPUString = Hexagon_MC::selectHexagonCPU(STI.getCPU());
return new HexagonAsmBackend(T, TT, OSABI, CPUString); return new HexagonAsmBackend(T, TT, OSABI, CPUString);
} }

2
lib/Target/Hexagon/MCTargetDesc/HexagonMCTargetDesc.h
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@ -61,8 +61,8 @@ MCCodeEmitter *createHexagonMCCodeEmitter(const MCInstrInfo &MCII,
MCContext &MCT); MCContext &MCT);
MCAsmBackend *createHexagonAsmBackend(const Target &T, MCAsmBackend *createHexagonAsmBackend(const Target &T,
const MCSubtargetInfo &STI,
const MCRegisterInfo &MRI, const MCRegisterInfo &MRI,
const Triple &TT, StringRef CPU,
const MCTargetOptions &Options); const MCTargetOptions &Options);
std::unique_ptr<MCObjectWriter> std::unique_ptr<MCObjectWriter>

3
lib/Target/Lanai/MCTargetDesc/LanaiAsmBackend.cpp
View File

@ -165,9 +165,10 @@ LanaiAsmBackend::getFixupKindInfo(MCFixupKind Kind) const {
} // namespace } // namespace
MCAsmBackend *llvm::createLanaiAsmBackend(const Target &T, MCAsmBackend *llvm::createLanaiAsmBackend(const Target &T,
const MCSubtargetInfo &STI,
const MCRegisterInfo & /*MRI*/, const MCRegisterInfo & /*MRI*/,
const Triple &TT, StringRef /*CPU*/,
const MCTargetOptions & /*Options*/) { const MCTargetOptions & /*Options*/) {
const Triple &TT = STI.getTargetTriple();
if (!TT.isOSBinFormatELF()) if (!TT.isOSBinFormatELF())
llvm_unreachable("OS not supported"); llvm_unreachable("OS not supported");

4
lib/Target/Lanai/MCTargetDesc/LanaiMCTargetDesc.h
View File

@ -38,8 +38,8 @@ MCCodeEmitter *createLanaiMCCodeEmitter(const MCInstrInfo &MCII,
const MCRegisterInfo &MRI, const MCRegisterInfo &MRI,
MCContext &Ctx); MCContext &Ctx);
MCAsmBackend *createLanaiAsmBackend(const Target &T, const MCRegisterInfo &MRI, MCAsmBackend *createLanaiAsmBackend(const Target &T, const MCSubtargetInfo &STI,
const Triple &TheTriple, StringRef CPU, const MCRegisterInfo &MRI,
const MCTargetOptions &Options); const MCTargetOptions &Options);
std::unique_ptr<MCObjectWriter> std::unique_ptr<MCObjectWriter>

5
lib/Target/Mips/MCTargetDesc/MipsAsmBackend.cpp
View File

@ -476,8 +476,9 @@ bool MipsAsmBackend::writeNopData(uint64_t Count, MCObjectWriter *OW) const {
} }
MCAsmBackend *llvm::createMipsAsmBackend(const Target &T, MCAsmBackend *llvm::createMipsAsmBackend(const Target &T,
const MCSubtargetInfo &STI,
const MCRegisterInfo &MRI, const MCRegisterInfo &MRI,
const Triple &TT, StringRef CPU,
const MCTargetOptions &Options) { const MCTargetOptions &Options) {
return new MipsAsmBackend(T, MRI, TT, CPU, Options.ABIName == "n32"); return new MipsAsmBackend(T, MRI, STI.getTargetTriple(), STI.getCPU(),
Options.ABIName == "n32");
} }

4
lib/Target/Mips/MCTargetDesc/MipsMCTargetDesc.h
View File

@ -45,8 +45,8 @@ MCCodeEmitter *createMipsMCCodeEmitterEL(const MCInstrInfo &MCII,
const MCRegisterInfo &MRI, const MCRegisterInfo &MRI,
MCContext &Ctx); MCContext &Ctx);
MCAsmBackend *createMipsAsmBackend(const Target &T, const MCRegisterInfo &MRI, MCAsmBackend *createMipsAsmBackend(const Target &T, const MCSubtargetInfo &STI,
const Triple &TT, StringRef CPU, const MCRegisterInfo &MRI,
const MCTargetOptions &Options); const MCTargetOptions &Options);
std::unique_ptr<MCObjectWriter> std::unique_ptr<MCObjectWriter>

4
lib/Target/PowerPC/MCTargetDesc/PPCAsmBackend.cpp
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@ -18,6 +18,7 @@
#include "llvm/MC/MCMachObjectWriter.h" #include "llvm/MC/MCMachObjectWriter.h"
#include "llvm/MC/MCObjectWriter.h" #include "llvm/MC/MCObjectWriter.h"
#include "llvm/MC/MCSectionMachO.h" #include "llvm/MC/MCSectionMachO.h"
#include "llvm/MC/MCSubtargetInfo.h"
#include "llvm/MC/MCSymbolELF.h" #include "llvm/MC/MCSymbolELF.h"
#include "llvm/MC/MCValue.h" #include "llvm/MC/MCValue.h"
#include "llvm/Support/ErrorHandling.h" #include "llvm/Support/ErrorHandling.h"
@ -231,9 +232,10 @@ namespace {
} // end anonymous namespace } // end anonymous namespace
MCAsmBackend *llvm::createPPCAsmBackend(const Target &T, MCAsmBackend *llvm::createPPCAsmBackend(const Target &T,
const MCSubtargetInfo &STI,
const MCRegisterInfo &MRI, const MCRegisterInfo &MRI,
const Triple &TT, StringRef CPU,
const MCTargetOptions &Options) { const MCTargetOptions &Options) {
const Triple &TT = STI.getTargetTriple();
if (TT.isOSDarwin()) if (TT.isOSDarwin())
return new DarwinPPCAsmBackend(T); return new DarwinPPCAsmBackend(T);

5
lib/Target/PowerPC/MCTargetDesc/PPCMCTargetDesc.h
View File

@ -29,6 +29,7 @@ class MCContext;
class MCInstrInfo; class MCInstrInfo;
class MCObjectWriter; class MCObjectWriter;
class MCRegisterInfo; class MCRegisterInfo;
class MCSubtargetInfo;
class MCTargetOptions; class MCTargetOptions;
class Target; class Target;
class Triple; class Triple;
@ -43,8 +44,8 @@ MCCodeEmitter *createPPCMCCodeEmitter(const MCInstrInfo &MCII,
const MCRegisterInfo &MRI, const MCRegisterInfo &MRI,
MCContext &Ctx); MCContext &Ctx);
MCAsmBackend *createPPCAsmBackend(const Target &T, const MCRegisterInfo &MRI, MCAsmBackend *createPPCAsmBackend(const Target &T, const MCSubtargetInfo &STI,
const Triple &TT, StringRef CPU, const MCRegisterInfo &MRI,
const MCTargetOptions &Options); const MCTargetOptions &Options);
/// Construct an PPC ELF object writer. /// Construct an PPC ELF object writer.

3
lib/Target/RISCV/MCTargetDesc/RISCVAsmBackend.cpp
View File

@ -230,9 +230,10 @@ RISCVAsmBackend::createObjectWriter(raw_pwrite_stream &OS) const {
} // end anonymous namespace } // end anonymous namespace
MCAsmBackend *llvm::createRISCVAsmBackend(const Target &T, MCAsmBackend *llvm::createRISCVAsmBackend(const Target &T,
const MCSubtargetInfo &STI,
const MCRegisterInfo &MRI, const MCRegisterInfo &MRI,
const Triple &TT, StringRef CPU,
const MCTargetOptions &Options) { const MCTargetOptions &Options) {
const Triple &TT = STI.getTargetTriple();
uint8_t OSABI = MCELFObjectTargetWriter::getOSABI(TT.getOS()); uint8_t OSABI = MCELFObjectTargetWriter::getOSABI(TT.getOS());
return new RISCVAsmBackend(OSABI, TT.isArch64Bit()); return new RISCVAsmBackend(OSABI, TT.isArch64Bit());
} }

4
lib/Target/RISCV/MCTargetDesc/RISCVMCTargetDesc.h
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@ -40,8 +40,8 @@ MCCodeEmitter *createRISCVMCCodeEmitter(const MCInstrInfo &MCII,
const MCRegisterInfo &MRI, const MCRegisterInfo &MRI,
MCContext &Ctx); MCContext &Ctx);
MCAsmBackend *createRISCVAsmBackend(const Target &T, const MCRegisterInfo &MRI, MCAsmBackend *createRISCVAsmBackend(const Target &T, const MCSubtargetInfo &STI,
const Triple &TT, StringRef CPU, const MCRegisterInfo &MRI,
const MCTargetOptions &Options); const MCTargetOptions &Options);
std::unique_ptr<MCObjectWriter> std::unique_ptr<MCObjectWriter>

5
lib/Target/Sparc/MCTargetDesc/SparcAsmBackend.cpp
View File

@ -14,6 +14,7 @@
#include "llvm/MC/MCExpr.h" #include "llvm/MC/MCExpr.h"
#include "llvm/MC/MCFixupKindInfo.h" #include "llvm/MC/MCFixupKindInfo.h"
#include "llvm/MC/MCObjectWriter.h" #include "llvm/MC/MCObjectWriter.h"
#include "llvm/MC/MCSubtargetInfo.h"
#include "llvm/MC/MCValue.h" #include "llvm/MC/MCValue.h"
#include "llvm/Support/TargetRegistry.h" #include "llvm/Support/TargetRegistry.h"
@ -301,8 +302,8 @@ namespace {
} // end anonymous namespace } // end anonymous namespace
MCAsmBackend *llvm::createSparcAsmBackend(const Target &T, MCAsmBackend *llvm::createSparcAsmBackend(const Target &T,
const MCSubtargetInfo &STI,
const MCRegisterInfo &MRI, const MCRegisterInfo &MRI,
const Triple &TT, StringRef CPU,
const MCTargetOptions &Options) { const MCTargetOptions &Options) {
return new ELFSparcAsmBackend(T, TT.getOS()); return new ELFSparcAsmBackend(T, STI.getTargetTriple().getOS());
} }

4
lib/Target/Sparc/MCTargetDesc/SparcMCTargetDesc.h
View File

@ -40,8 +40,8 @@ Target &getTheSparcelTarget();
MCCodeEmitter *createSparcMCCodeEmitter(const MCInstrInfo &MCII, MCCodeEmitter *createSparcMCCodeEmitter(const MCInstrInfo &MCII,
const MCRegisterInfo &MRI, const MCRegisterInfo &MRI,
MCContext &Ctx); MCContext &Ctx);
MCAsmBackend *createSparcAsmBackend(const Target &T, const MCRegisterInfo &MRI, MCAsmBackend *createSparcAsmBackend(const Target &T, const MCSubtargetInfo &STI,
const Triple &TT, StringRef CPU, const MCRegisterInfo &MRI,
const MCTargetOptions &Options); const MCTargetOptions &Options);
std::unique_ptr<MCObjectWriter> std::unique_ptr<MCObjectWriter>
createSparcELFObjectWriter(raw_pwrite_stream &OS, bool Is64Bit, createSparcELFObjectWriter(raw_pwrite_stream &OS, bool Is64Bit,

6
lib/Target/SystemZ/MCTargetDesc/SystemZMCAsmBackend.cpp
View File

@ -14,6 +14,7 @@
#include "llvm/MC/MCFixupKindInfo.h" #include "llvm/MC/MCFixupKindInfo.h"
#include "llvm/MC/MCInst.h" #include "llvm/MC/MCInst.h"
#include "llvm/MC/MCObjectWriter.h" #include "llvm/MC/MCObjectWriter.h"
#include "llvm/MC/MCSubtargetInfo.h"
using namespace llvm; using namespace llvm;
@ -122,9 +123,10 @@ bool SystemZMCAsmBackend::writeNopData(uint64_t Count,
} }
MCAsmBackend *llvm::createSystemZMCAsmBackend(const Target &T, MCAsmBackend *llvm::createSystemZMCAsmBackend(const Target &T,
const MCSubtargetInfo &STI,
const MCRegisterInfo &MRI, const MCRegisterInfo &MRI,
const Triple &TT, StringRef CPU,
const MCTargetOptions &Options) { const MCTargetOptions &Options) {
uint8_t OSABI = MCELFObjectTargetWriter::getOSABI(TT.getOS()); uint8_t OSABI =
MCELFObjectTargetWriter::getOSABI(STI.getTargetTriple().getOS());
return new SystemZMCAsmBackend(OSABI); return new SystemZMCAsmBackend(OSABI);
} }

2
lib/Target/SystemZ/MCTargetDesc/SystemZMCTargetDesc.h
View File

@ -89,8 +89,8 @@ MCCodeEmitter *createSystemZMCCodeEmitter(const MCInstrInfo &MCII,
MCContext &Ctx); MCContext &Ctx);
MCAsmBackend *createSystemZMCAsmBackend(const Target &T, MCAsmBackend *createSystemZMCAsmBackend(const Target &T,
const MCSubtargetInfo &STI,
const MCRegisterInfo &MRI, const MCRegisterInfo &MRI,
const Triple &TT, StringRef CPU,
const MCTargetOptions &Options); const MCTargetOptions &Options);
std::unique_ptr<MCObjectWriter> createSystemZObjectWriter(raw_pwrite_stream &OS, std::unique_ptr<MCObjectWriter> createSystemZObjectWriter(raw_pwrite_stream &OS,

11
lib/Target/X86/MCTargetDesc/X86AsmBackend.cpp
View File

@ -843,10 +843,12 @@ public:
} // end anonymous namespace } // end anonymous namespace
MCAsmBackend *llvm::createX86_32AsmBackend(const Target &T, MCAsmBackend *llvm::createX86_32AsmBackend(const Target &T,
const MCSubtargetInfo &STI,
const MCRegisterInfo &MRI, const MCRegisterInfo &MRI,
const Triple &TheTriple,
StringRef CPU,
const MCTargetOptions &Options) { const MCTargetOptions &Options) {
const Triple &TheTriple = STI.getTargetTriple();
StringRef CPU = STI.getCPU();
llvm::errs() << "create x86-32 backend with CPU: " << CPU << "\n";
if (TheTriple.isOSBinFormatMachO()) if (TheTriple.isOSBinFormatMachO())
return new DarwinX86_32AsmBackend(T, MRI, CPU); return new DarwinX86_32AsmBackend(T, MRI, CPU);
@ -862,10 +864,11 @@ MCAsmBackend *llvm::createX86_32AsmBackend(const Target &T,
} }
MCAsmBackend *llvm::createX86_64AsmBackend(const Target &T, MCAsmBackend *llvm::createX86_64AsmBackend(const Target &T,
const MCSubtargetInfo &STI,
const MCRegisterInfo &MRI, const MCRegisterInfo &MRI,
const Triple &TheTriple,
StringRef CPU,
const MCTargetOptions &Options) { const MCTargetOptions &Options) {
const Triple &TheTriple = STI.getTargetTriple();
StringRef CPU = STI.getCPU();
if (TheTriple.isOSBinFormatMachO()) { if (TheTriple.isOSBinFormatMachO()) {
MachO::CPUSubTypeX86 CS = MachO::CPUSubTypeX86 CS =
StringSwitch<MachO::CPUSubTypeX86>(TheTriple.getArchName()) StringSwitch<MachO::CPUSubTypeX86>(TheTriple.getArchName())

10
lib/Target/X86/MCTargetDesc/X86MCTargetDesc.h
View File

@ -70,11 +70,13 @@ MCCodeEmitter *createX86MCCodeEmitter(const MCInstrInfo &MCII,
const MCRegisterInfo &MRI, const MCRegisterInfo &MRI,
MCContext &Ctx); MCContext &Ctx);
MCAsmBackend *createX86_32AsmBackend(const Target &T, const MCRegisterInfo &MRI, MCAsmBackend *createX86_32AsmBackend(const Target &T,
const Triple &TT, StringRef CPU, const MCSubtargetInfo &STI,
const MCRegisterInfo &MRI,
const MCTargetOptions &Options); const MCTargetOptions &Options);
MCAsmBackend *createX86_64AsmBackend(const Target &T, const MCRegisterInfo &MRI, MCAsmBackend *createX86_64AsmBackend(const Target &T,
const Triple &TT, StringRef CPU, const MCSubtargetInfo &STI,
const MCRegisterInfo &MRI,
const MCTargetOptions &Options); const MCTargetOptions &Options);
/// Implements X86-only directives for assembly emission. /// Implements X86-only directives for assembly emission.

10
tools/dsymutil/DwarfLinker.cpp
View File

@ -672,8 +672,12 @@ bool DwarfStreamer::init(Triple TheTriple) {
MC.reset(new MCContext(MAI.get(), MRI.get(), MOFI.get())); MC.reset(new MCContext(MAI.get(), MRI.get(), MOFI.get()));
MOFI->InitMCObjectFileInfo(TheTriple, /*PIC*/ false, *MC); MOFI->InitMCObjectFileInfo(TheTriple, /*PIC*/ false, *MC);
MSTI.reset(TheTarget->createMCSubtargetInfo(TripleName, "", ""));
if (!MSTI)
return error("no subtarget info for target " + TripleName, Context);
MCTargetOptions Options; MCTargetOptions Options;
MAB = TheTarget->createMCAsmBackend(*MRI, TripleName, "", Options); MAB = TheTarget->createMCAsmBackend(*MSTI, *MRI, Options);
if (!MAB) if (!MAB)
return error("no asm backend for target " + TripleName, Context); return error("no asm backend for target " + TripleName, Context);
@ -681,10 +685,6 @@ bool DwarfStreamer::init(Triple TheTriple) {
if (!MII) if (!MII)
return error("no instr info info for target " + TripleName, Context); return error("no instr info info for target " + TripleName, Context);
MSTI.reset(TheTarget->createMCSubtargetInfo(TripleName, "", ""));
if (!MSTI)
return error("no subtarget info for target " + TripleName, Context);
MCE = TheTarget->createMCCodeEmitter(*MII, *MRI, *MC); MCE = TheTarget->createMCCodeEmitter(*MII, *MRI, *MC);
if (!MCE) if (!MCE)
return error("no code emitter for target " + TripleName, Context); return error("no code emitter for target " + TripleName, Context);

12
tools/llvm-dwp/llvm-dwp.cpp
View File

@ -673,8 +673,13 @@ int main(int argc, char **argv) {
MCContext MC(MAI.get(), MRI.get(), &MOFI); MCContext MC(MAI.get(), MRI.get(), &MOFI);
MOFI.InitMCObjectFileInfo(TheTriple, /*PIC*/ false, MC); MOFI.InitMCObjectFileInfo(TheTriple, /*PIC*/ false, MC);
std::unique_ptr<MCSubtargetInfo> MSTI(
TheTarget->createMCSubtargetInfo(TripleName, "", ""));
if (!MSTI)
return error("no subtarget info for target " + TripleName, Context);
MCTargetOptions Options; MCTargetOptions Options;
auto MAB = TheTarget->createMCAsmBackend(*MRI, TripleName, "", Options); auto MAB = TheTarget->createMCAsmBackend(*MSTI, *MRI, Options);
if (!MAB) if (!MAB)
return error("no asm backend for target " + TripleName, Context); return error("no asm backend for target " + TripleName, Context);
@ -682,11 +687,6 @@ int main(int argc, char **argv) {
if (!MII) if (!MII)
return error("no instr info info for target " + TripleName, Context); return error("no instr info info for target " + TripleName, Context);
std::unique_ptr<MCSubtargetInfo> MSTI(
TheTarget->createMCSubtargetInfo(TripleName, "", ""));
if (!MSTI)
return error("no subtarget info for target " + TripleName, Context);
MCCodeEmitter *MCE = TheTarget->createMCCodeEmitter(*MII, *MRI, MC); MCCodeEmitter *MCE = TheTarget->createMCCodeEmitter(*MII, *MRI, MC);
if (!MCE) if (!MCE)
return error("no code emitter for target " + TripleName, Context); return error("no code emitter for target " + TripleName, Context);

5
tools/llvm-mc/llvm-mc.cpp
View File

@ -567,7 +567,7 @@ int main(int argc, char **argv) {
MCAsmBackend *MAB = nullptr; MCAsmBackend *MAB = nullptr;
if (ShowEncoding) { if (ShowEncoding) {
CE = TheTarget->createMCCodeEmitter(*MCII, *MRI, Ctx); CE = TheTarget->createMCCodeEmitter(*MCII, *MRI, Ctx);
MAB = TheTarget->createMCAsmBackend(*MRI, TripleName, MCPU, MCOptions); MAB = TheTarget->createMCAsmBackend(*STI, *MRI, MCOptions);
} }
auto FOut = llvm::make_unique<formatted_raw_ostream>(*OS); auto FOut = llvm::make_unique<formatted_raw_ostream>(*OS);
Str.reset(TheTarget->createAsmStreamer( Str.reset(TheTarget->createAsmStreamer(
@ -588,8 +588,7 @@ int main(int argc, char **argv) {
} }
MCCodeEmitter *CE = TheTarget->createMCCodeEmitter(*MCII, *MRI, Ctx); MCCodeEmitter *CE = TheTarget->createMCCodeEmitter(*MCII, *MRI, Ctx);
MCAsmBackend *MAB = TheTarget->createMCAsmBackend(*MRI, TripleName, MCPU, MCAsmBackend *MAB = TheTarget->createMCAsmBackend(*STI, *MRI, MCOptions);
MCOptions);
Str.reset(TheTarget->createMCObjectStreamer( Str.reset(TheTarget->createMCObjectStreamer(
TheTriple, Ctx, std::unique_ptr<MCAsmBackend>(MAB), *OS, TheTriple, Ctx, std::unique_ptr<MCAsmBackend>(MAB), *OS,
std::unique_ptr<MCCodeEmitter>(CE), *STI, MCOptions.MCRelaxAll, std::unique_ptr<MCCodeEmitter>(CE), *STI, MCOptions.MCRelaxAll,

12
unittests/DebugInfo/DWARF/DwarfGenerator.cpp
View File

@ -152,8 +152,13 @@ llvm::Error dwarfgen::Generator::init(Triple TheTriple, uint16_t V) {
MC.reset(new MCContext(MAI.get(), MRI.get(), MOFI.get())); MC.reset(new MCContext(MAI.get(), MRI.get(), MOFI.get()));
MOFI->InitMCObjectFileInfo(TheTriple, /*PIC*/ false, *MC); MOFI->InitMCObjectFileInfo(TheTriple, /*PIC*/ false, *MC);
MSTI.reset(TheTarget->createMCSubtargetInfo(TripleName, "", ""));
if (!MSTI)
return make_error<StringError>("no subtarget info for target " + TripleName,
inconvertibleErrorCode());
MCTargetOptions MCOptions = InitMCTargetOptionsFromFlags(); MCTargetOptions MCOptions = InitMCTargetOptionsFromFlags();
MAB = TheTarget->createMCAsmBackend(*MRI, TripleName, "", MCOptions); MAB = TheTarget->createMCAsmBackend(*MSTI, *MRI, MCOptions);
if (!MAB) if (!MAB)
return make_error<StringError>("no asm backend for target " + TripleName, return make_error<StringError>("no asm backend for target " + TripleName,
inconvertibleErrorCode()); inconvertibleErrorCode());
@ -164,11 +169,6 @@ llvm::Error dwarfgen::Generator::init(Triple TheTriple, uint16_t V) {
TripleName, TripleName,
inconvertibleErrorCode()); inconvertibleErrorCode());
MSTI.reset(TheTarget->createMCSubtargetInfo(TripleName, "", ""));
if (!MSTI)
return make_error<StringError>("no subtarget info for target " + TripleName,
inconvertibleErrorCode());
MCE = TheTarget->createMCCodeEmitter(*MII, *MRI, *MC); MCE = TheTarget->createMCCodeEmitter(*MII, *MRI, *MC);
if (!MCE) if (!MCE)
return make_error<StringError>("no code emitter for target " + TripleName, return make_error<StringError>("no code emitter for target " + TripleName,