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[X86][RDRAND] Split off i64 intrinsic tests and test i16/i32 on 32-bit target as well.

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llvm-svn: 306960
This commit is contained in:
Simon Pilgrim 2017-07-01 16:41:12 +00:00
parent ad8696a5ed
commit 0808fb63d2
2 changed files with 102 additions and 36 deletions
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19
test/CodeGen/X86/rdrand-x86_64.ll Normal file
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@ -0,0 +1,19 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mcpu=core-avx-i -mattr=+rdrnd | FileCheck %s
declare {i64, i32} @llvm.x86.rdrand.64()
define i32 @_rdrand64_step(i64* %random_val) {
; CHECK-LABEL: _rdrand64_step:
; CHECK: # BB#0:
; CHECK-NEXT: rdrandq %rcx
; CHECK-NEXT: movl $1, %eax
; CHECK-NEXT: cmovael %ecx, %eax
; CHECK-NEXT: movq %rcx, (%rdi)
; CHECK-NEXT: retq
%call = call {i64, i32} @llvm.x86.rdrand.64()
%randval = extractvalue {i64, i32} %call, 0
store i64 %randval, i64* %random_val
%isvalid = extractvalue {i64, i32} %call, 1
ret i32 %isvalid
}

119
test/CodeGen/X86/rdrand.ll
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@ -1,66 +1,117 @@
; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mcpu=core-avx-i -mattr=+rdrnd | FileCheck %s
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc < %s -mtriple=i686-unknown-unknown -mcpu=core-avx-i -mattr=+rdrnd | FileCheck %s --check-prefix=X86
; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mcpu=core-avx-i -mattr=+rdrnd | FileCheck %s --check-prefix=X64
declare {i16, i32} @llvm.x86.rdrand.16()
declare {i32, i32} @llvm.x86.rdrand.32()
declare {i64, i32} @llvm.x86.rdrand.64()
define i32 @_rdrand16_step(i16* %random_val) {
; X86-LABEL: _rdrand16_step:
; X86: # BB#0:
; X86-NEXT: movl {{[0-9]+}}(%esp), %ecx
; X86-NEXT: rdrandw %ax
; X86-NEXT: movzwl %ax, %edx
; X86-NEXT: movl $1, %eax
; X86-NEXT: cmovael %edx, %eax
; X86-NEXT: movw %dx, (%ecx)
; X86-NEXT: retl
;
; X64-LABEL: _rdrand16_step:
; X64: # BB#0:
; X64-NEXT: rdrandw %ax
; X64-NEXT: movzwl %ax, %ecx
; X64-NEXT: movl $1, %eax
; X64-NEXT: cmovael %ecx, %eax
; X64-NEXT: movw %cx, (%rdi)
; X64-NEXT: retq
%call = call {i16, i32} @llvm.x86.rdrand.16()
%randval = extractvalue {i16, i32} %call, 0
store i16 %randval, i16* %random_val
%isvalid = extractvalue {i16, i32} %call, 1
ret i32 %isvalid
; CHECK-LABEL: _rdrand16_step:
; CHECK: rdrandw %ax
; CHECK: movzwl %ax, %ecx
; CHECK: movl $1, %eax
; CHECK: cmovael %ecx, %eax
; CHECK: movw %cx, (%r[[A0:di|cx]])
; CHECK: ret
}
define i32 @_rdrand32_step(i32* %random_val) {
; X86-LABEL: _rdrand32_step:
; X86: # BB#0:
; X86-NEXT: movl {{[0-9]+}}(%esp), %ecx
; X86-NEXT: rdrandl %edx
; X86-NEXT: movl $1, %eax
; X86-NEXT: cmovael %edx, %eax
; X86-NEXT: movl %edx, (%ecx)
; X86-NEXT: retl
;
; X64-LABEL: _rdrand32_step:
; X64: # BB#0:
; X64-NEXT: rdrandl %ecx
; X64-NEXT: movl $1, %eax
; X64-NEXT: cmovael %ecx, %eax
; X64-NEXT: movl %ecx, (%rdi)
; X64-NEXT: retq
%call = call {i32, i32} @llvm.x86.rdrand.32()
%randval = extractvalue {i32, i32} %call, 0
store i32 %randval, i32* %random_val
%isvalid = extractvalue {i32, i32} %call, 1
ret i32 %isvalid
; CHECK-LABEL: _rdrand32_step:
; CHECK: rdrandl %e[[T0:[a-z]+]]
; CHECK: movl $1, %eax
; CHECK: cmovael %e[[T0]], %eax
; CHECK: movl %e[[T0]], (%r[[A0]])
; CHECK: ret
}
define i32 @_rdrand64_step(i64* %random_val) {
%call = call {i64, i32} @llvm.x86.rdrand.64()
%randval = extractvalue {i64, i32} %call, 0
store i64 %randval, i64* %random_val
%isvalid = extractvalue {i64, i32} %call, 1
ret i32 %isvalid
; CHECK-LABEL: _rdrand64_step:
; CHECK: rdrandq %r[[T1:[a-z]+]]
; CHECK: movl $1, %eax
; CHECK: cmovael %e[[T1]], %eax
; CHECK: movq %r[[T1]], (%r[[A0]])
; CHECK: ret
}
; Check that MachineCSE doesn't eliminate duplicate rdrand instructions.
define i32 @CSE() nounwind {
; X86-LABEL: CSE:
; X86: # BB#0:
; X86-NEXT: rdrandl %ecx
; X86-NEXT: rdrandl %eax
; X86-NEXT: addl %ecx, %eax
; X86-NEXT: retl
;
; X64-LABEL: CSE:
; X64: # BB#0:
; X64-NEXT: rdrandl %ecx
; X64-NEXT: rdrandl %eax
; X64-NEXT: addl %ecx, %eax
; X64-NEXT: retq
%rand1 = tail call { i32, i32 } @llvm.x86.rdrand.32() nounwind
%v1 = extractvalue { i32, i32 } %rand1, 0
%rand2 = tail call { i32, i32 } @llvm.x86.rdrand.32() nounwind
%v2 = extractvalue { i32, i32 } %rand2, 0
%add = add i32 %v2, %v1
ret i32 %add
; CHECK-LABEL: CSE:
; CHECK: rdrandl
; CHECK: rdrandl
}
; Check that MachineLICM doesn't hoist rdrand instructions.
define void @loop(i32* %p, i32 %n) nounwind {
; X86-LABEL: loop:
; X86: # BB#0: # %entry
; X86-NEXT: movl {{[0-9]+}}(%esp), %eax
; X86-NEXT: testl %eax, %eax
; X86-NEXT: je .LBB3_3
; X86-NEXT: # BB#1: # %while.body.preheader
; X86-NEXT: movl {{[0-9]+}}(%esp), %ecx
; X86-NEXT: .p2align 4, 0x90
; X86-NEXT: .LBB3_2: # %while.body
; X86-NEXT: # =>This Inner Loop Header: Depth=1
; X86-NEXT: rdrandl %edx
; X86-NEXT: movl %edx, (%ecx)
; X86-NEXT: leal 4(%ecx), %ecx
; X86-NEXT: decl %eax
; X86-NEXT: jne .LBB3_2
; X86-NEXT: .LBB3_3: # %while.end
; X86-NEXT: retl
;
; X64-LABEL: loop:
; X64: # BB#0: # %entry
; X64-NEXT: testl %esi, %esi
; X64-NEXT: je .LBB3_2
; X64-NEXT: .p2align 4, 0x90
; X64-NEXT: .LBB3_1: # %while.body
; X64-NEXT: # =>This Inner Loop Header: Depth=1
; X64-NEXT: rdrandl %eax
; X64-NEXT: movl %eax, (%rdi)
; X64-NEXT: leaq 4(%rdi), %rdi
; X64-NEXT: decl %esi
; X64-NEXT: jne .LBB3_1
; X64-NEXT: .LBB3_2: # %while.end
; X64-NEXT: retq
entry:
%tobool1 = icmp eq i32 %n, 0
br i1 %tobool1, label %while.end, label %while.body
@ -78,8 +129,4 @@ while.body: ; preds = %entry, %while.body
while.end: ; preds = %while.body, %entry
ret void
; CHECK-LABEL: loop:
; CHECK-NOT: rdrandl
; CHECK: This Inner Loop Header: Depth=1
; CHECK: rdrandl
}