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[AArch64] IDSAR6 register assembler support

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The IDSAR6 system register has been introduced to identify the
v8.3-a Javascript data type conversion and v8.2-a dot product
support.

Differential Revision: https://reviews.llvm.org/D37068

llvm-svn: 312225
This commit is contained in:
Sam Parker 2017-08-31 08:36:45 +00:00
parent e2e0dd8cae
commit 081272a7e2
3 changed files with 16 additions and 0 deletions
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3
lib/Target/AArch64/AArch64SystemOperands.td
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@ -342,6 +342,9 @@ def : ROSysReg<"ID_ISAR2_EL1", 0b11, 0b000, 0b0000, 0b0010, 0b010>;
def : ROSysReg<"ID_ISAR3_EL1", 0b11, 0b000, 0b0000, 0b0010, 0b011>;
def : ROSysReg<"ID_ISAR4_EL1", 0b11, 0b000, 0b0000, 0b0010, 0b100>;
def : ROSysReg<"ID_ISAR5_EL1", 0b11, 0b000, 0b0000, 0b0010, 0b101>;
def : ROSysReg<"ID_ISAR6_EL1", 0b11, 0b000, 0b0000, 0b0010, 0b111> {
let Requires = [{ {AArch64::HasV8_2aOps} }];
}
def : ROSysReg<"ID_AA64PFR0_EL1", 0b11, 0b000, 0b0000, 0b0100, 0b000>;
def : ROSysReg<"ID_AA64PFR1_EL1", 0b11, 0b000, 0b0000, 0b0100, 0b001>;
def : ROSysReg<"ID_AA64DFR0_EL1", 0b11, 0b000, 0b0000, 0b0101, 0b000>;

9
test/MC/AArch64/armv8.3a-ID_ISAR6_EL1.s Normal file
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@ -0,0 +1,9 @@
// RUN: llvm-mc -triple aarch64-none-linux-gnu -show-encoding -mattr=+v8.3a < %s 2>&1 | FileCheck %s
// RUN: not llvm-mc -triple aarch64-none-linux-gnu < %s 2> %t
// RUN: FileCheck --check-prefix=CHECK-REQ %s < %t
mrs x0, ID_ISAR6_EL1
// CHECK: mrs x0, ID_ISAR6_EL1 // encoding: [0xe0,0x02,0x38,0xd5]
// CHECK-REQ: error: expected readable system register
// CHECK-REQ-NEXT: mrs x0, ID_ISAR6_EL1
// CHECK-REQ-NEXT: ^

4
test/MC/Disassembler/AArch64/armv8.3a-ID_ISAR6_EL1.txt Normal file
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@ -0,0 +1,4 @@
# RUN: llvm-mc -triple aarch64-none-linux-gnu -mattr=+v8.3a --disassemble < %s | FileCheck %s
# CHECK: mrs x0, ID_ISAR6_EL1
0xe0,0x02,0x38,0xd5