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https://github.com/RPCS3/llvm-mirror.git
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switch to the new live in thing
llvm-svn: 22185
This commit is contained in:
Andrew Lenharth
parent
cccc417f16
commit
083ba1ead1
@ -140,6 +140,17 @@ namespace {
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};
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}
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/// AddLiveIn - This helper function adds the specified physical register to the
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/// MachineFunction as a live in value. It also creates a corresponding virtual
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/// register for it.
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static unsigned AddLiveIn(MachineFunction &MF, unsigned PReg,
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TargetRegisterClass *RC) {
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assert(RC->contains(PReg) && "Not the correct regclass!");
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unsigned VReg = MF.getSSARegMap()->createVirtualRegister(RC);
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MF.addLiveIn(PReg, VReg);
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return VReg;
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}
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//http://www.cs.arizona.edu/computer.help/policy/DIGITAL_unix/AA-PY8AC-TET1_html/callCH3.html#BLOCK21
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//For now, just use variable size stack frame format
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@ -162,14 +173,10 @@ std::vector<SDOperand>
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AlphaTargetLowering::LowerArguments(Function &F, SelectionDAG &DAG)
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{
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std::vector<SDOperand> ArgValues;
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std::vector<SDOperand> LS;
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SDOperand Chain = DAG.getRoot();
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// assert(0 && "TODO");
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MachineFunction &MF = DAG.getMachineFunction();
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MachineFrameInfo*MFI = MF.getFrameInfo();
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GP = MF.getSSARegMap()->createVirtualRegister(getRegClassFor(MVT::i64));
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MachineBasicBlock& BB = MF.front();
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//Handle the return address
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@ -181,64 +188,35 @@ AlphaTargetLowering::LowerArguments(Function &F, SelectionDAG &DAG)
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Alpha::F19, Alpha::F20, Alpha::F21};
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int count = 0;
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//Def incoming registers
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{
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Function::arg_iterator I = F.arg_begin();
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Function::arg_iterator E = F.arg_end();
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for (int i = 0; i < 6; ++i)
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{
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if (F.isVarArg()) {
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MF.addLiveIn(args_int[i]);
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MF.addLiveIn(args_float[i]);
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// BuildMI(&BB, Alpha::IDEF, 0, args_int[i]);
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// BuildMI(&BB, Alpha::IDEF, 0, args_float[i]);
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} else if (I != E)
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{
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if(MVT::isInteger(getValueType(I->getType())))
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MF.addLiveIn(args_int[i]);
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// BuildMI(&BB, Alpha::IDEF, 0, args_int[i]);
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else
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MF.addLiveIn(args_float[i]);
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// BuildMI(&BB, Alpha::IDEF, 0, args_float[i]);
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++I;
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}
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}
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}
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MF.addLiveIn(Alpha::R29);
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// BuildMI(&BB, Alpha::IDEF, 0, Alpha::R29);
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BuildMI(&BB, Alpha::BIS, 2, GP).addReg(Alpha::R29).addReg(Alpha::R29);
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GP = AddLiveIn(MF, Alpha::R29, getRegClassFor(MVT::i64));
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for (Function::arg_iterator I = F.arg_begin(), E = F.arg_end(); I != E; ++I)
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{
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SDOperand newroot, argt;
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SDOperand argt;
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if (count < 6) {
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unsigned Vreg;
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MVT::ValueType VT = getValueType(I->getType());
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switch (getValueType(I->getType())) {
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switch (VT) {
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default:
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std::cerr << "Unknown Type " << VT << "\n";
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abort();
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case MVT::f64:
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case MVT::f32:
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Vreg = MF.getSSARegMap()->createVirtualRegister(getRegClassFor(VT));
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BuildMI(&BB, Alpha::CPYS, 2, Vreg).addReg(args_float[count]).addReg(args_float[count]);
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argt = newroot = DAG.getCopyFromReg(Vreg,
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getValueType(I->getType()),
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Chain);
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args_float[count] = AddLiveIn(MF,args_float[count], getRegClassFor(VT));
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argt = DAG.getCopyFromReg(args_float[count], VT, DAG.getRoot());
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break;
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case MVT::i1:
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case MVT::i8:
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case MVT::i16:
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case MVT::i32:
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case MVT::i64:
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Vreg = MF.getSSARegMap()->createVirtualRegister(getRegClassFor(MVT::i64));
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BuildMI(&BB, Alpha::BIS, 2, Vreg).addReg(args_int[count]).addReg(args_int[count]);
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argt = newroot = DAG.getCopyFromReg(Vreg, MVT::i64, Chain);
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if (getValueType(I->getType()) != MVT::i64)
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argt = DAG.getNode(ISD::TRUNCATE, getValueType(I->getType()), newroot);
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args_int[count] = AddLiveIn(MF, args_int[count], getRegClassFor(VT));
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argt = DAG.getCopyFromReg(args_int[count], VT, DAG.getRoot());
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// if (VT != MVT::i64)
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// argt = DAG.getNode(ISD::TRUNCATE, VT, argt);
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break;
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}
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DAG.setRoot(argt.getValue(1));
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} else { //more args
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// Create the frame index object for this incoming parameter...
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int FI = MFI->CreateFixedObject(8, 8 * (count - 6));
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@ -246,40 +224,35 @@ AlphaTargetLowering::LowerArguments(Function &F, SelectionDAG &DAG)
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// Create the SelectionDAG nodes corresponding to a load
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//from this parameter
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SDOperand FIN = DAG.getFrameIndex(FI, MVT::i64);
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argt = newroot = DAG.getLoad(getValueType(I->getType()),
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DAG.getEntryNode(), FIN, DAG.getSrcValue(NULL));
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argt = DAG.getLoad(getValueType(I->getType()),
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DAG.getEntryNode(), FIN, DAG.getSrcValue(NULL));
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}
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++count;
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LS.push_back(newroot.getValue(1));
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ArgValues.push_back(argt);
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}
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// If the functions takes variable number of arguments, copy all regs to stack
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if (F.isVarArg())
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for (int i = 0; i < 6; ++i)
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{
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unsigned Vreg = MF.getSSARegMap()->createVirtualRegister(getRegClassFor(MVT::i64));
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BuildMI(&BB, Alpha::BIS, 2, Vreg).addReg(args_int[i]).addReg(args_int[i]);
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SDOperand argt = DAG.getCopyFromReg(Vreg, MVT::i64, Chain);
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if (F.isVarArg()) {
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std::vector<SDOperand> LS;
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for (int i = 0; i < 6; ++i) {
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if (args_int[i] < 1024)
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args_int[i] = AddLiveIn(MF,args_int[i], getRegClassFor(MVT::i64));
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SDOperand argt = DAG.getCopyFromReg(args_int[i], MVT::i64, DAG.getRoot());
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int FI = MFI->CreateFixedObject(8, -8 * (6 - i));
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SDOperand SDFI = DAG.getFrameIndex(FI, MVT::i64);
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LS.push_back(DAG.getNode(ISD::STORE, MVT::Other, Chain, argt, SDFI, DAG.getSrcValue(NULL)));
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Vreg = MF.getSSARegMap()->createVirtualRegister(getRegClassFor(MVT::f64));
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BuildMI(&BB, Alpha::CPYS, 2, Vreg).addReg(args_float[i]).addReg(args_float[i]);
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argt = DAG.getCopyFromReg(Vreg, MVT::f64, Chain);
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LS.push_back(DAG.getNode(ISD::STORE, MVT::Other, DAG.getRoot(), argt, SDFI, DAG.getSrcValue(NULL)));
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if (args_float[i] < 1024)
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args_float[i] = AddLiveIn(MF,args_float[i], getRegClassFor(MVT::f64));
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argt = DAG.getCopyFromReg(args_float[i], MVT::f64, DAG.getRoot());
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FI = MFI->CreateFixedObject(8, - 8 * (12 - i));
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SDFI = DAG.getFrameIndex(FI, MVT::i64);
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LS.push_back(DAG.getNode(ISD::STORE, MVT::Other, Chain, argt, SDFI, DAG.getSrcValue(NULL)));
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LS.push_back(DAG.getNode(ISD::STORE, MVT::Other, DAG.getRoot(), argt, SDFI, DAG.getSrcValue(NULL)));
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}
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// If the function takes variable number of arguments, make a frame index for
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// the start of the first arg value... for expansion of llvm.va_start.
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// if (F.isVarArg())
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// VarArgsFrameIndex = MFI->CreateFixedObject(4, ArgOffset);
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//Set up a token factor with all the stack traffic
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DAG.setRoot(DAG.getNode(ISD::TokenFactor, MVT::Other, LS));
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//Set up a token factor with all the stack traffic
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DAG.setRoot(DAG.getNode(ISD::TokenFactor, MVT::Other, LS));
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}
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// Finally, inform the code generator which regs we return values in.
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switch (getValueType(F.getReturnType())) {
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@ -436,6 +409,8 @@ public:
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ExprMap.clear();
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CCInvMap.clear();
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}
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virtual void EmitFunctionEntryCode(Function &Fn, MachineFunction &MF);
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unsigned SelectExpr(SDOperand N);
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unsigned SelectExprFP(SDOperand N, unsigned Result);
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@ -455,6 +430,26 @@ public:
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};
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}
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void ISel::EmitFunctionEntryCode(Function &Fn, MachineFunction &MF) {
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// If this function has live-in values, emit the copies from pregs to vregs at
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// the top of the function, before anything else.
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MachineBasicBlock *BB = MF.begin();
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if (MF.livein_begin() != MF.livein_end()) {
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SSARegMap *RegMap = MF.getSSARegMap();
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for (MachineFunction::livein_iterator LI = MF.livein_begin(),
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E = MF.livein_end(); LI != E; ++LI) {
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const TargetRegisterClass *RC = RegMap->getRegClass(LI->second);
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if (RC == Alpha::GPRCRegisterClass) {
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BuildMI(BB, Alpha::BIS, 2, LI->second).addReg(LI->first).addReg(LI->first);
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} else if (RC == Alpha::FPRCRegisterClass) {
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BuildMI(BB, Alpha::CPYS, 2, LI->second).addReg(LI->first).addReg(LI->first);
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} else {
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assert(0 && "Unknown regclass!");
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}
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}
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}
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}
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//Factorize a number using the list of constants
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static bool factorize(int v[], int res[], int size, uint64_t c)
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{
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