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[Hexagon] Disassembling, printing, and emitting instructions a whole-bundle at a time which is the semantic unit for Hexagon. Fixing tests to use the new format. Disabling tests in the direct object emission path for a followup patch.
llvm-svn: 238556
This commit is contained in:
Colin LeMahieu
parent
2ea0919069
commit
084c4d499d
@ -7,9 +7,11 @@
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//
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//===----------------------------------------------------------------------===//
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#include "Hexagon.h"
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#include "MCTargetDesc/HexagonBaseInfo.h"
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#include "MCTargetDesc/HexagonMCInstrInfo.h"
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#include "MCTargetDesc/HexagonMCTargetDesc.h"
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#include "llvm/MC/MCContext.h"
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#include "llvm/MC/MCDisassembler.h"
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#include "llvm/MC/MCExpr.h"
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@ -27,6 +29,7 @@
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#include <vector>
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using namespace llvm;
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using namespace Hexagon;
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#define DEBUG_TYPE "hexagon-disassembler"
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@ -37,9 +40,14 @@ namespace {
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/// \brief Hexagon disassembler for all Hexagon platforms.
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class HexagonDisassembler : public MCDisassembler {
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public:
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std::unique_ptr<MCInst *> CurrentBundle;
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HexagonDisassembler(MCSubtargetInfo const &STI, MCContext &Ctx)
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: MCDisassembler(STI, Ctx) {}
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: MCDisassembler(STI, Ctx), CurrentBundle(new MCInst *) {}
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DecodeStatus getSingleInstruction(MCInst &Instr, MCInst &MCB,
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ArrayRef<uint8_t> Bytes, uint64_t Address,
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raw_ostream &VStream, raw_ostream &CStream,
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bool &Complete) const;
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DecodeStatus getInstruction(MCInst &Instr, uint64_t &Size,
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ArrayRef<uint8_t> Bytes, uint64_t Address,
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raw_ostream &VStream,
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@ -191,17 +199,53 @@ DecodeStatus HexagonDisassembler::getInstruction(MCInst &MI, uint64_t &Size,
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uint64_t Address,
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raw_ostream &os,
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raw_ostream &cs) const {
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Size = 4;
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if (Bytes.size() < 4)
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return MCDisassembler::Fail;
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DecodeStatus Result = DecodeStatus::Success;
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bool Complete = false;
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Size = 0;
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uint32_t insn =
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*CurrentBundle = &MI;
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MI.setOpcode(Hexagon::BUNDLE);
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MI.addOperand(MCOperand::createImm(0));
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while (Result == Success && Complete == false)
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{
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if (Bytes.size() < HEXAGON_INSTR_SIZE)
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return MCDisassembler::Fail;
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MCInst * Inst = new (getContext()) MCInst;
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Result = getSingleInstruction(*Inst, MI, Bytes, Address, os, cs, Complete);
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MI.addOperand(MCOperand::createInst(Inst));
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Size += HEXAGON_INSTR_SIZE;
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Bytes = Bytes.slice(HEXAGON_INSTR_SIZE);
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}
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return Result;
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}
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DecodeStatus HexagonDisassembler::getSingleInstruction(
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MCInst &MI, MCInst &MCB, ArrayRef<uint8_t> Bytes, uint64_t Address,
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raw_ostream &os, raw_ostream &cs, bool &Complete) const {
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assert(Bytes.size() >= HEXAGON_INSTR_SIZE);
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uint32_t Instruction =
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llvm::support::endian::read<uint32_t, llvm::support::little,
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llvm::support::unaligned>(Bytes.data());
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// Remove parse bits.
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insn &= ~static_cast<uint32_t>(HexagonII::InstParseBits::INST_PARSE_MASK);
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DecodeStatus Result = decodeInstruction(DecoderTable32, MI, insn, Address, this, STI);
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HexagonMCInstrInfo::AppendImplicitOperands(MI);
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auto BundleSize = HexagonMCInstrInfo::bundleSize(MCB);
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if ((Instruction & HexagonII::INST_PARSE_MASK) ==
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HexagonII::INST_PARSE_LOOP_END) {
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if (BundleSize == 0)
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HexagonMCInstrInfo::setInnerLoop(MCB);
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else if (BundleSize == 1)
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HexagonMCInstrInfo::setOuterLoop(MCB);
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else
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return DecodeStatus::Fail;
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}
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DecodeStatus Result = DecodeStatus::Success;
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if ((Instruction & HexagonII::INST_PARSE_MASK) ==
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HexagonII::INST_PARSE_PACKET_END)
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Complete = true;
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// Calling the auto-generated decoder function.
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Result =
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decodeInstruction(DecoderTable32, MI, Instruction, Address, this, STI);
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return Result;
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}
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@ -76,4 +76,8 @@ namespace llvm {
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// Maximum number of words and instructions in a packet.
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#define HEXAGON_PACKET_SIZE 4
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// Minimum number of instructions in an end-loop packet.
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#define HEXAGON_PACKET_INNER_SIZE 2
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#define HEXAGON_PACKET_OUTER_SIZE 3
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#endif
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@ -177,47 +177,29 @@ bool HexagonAsmPrinter::PrintAsmMemoryOperand(const MachineInstr *MI,
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/// the current output stream.
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///
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void HexagonAsmPrinter::EmitInstruction(const MachineInstr *MI) {
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MCInst MCB;
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MCB.setOpcode(Hexagon::BUNDLE);
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MCB.addOperand(MCOperand::createImm(0));
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if (MI->isBundle()) {
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std::vector<MachineInstr const *> BundleMIs;
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const MachineBasicBlock *MBB = MI->getParent();
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const MachineBasicBlock* MBB = MI->getParent();
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MachineBasicBlock::const_instr_iterator MII = MI;
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++MII;
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unsigned int IgnoreCount = 0;
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while (MII != MBB->end() && MII->isInsideBundle()) {
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const MachineInstr *MInst = MII;
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if (MInst->getOpcode() == TargetOpcode::DBG_VALUE ||
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MInst->getOpcode() == TargetOpcode::IMPLICIT_DEF) {
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IgnoreCount++;
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++MII;
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continue;
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}
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// BundleMIs.push_back(&*MII);
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BundleMIs.push_back(MInst);
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++MII;
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}
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unsigned Size = BundleMIs.size();
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assert((Size + IgnoreCount) == MI->getBundleSize() && "Corrupt Bundle!");
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for (unsigned Index = 0; Index < Size; Index++) {
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MCInst MCI;
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unsigned IgnoreCount = 0;
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HexagonLowerToMC(BundleMIs[Index], MCI, *this);
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HexagonMCInstrInfo::AppendImplicitOperands(MCI);
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HexagonMCInstrInfo::setPacketBegin(MCI, Index == 0);
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HexagonMCInstrInfo::setPacketEnd(MCI, Index == (Size - 1));
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EmitToStreamer(*OutStreamer, MCI);
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for (++MII; MII != MBB->end() && MII->isInsideBundle(); ++MII) {
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if (MII->getOpcode() == TargetOpcode::DBG_VALUE ||
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MII->getOpcode() == TargetOpcode::IMPLICIT_DEF)
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++IgnoreCount;
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else {
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HexagonLowerToMC(MII, MCB, *this);
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}
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}
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}
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else {
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MCInst MCI;
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HexagonLowerToMC(MI, MCI, *this);
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HexagonMCInstrInfo::AppendImplicitOperands(MCI);
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if (MI->getOpcode() == Hexagon::ENDLOOP0) {
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HexagonMCInstrInfo::setPacketBegin(MCI, true);
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HexagonMCInstrInfo::setPacketEnd(MCI, true);
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}
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EmitToStreamer(*OutStreamer, MCI);
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HexagonLowerToMC(MI, MCB, *this);
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HexagonMCInstrInfo::padEndloop(MCB);
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}
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EmitToStreamer(*OutStreamer, MCB);
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return;
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}
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@ -66,10 +66,8 @@ def DoubleWordAccess : MemAccessSize<4>;// Double word access instruction (memd)
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class OpcodeHexagon {
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field bits<32> Inst = ?; // Default to an invalid insn.
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bits<4> IClass = 0; // ICLASS
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bits<2> IParse = 0; // Parse bits.
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let Inst{31-28} = IClass;
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let Inst{15-14} = IParse;
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bits<1> zero = 0;
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}
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@ -15,9 +15,12 @@
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#include "Hexagon.h"
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#include "HexagonAsmPrinter.h"
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#include "HexagonMachineFunctionInfo.h"
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#include "MCTargetDesc/HexagonMCInstrInfo.h"
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#include "llvm/CodeGen/MachineBasicBlock.h"
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#include "llvm/IR/Constants.h"
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#include "llvm/IR/Mangler.h"
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#include "llvm/MC/MCContext.h"
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#include "llvm/MC/MCExpr.h"
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#include "llvm/MC/MCInst.h"
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@ -38,9 +41,20 @@ static MCOperand GetSymbolRef(const MachineOperand& MO, const MCSymbol* Symbol,
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}
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// Create an MCInst from a MachineInstr
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void llvm::HexagonLowerToMC(MachineInstr const* MI, MCInst& MCI,
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void llvm::HexagonLowerToMC(MachineInstr const* MI, MCInst& MCB,
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HexagonAsmPrinter& AP) {
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MCI.setOpcode(MI->getOpcode());
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if(MI->getOpcode() == Hexagon::ENDLOOP0){
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HexagonMCInstrInfo::setInnerLoop(MCB);
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return;
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}
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if(MI->getOpcode() == Hexagon::ENDLOOP1){
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HexagonMCInstrInfo::setOuterLoop(MCB);
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return;
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}
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MCInst* MCI = new (AP.OutContext) MCInst;
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MCI->setOpcode(MI->getOpcode());
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assert(MCI->getOpcode() == static_cast<unsigned>(MI->getOpcode()) &&
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"MCI opcode should have been set on construction");
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for (unsigned i = 0, e = MI->getNumOperands(); i < e; i++) {
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const MachineOperand &MO = MI->getOperand(i);
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@ -88,6 +102,7 @@ void llvm::HexagonLowerToMC(MachineInstr const* MI, MCInst& MCI,
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break;
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}
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MCI.addOperand(MCO);
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MCI->addOperand(MCO);
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}
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MCB.addOperand(MCOperand::createInst(MCI));
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}
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@ -190,7 +190,7 @@ namespace HexagonII {
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MO_GPREL
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};
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enum class InstParseBits : uint32_t {
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enum InstParseBits {
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INST_PARSE_MASK = 0x0000c000,
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INST_PARSE_PACKET_END = 0x0000c000,
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INST_PARSE_LOOP_END = 0x00008000,
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@ -28,7 +28,47 @@ using namespace llvm;
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#define GET_INSTRUCTION_NAME
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#include "HexagonGenAsmWriter.inc"
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const char HexagonInstPrinter::PacketPadding = '\t';
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HexagonAsmInstPrinter::HexagonAsmInstPrinter(MCInstPrinter *RawPrinter)
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: MCInstPrinter(*RawPrinter), RawPrinter(RawPrinter) {}
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void HexagonAsmInstPrinter::printInst(MCInst const *MI, raw_ostream &O,
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StringRef Annot,
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MCSubtargetInfo const &STI) {
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assert(HexagonMCInstrInfo::isBundle(*MI));
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assert(HexagonMCInstrInfo::bundleSize(*MI) <= HEXAGON_PACKET_SIZE);
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std::string Buffer;
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{
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raw_string_ostream TempStream(Buffer);
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RawPrinter->printInst(MI, TempStream, "", STI);
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}
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StringRef Contents(Buffer);
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auto PacketBundle = Contents.rsplit('\n');
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auto HeadTail = PacketBundle.first.split('\n');
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auto Preamble = "\t{\n\t\t";
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auto Separator = "";
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while(!HeadTail.first.empty()) {
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O << Separator;
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StringRef Inst;
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auto Duplex = HeadTail.first.split('\v');
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if(!Duplex.second.empty()){
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O << Duplex.first << "\n";
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Inst = Duplex.second;
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}
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else
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Inst = Duplex.first;
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O << Preamble;
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O << Inst;
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HeadTail = HeadTail.second.split('\n');
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Preamble = "";
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Separator = "\n\t\t";
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}
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O << "\n\t}" << PacketBundle.second;
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}
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void HexagonAsmInstPrinter::printRegName(raw_ostream &O, unsigned RegNo) const {
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RawPrinter->printRegName(O, RegNo);
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}
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// Return the minimum value that a constant extendable operand can have
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// without being extended.
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static int getMinValue(uint64_t TSFlags) {
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@ -77,48 +117,38 @@ void HexagonInstPrinter::printRegName(raw_ostream &OS, unsigned RegNo) const {
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OS << getRegisterName(RegNo);
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}
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void HexagonInstPrinter::printInst(MCInst const *MI, raw_ostream &O,
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void HexagonInstPrinter::setExtender(MCInst const &MCI) {
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HasExtender = HexagonMCInstrInfo::isImmext(MCI);
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}
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void HexagonInstPrinter::printInst(MCInst const *MI, raw_ostream &OS,
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StringRef Annot,
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const MCSubtargetInfo &STI) {
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const char startPacket = '{',
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endPacket = '}';
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// TODO: add outer HW loop when it's supported too.
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if (MI->getOpcode() == Hexagon::ENDLOOP0) {
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// Ending a harware loop is different from ending an regular packet.
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assert(HexagonMCInstrInfo::isPacketEnd(*MI) && "Loop-end must also end the packet");
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if (HexagonMCInstrInfo::isPacketBegin(*MI)) {
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// There must be a packet to end a loop.
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// FIXME: when shuffling is always run, this shouldn't be needed.
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MCInst Nop;
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StringRef NoAnnot;
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Nop.setOpcode (Hexagon::A2_nop);
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HexagonMCInstrInfo::setPacketBegin (Nop, HexagonMCInstrInfo::isPacketBegin(*MI));
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printInst (&Nop, O, NoAnnot, STI);
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}
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// Close the packet.
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if (HexagonMCInstrInfo::isPacketEnd(*MI))
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O << PacketPadding << endPacket;
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printInstruction(MI, O);
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}
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else {
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// Prefix the insn opening the packet.
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if (HexagonMCInstrInfo::isPacketBegin(*MI))
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O << PacketPadding << startPacket << '\n';
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printInstruction(MI, O);
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// Suffix the insn closing the packet.
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if (HexagonMCInstrInfo::isPacketEnd(*MI))
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// Suffix the packet in a new line always, since the GNU assembler has
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// issues with a closing brace on the same line as CONST{32,64}.
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O << '\n' << PacketPadding << endPacket;
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MCSubtargetInfo const &STI) {
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assert(HexagonMCInstrInfo::isBundle(*MI));
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assert(HexagonMCInstrInfo::bundleSize(*MI) <= HEXAGON_PACKET_SIZE);
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HasExtender = false;
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for (auto const &I : HexagonMCInstrInfo::bundleInstructions(*MI)) {
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MCInst const &MCI = *I.getInst();
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printInstruction(&MCI, OS);
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setExtender(MCI);
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OS << "\n";
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}
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printAnnotation(O, Annot);
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auto Separator = "";
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if (HexagonMCInstrInfo::isInnerLoop(*MI)) {
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OS << Separator;
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Separator = " ";
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MCInst ME;
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ME.setOpcode(Hexagon::ENDLOOP0);
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printInstruction(&ME, OS);
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}
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if (HexagonMCInstrInfo::isOuterLoop(*MI)) {
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OS << Separator;
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Separator = " ";
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MCInst ME;
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ME.setOpcode(Hexagon::ENDLOOP1);
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printInstruction(&ME, OS);
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}
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}
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void HexagonInstPrinter::printOperand(const MCInst *MI, unsigned OpNo,
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@ -18,6 +18,21 @@
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#include "llvm/MC/MCInstrInfo.h"
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namespace llvm {
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class HexagonAsmInstPrinter : public MCInstPrinter {
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public:
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HexagonAsmInstPrinter(MCInstPrinter *RawPrinter);
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void printInst(MCInst const *MI, raw_ostream &O, StringRef Annot,
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MCSubtargetInfo const &STI) override;
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void printRegName(raw_ostream &O, unsigned RegNo) const override;
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std::unique_ptr<MCInstPrinter> RawPrinter;
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};
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/// Prints bundles as a newline separated list of individual instructions
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/// Duplexes are separated by a vertical tab \v character
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/// A trailing line includes bundle properties such as endloop0/1
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///
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/// r0 = add(r1, r2)
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/// r0 = #0 \v jump 0x0
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/// :endloop0 :endloop1
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class HexagonInstPrinter : public MCInstPrinter {
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public:
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explicit HexagonInstPrinter(MCAsmInfo const &MAI,
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@ -74,11 +89,11 @@ namespace llvm {
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void printSymbol(const MCInst *MI, unsigned OpNo, raw_ostream &O, bool hi)
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const;
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static const char PacketPadding;
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private:
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const MCInstrInfo &MII;
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bool HasExtender;
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void setExtender(MCInst const &MCI);
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};
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} // end namespace llvm
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@ -32,16 +32,6 @@ using namespace Hexagon;
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STATISTIC(MCNumEmitted, "Number of MC instructions emitted");
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namespace {
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/// \brief 10.6 Instruction Packets
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/// Possible values for instruction packet parse field.
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enum class ParseField { duplex = 0x0, last0 = 0x1, last1 = 0x2, end = 0x3 };
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/// \brief Returns the packet bits based on instruction position.
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uint32_t getPacketBits(MCInst const &HMI) {
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unsigned const ParseFieldOffset = 14;
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ParseField Field = HexagonMCInstrInfo::isPacketEnd(HMI) ? ParseField::end
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: ParseField::last0;
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return static_cast<uint32_t>(Field) << ParseFieldOffset;
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}
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void emitLittleEndian(uint64_t Binary, raw_ostream &OS) {
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OS << static_cast<uint8_t>((Binary >> 0x00) & 0xff);
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OS << static_cast<uint8_t>((Binary >> 0x08) & 0xff);
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@ -53,15 +43,120 @@ void emitLittleEndian(uint64_t Binary, raw_ostream &OS) {
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HexagonMCCodeEmitter::HexagonMCCodeEmitter(MCInstrInfo const &aMII,
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MCContext &aMCT)
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: MCT(aMCT), MCII(aMII), Addend(new unsigned(0)),
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Extended(new bool(false)) {}
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Extended(new bool(false)), CurrentBundle(new MCInst const *) {}
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uint32_t HexagonMCCodeEmitter::parseBits(size_t Instruction, size_t Last,
|
||||
MCInst const &MCB,
|
||||
MCInst const &MCI) const {
|
||||
if (Instruction == 0) {
|
||||
if (HexagonMCInstrInfo::isInnerLoop(MCB)) {
|
||||
assert(Instruction != Last);
|
||||
return HexagonII::INST_PARSE_LOOP_END;
|
||||
}
|
||||
}
|
||||
if (Instruction == 1) {
|
||||
if (HexagonMCInstrInfo::isOuterLoop(MCB)) {
|
||||
assert(Instruction != Last);
|
||||
return HexagonII::INST_PARSE_LOOP_END;
|
||||
}
|
||||
}
|
||||
if(Instruction == Last)
|
||||
return HexagonII::INST_PARSE_PACKET_END;
|
||||
return HexagonII::INST_PARSE_NOT_END;
|
||||
}
|
||||
|
||||
void HexagonMCCodeEmitter::encodeInstruction(MCInst const &MI, raw_ostream &OS,
|
||||
SmallVectorImpl<MCFixup> &Fixups,
|
||||
MCSubtargetInfo const &STI) const {
|
||||
uint64_t Binary = getBinaryCodeForInstr(MI, Fixups, STI) | getPacketBits(MI);
|
||||
assert(HexagonMCInstrInfo::getDesc(MCII, MI).getSize() == 4 &&
|
||||
"All instructions should be 32bit");
|
||||
(void)&MCII;
|
||||
MCInst &HMB = const_cast<MCInst &>(MI);
|
||||
|
||||
assert(HexagonMCInstrInfo::isBundle(HMB));
|
||||
DEBUG(dbgs() << "Encoding bundle\n";);
|
||||
*Addend = 0;
|
||||
*Extended = false;
|
||||
*CurrentBundle = &MI;
|
||||
size_t Instruction = 0;
|
||||
size_t Last = HexagonMCInstrInfo::bundleSize(HMB) - 1;
|
||||
for (auto &I : HexagonMCInstrInfo::bundleInstructions(HMB)) {
|
||||
MCInst &HMI = const_cast<MCInst &>(*I.getInst());
|
||||
EncodeSingleInstruction(HMI, OS, Fixups, STI,
|
||||
parseBits(Instruction, Last, HMB, HMI),
|
||||
Instruction);
|
||||
*Extended = HexagonMCInstrInfo::isImmext(HMI);
|
||||
*Addend += HEXAGON_INSTR_SIZE;
|
||||
++Instruction;
|
||||
}
|
||||
return;
|
||||
}
|
||||
|
||||
/// EncodeSingleInstruction - Emit a single
|
||||
void HexagonMCCodeEmitter::EncodeSingleInstruction(
|
||||
const MCInst &MI, raw_ostream &OS, SmallVectorImpl<MCFixup> &Fixups,
|
||||
const MCSubtargetInfo &STI, uint32_t Parse, size_t Index) const {
|
||||
MCInst HMB = MI;
|
||||
assert(!HexagonMCInstrInfo::isBundle(HMB));
|
||||
uint64_t Binary;
|
||||
|
||||
// Pseudo instructions don't get encoded and shouldn't be here
|
||||
// in the first place!
|
||||
assert(!HexagonMCInstrInfo::getDesc(MCII, HMB).isPseudo() &&
|
||||
"pseudo-instruction found");
|
||||
DEBUG(dbgs() << "Encoding insn"
|
||||
" `" << HexagonMCInstrInfo::getName(MCII, HMB) << "'"
|
||||
"\n");
|
||||
|
||||
if (HexagonMCInstrInfo::isNewValue(MCII, HMB)) {
|
||||
// Calculate the new value distance to the associated producer
|
||||
MCOperand &MCO =
|
||||
HMB.getOperand(HexagonMCInstrInfo::getNewValueOp(MCII, HMB));
|
||||
unsigned SOffset = 0;
|
||||
unsigned Register = MCO.getReg();
|
||||
unsigned Register1;
|
||||
auto Instructions = HexagonMCInstrInfo::bundleInstructions(**CurrentBundle);
|
||||
auto i = Instructions.begin() + Index - 1;
|
||||
for (;; --i) {
|
||||
assert(i != Instructions.begin() - 1 && "Couldn't find producer");
|
||||
MCInst const &Inst = *i->getInst();
|
||||
if (HexagonMCInstrInfo::isImmext(Inst))
|
||||
continue;
|
||||
++SOffset;
|
||||
Register1 =
|
||||
HexagonMCInstrInfo::hasNewValue(MCII, Inst)
|
||||
? HexagonMCInstrInfo::getNewValueOperand(MCII, Inst).getReg()
|
||||
: static_cast<unsigned>(Hexagon::NoRegister);
|
||||
if (Register != Register1)
|
||||
// This isn't the register we're looking for
|
||||
continue;
|
||||
if (!HexagonMCInstrInfo::isPredicated(MCII, Inst))
|
||||
// Producer is unpredicated
|
||||
break;
|
||||
assert(HexagonMCInstrInfo::isPredicated(MCII, HMB) &&
|
||||
"Unpredicated consumer depending on predicated producer");
|
||||
if (HexagonMCInstrInfo::isPredicatedTrue(MCII, Inst) ==
|
||||
HexagonMCInstrInfo::isPredicatedTrue(MCII, HMB))
|
||||
// Producer predicate sense matched ours
|
||||
break;
|
||||
}
|
||||
// Hexagon PRM 10.11 Construct Nt from distance
|
||||
unsigned Offset = SOffset;
|
||||
Offset <<= 1;
|
||||
MCO.setReg(Offset + Hexagon::R0);
|
||||
}
|
||||
|
||||
Binary = getBinaryCodeForInstr(HMB, Fixups, STI);
|
||||
// Check for unimplemented instructions. Immediate extenders
|
||||
// are encoded as zero, so they need to be accounted for.
|
||||
if ((!Binary) &&
|
||||
((HMB.getOpcode() != DuplexIClass0) && (HMB.getOpcode() != A4_ext) &&
|
||||
(HMB.getOpcode() != A4_ext_b) && (HMB.getOpcode() != A4_ext_c) &&
|
||||
(HMB.getOpcode() != A4_ext_g))) {
|
||||
// Use a A2_nop for unimplemented instructions.
|
||||
DEBUG(dbgs() << "Unimplemented inst: "
|
||||
" `" << HexagonMCInstrInfo::getName(MCII, HMB) << "'"
|
||||
"\n");
|
||||
llvm_unreachable("Unimplemented Instruction");
|
||||
}
|
||||
Binary |= Parse;
|
||||
emitLittleEndian(Binary, OS);
|
||||
++MCNumEmitted;
|
||||
}
|
||||
|
||||
@ -30,6 +30,7 @@ class HexagonMCCodeEmitter : public MCCodeEmitter {
|
||||
MCInstrInfo const &MCII;
|
||||
std::unique_ptr<unsigned> Addend;
|
||||
std::unique_ptr<bool> Extended;
|
||||
std::unique_ptr<MCInst const *> CurrentBundle;
|
||||
|
||||
// helper routine for getMachineOpValue()
|
||||
unsigned getExprOpValue(const MCInst &MI, const MCOperand &MO,
|
||||
@ -39,12 +40,21 @@ class HexagonMCCodeEmitter : public MCCodeEmitter {
|
||||
public:
|
||||
HexagonMCCodeEmitter(MCInstrInfo const &aMII, MCContext &aMCT);
|
||||
|
||||
// Return parse bits for instruction `MCI' inside bundle `MCB'
|
||||
uint32_t parseBits(size_t Instruction, size_t Last, MCInst const &MCB,
|
||||
MCInst const &MCI) const;
|
||||
|
||||
MCSubtargetInfo const &getSubtargetInfo() const;
|
||||
|
||||
void encodeInstruction(MCInst const &MI, raw_ostream &OS,
|
||||
SmallVectorImpl<MCFixup> &Fixups,
|
||||
MCSubtargetInfo const &STI) const override;
|
||||
|
||||
void EncodeSingleInstruction(const MCInst &MI, raw_ostream &OS,
|
||||
SmallVectorImpl<MCFixup> &Fixups,
|
||||
const MCSubtargetInfo &STI,
|
||||
uint32_t Parse, size_t Index) const;
|
||||
|
||||
// \brief TableGen'erated function for getting the
|
||||
// binary encoding for an instruction.
|
||||
uint64_t getBinaryCodeForInstr(MCInst const &MI,
|
||||
|
||||
@ -11,13 +11,23 @@
|
||||
//
|
||||
//===----------------------------------------------------------------------===//
|
||||
|
||||
#include "HexagonMCInstrInfo.h"
|
||||
#include "Hexagon.h"
|
||||
#include "HexagonBaseInfo.h"
|
||||
#include "HexagonMCInstrInfo.h"
|
||||
|
||||
namespace llvm {
|
||||
void HexagonMCInstrInfo::AppendImplicitOperands(MCInst &MCI) {
|
||||
MCI.addOperand(MCOperand::createImm(0));
|
||||
MCI.addOperand(MCOperand::createInst(nullptr));
|
||||
iterator_range<MCInst::const_iterator>
|
||||
HexagonMCInstrInfo::bundleInstructions(MCInst const &MCI) {
|
||||
assert(isBundle(MCI));
|
||||
return iterator_range<MCInst::const_iterator>(
|
||||
MCI.begin() + bundleInstructionsOffset, MCI.end());
|
||||
}
|
||||
|
||||
size_t HexagonMCInstrInfo::bundleSize(MCInst const &MCI) {
|
||||
if (HexagonMCInstrInfo::isBundle(MCI))
|
||||
return (MCI.size() - bundleInstructionsOffset);
|
||||
else
|
||||
return (1);
|
||||
}
|
||||
|
||||
HexagonII::MemAccessSize
|
||||
@ -58,12 +68,6 @@ unsigned HexagonMCInstrInfo::getExtentBits(MCInstrInfo const &MCII,
|
||||
return ((F >> HexagonII::ExtentBitsPos) & HexagonII::ExtentBitsMask);
|
||||
}
|
||||
|
||||
std::bitset<16> HexagonMCInstrInfo::GetImplicitBits(MCInst const &MCI) {
|
||||
SanityCheckImplicitOperands(MCI);
|
||||
std::bitset<16> Bits(MCI.getOperand(MCI.getNumOperands() - 2).getImm());
|
||||
return Bits;
|
||||
}
|
||||
|
||||
// Return the max value that a constant extendable operand can have
|
||||
// without being extended.
|
||||
int HexagonMCInstrInfo::getMaxValue(MCInstrInfo const &MCII,
|
||||
@ -99,9 +103,14 @@ char const *HexagonMCInstrInfo::getName(MCInstrInfo const &MCII,
|
||||
return MCII.getName(MCI.getOpcode());
|
||||
}
|
||||
|
||||
// Return the operand that consumes or produces a new value.
|
||||
MCOperand const &HexagonMCInstrInfo::getNewValue(MCInstrInfo const &MCII,
|
||||
unsigned short HexagonMCInstrInfo::getNewValueOp(MCInstrInfo const &MCII,
|
||||
MCInst const &MCI) {
|
||||
const uint64_t F = HexagonMCInstrInfo::getDesc(MCII, MCI).TSFlags;
|
||||
return ((F >> HexagonII::NewValueOpPos) & HexagonII::NewValueOpMask);
|
||||
}
|
||||
|
||||
MCOperand const &HexagonMCInstrInfo::getNewValueOperand(MCInstrInfo const &MCII,
|
||||
MCInst const &MCI) {
|
||||
uint64_t const F = HexagonMCInstrInfo::getDesc(MCII, MCI).TSFlags;
|
||||
unsigned const O =
|
||||
(F >> HexagonII::NewValueOpPos) & HexagonII::NewValueOpMask;
|
||||
@ -128,6 +137,12 @@ bool HexagonMCInstrInfo::hasNewValue(MCInstrInfo const &MCII,
|
||||
return ((F >> HexagonII::hasNewValuePos) & HexagonII::hasNewValueMask);
|
||||
}
|
||||
|
||||
bool HexagonMCInstrInfo::isBundle(MCInst const &MCI) {
|
||||
auto Result = Hexagon::BUNDLE == MCI.getOpcode();
|
||||
assert(!Result || (MCI.size() > 0 && MCI.getOperand(0).isImm()));
|
||||
return Result;
|
||||
}
|
||||
|
||||
// Return whether the insn is an actual insn.
|
||||
bool HexagonMCInstrInfo::isCanon(MCInstrInfo const &MCII, MCInst const &MCI) {
|
||||
return (!HexagonMCInstrInfo::getDesc(MCII, MCI).isPseudo() &&
|
||||
@ -187,6 +202,18 @@ bool HexagonMCInstrInfo::isExtended(MCInstrInfo const &MCII,
|
||||
return (F >> HexagonII::ExtendedPos) & HexagonII::ExtendedMask;
|
||||
}
|
||||
|
||||
bool HexagonMCInstrInfo::isImmext(MCInst const &MCI) {
|
||||
auto Op = MCI.getOpcode();
|
||||
return (Op == Hexagon::A4_ext_b || Op == Hexagon::A4_ext_c ||
|
||||
Op == Hexagon::A4_ext_g || Op == Hexagon::A4_ext);
|
||||
}
|
||||
|
||||
bool HexagonMCInstrInfo::isInnerLoop(MCInst const &MCI) {
|
||||
assert(isBundle(MCI));
|
||||
int64_t Flags = MCI.getOperand(0).getImm();
|
||||
return (Flags & innerLoopMask) != 0;
|
||||
}
|
||||
|
||||
// Return whether the insn is a new-value consumer.
|
||||
bool HexagonMCInstrInfo::isNewValue(MCInstrInfo const &MCII,
|
||||
MCInst const &MCI) {
|
||||
@ -203,14 +230,23 @@ bool HexagonMCInstrInfo::isOperandExtended(MCInstrInfo const &MCII,
|
||||
OperandNum;
|
||||
}
|
||||
|
||||
bool HexagonMCInstrInfo::isPacketBegin(MCInst const &MCI) {
|
||||
std::bitset<16> Bits(GetImplicitBits(MCI));
|
||||
return Bits.test(packetBeginIndex);
|
||||
bool HexagonMCInstrInfo::isOuterLoop(MCInst const &MCI) {
|
||||
assert(isBundle(MCI));
|
||||
int64_t Flags = MCI.getOperand(0).getImm();
|
||||
return (Flags & outerLoopMask) != 0;
|
||||
}
|
||||
|
||||
bool HexagonMCInstrInfo::isPacketEnd(MCInst const &MCI) {
|
||||
std::bitset<16> Bits(GetImplicitBits(MCI));
|
||||
return Bits.test(packetEndIndex);
|
||||
bool HexagonMCInstrInfo::isPredicated(MCInstrInfo const &MCII,
|
||||
MCInst const &MCI) {
|
||||
const uint64_t F = HexagonMCInstrInfo::getDesc(MCII, MCI).TSFlags;
|
||||
return ((F >> HexagonII::PredicatedPos) & HexagonII::PredicatedMask);
|
||||
}
|
||||
|
||||
bool HexagonMCInstrInfo::isPredicatedTrue(MCInstrInfo const &MCII,
|
||||
MCInst const &MCI) {
|
||||
const uint64_t F = HexagonMCInstrInfo::getDesc(MCII, MCI).TSFlags;
|
||||
return (
|
||||
!((F >> HexagonII::PredicatedFalsePos) & HexagonII::PredicatedFalseMask));
|
||||
}
|
||||
|
||||
// Return whether the insn is a prefix.
|
||||
@ -224,25 +260,26 @@ bool HexagonMCInstrInfo::isSolo(MCInstrInfo const &MCII, MCInst const &MCI) {
|
||||
return ((F >> HexagonII::SoloPos) & HexagonII::SoloMask);
|
||||
}
|
||||
|
||||
void HexagonMCInstrInfo::resetPacket(MCInst &MCI) {
|
||||
setPacketBegin(MCI, false);
|
||||
setPacketEnd(MCI, false);
|
||||
void HexagonMCInstrInfo::padEndloop(MCInst &MCB) {
|
||||
MCInst Nop;
|
||||
Nop.setOpcode(Hexagon::A2_nop);
|
||||
assert(isBundle(MCB));
|
||||
while ((HexagonMCInstrInfo::isInnerLoop(MCB) &&
|
||||
(HexagonMCInstrInfo::bundleSize(MCB) < HEXAGON_PACKET_INNER_SIZE)) ||
|
||||
((HexagonMCInstrInfo::isOuterLoop(MCB) &&
|
||||
(HexagonMCInstrInfo::bundleSize(MCB) < HEXAGON_PACKET_OUTER_SIZE))))
|
||||
MCB.addOperand(MCOperand::createInst(new MCInst(Nop)));
|
||||
}
|
||||
|
||||
void HexagonMCInstrInfo::SetImplicitBits(MCInst &MCI, std::bitset<16> Bits) {
|
||||
SanityCheckImplicitOperands(MCI);
|
||||
MCI.getOperand(MCI.getNumOperands() - 2).setImm(Bits.to_ulong());
|
||||
void HexagonMCInstrInfo::setInnerLoop(MCInst &MCI) {
|
||||
assert(isBundle(MCI));
|
||||
MCOperand &Operand = MCI.getOperand(0);
|
||||
Operand.setImm(Operand.getImm() | innerLoopMask);
|
||||
}
|
||||
|
||||
void HexagonMCInstrInfo::setPacketBegin(MCInst &MCI, bool f) {
|
||||
std::bitset<16> Bits(GetImplicitBits(MCI));
|
||||
Bits.set(packetBeginIndex, f);
|
||||
SetImplicitBits(MCI, Bits);
|
||||
}
|
||||
|
||||
void HexagonMCInstrInfo::setPacketEnd(MCInst &MCI, bool f) {
|
||||
std::bitset<16> Bits(GetImplicitBits(MCI));
|
||||
Bits.set(packetEndIndex, f);
|
||||
SetImplicitBits(MCI, Bits);
|
||||
void HexagonMCInstrInfo::setOuterLoop(MCInst &MCI) {
|
||||
assert(isBundle(MCI));
|
||||
MCOperand &Operand = MCI.getOperand(0);
|
||||
Operand.setImm(Operand.getImm() | outerLoopMask);
|
||||
}
|
||||
}
|
||||
|
||||
@ -28,7 +28,19 @@ namespace HexagonII {
|
||||
enum class MemAccessSize;
|
||||
}
|
||||
namespace HexagonMCInstrInfo {
|
||||
void AppendImplicitOperands(MCInst &MCI);
|
||||
size_t const innerLoopOffset = 0;
|
||||
int64_t const innerLoopMask = 1 << innerLoopOffset;
|
||||
|
||||
size_t const outerLoopOffset = 1;
|
||||
int64_t const outerLoopMask = 1 << outerLoopOffset;
|
||||
|
||||
size_t const bundleInstructionsOffset = 1;
|
||||
|
||||
// Returns the number of instructions in the bundle
|
||||
size_t bundleSize(MCInst const &MCI);
|
||||
|
||||
// Returns a iterator range of instructions in this bundle
|
||||
iterator_range<MCInst::const_iterator> bundleInstructions(MCInst const &MCI);
|
||||
|
||||
// Return memory access size
|
||||
HexagonII::MemAccessSize getAccessSize(MCInstrInfo const &MCII,
|
||||
@ -48,8 +60,6 @@ unsigned getExtentAlignment(MCInstrInfo const &MCII, MCInst const &MCI);
|
||||
// Return the number of logical bits of the extendable operand
|
||||
unsigned getExtentBits(MCInstrInfo const &MCII, MCInst const &MCI);
|
||||
|
||||
std::bitset<16> GetImplicitBits(MCInst const &MCI);
|
||||
|
||||
// Return the max value that a constant extendable operand can have
|
||||
// without being extended.
|
||||
int getMaxValue(MCInstrInfo const &MCII, MCInst const &MCI);
|
||||
@ -61,8 +71,11 @@ int getMinValue(MCInstrInfo const &MCII, MCInst const &MCI);
|
||||
// Return instruction name
|
||||
char const *getName(MCInstrInfo const &MCII, MCInst const &MCI);
|
||||
|
||||
// Return the operand index for the new value.
|
||||
unsigned short getNewValueOp(MCInstrInfo const &MCII, MCInst const &MCI);
|
||||
|
||||
// Return the operand that consumes or produces a new value.
|
||||
MCOperand const &getNewValue(MCInstrInfo const &MCII, MCInst const &MCI);
|
||||
MCOperand const &getNewValueOperand(MCInstrInfo const &MCII, MCInst const &MCI);
|
||||
|
||||
// Return the Hexagon ISA class for the insn.
|
||||
unsigned getType(MCInstrInfo const &MCII, MCInst const &MCI);
|
||||
@ -70,6 +83,9 @@ unsigned getType(MCInstrInfo const &MCII, MCInst const &MCI);
|
||||
// Return whether the instruction is a legal new-value producer.
|
||||
bool hasNewValue(MCInstrInfo const &MCII, MCInst const &MCI);
|
||||
|
||||
// Returns whether this MCInst is a wellformed bundle
|
||||
bool isBundle(MCInst const &MCI);
|
||||
|
||||
// Return whether the insn is an actual insn.
|
||||
bool isCanon(MCInstrInfo const &MCII, MCInst const &MCI);
|
||||
|
||||
@ -82,6 +98,12 @@ bool isExtendable(MCInstrInfo const &MCII, MCInst const &MCI);
|
||||
// Return whether the instruction must be always extended.
|
||||
bool isExtended(MCInstrInfo const &MCII, MCInst const &MCI);
|
||||
|
||||
// Returns whether this instruction is an immediate extender
|
||||
bool isImmext(MCInst const &MCI);
|
||||
|
||||
// Returns whether this bundle is an endloop0
|
||||
bool isInnerLoop(MCInst const &MCI);
|
||||
|
||||
// Return whether the insn is a new-value consumer.
|
||||
bool isNewValue(MCInstrInfo const &MCII, MCInst const &MCI);
|
||||
|
||||
@ -89,9 +111,14 @@ bool isNewValue(MCInstrInfo const &MCII, MCInst const &MCI);
|
||||
bool isOperandExtended(MCInstrInfo const &MCII, MCInst const &MCI,
|
||||
unsigned short OperandNum);
|
||||
|
||||
bool isPacketBegin(MCInst const &MCI);
|
||||
// Returns whether this bundle is an endloop1
|
||||
bool isOuterLoop(MCInst const &MCI);
|
||||
|
||||
bool isPacketEnd(MCInst const &MCI);
|
||||
// Return whether this instruction is predicated
|
||||
bool isPredicated(MCInstrInfo const &MCII, MCInst const &MCI);
|
||||
|
||||
// Return whether the predicate sense is true
|
||||
bool isPredicatedTrue(MCInstrInfo const &MCII, MCInst const &MCI);
|
||||
|
||||
// Return whether the insn is a prefix.
|
||||
bool isPrefix(MCInstrInfo const &MCII, MCInst const &MCI);
|
||||
@ -99,23 +126,14 @@ bool isPrefix(MCInstrInfo const &MCII, MCInst const &MCI);
|
||||
// Return whether the insn is solo, i.e., cannot be in a packet.
|
||||
bool isSolo(MCInstrInfo const &MCII, MCInst const &MCI);
|
||||
|
||||
static const size_t packetBeginIndex = 0;
|
||||
static const size_t packetEndIndex = 1;
|
||||
// Pad the bundle with nops to satisfy endloop requirements
|
||||
void padEndloop(MCInst &MCI);
|
||||
|
||||
void resetPacket(MCInst &MCI);
|
||||
// Marks a bundle as endloop0
|
||||
void setInnerLoop(MCInst &MCI);
|
||||
|
||||
inline void SanityCheckImplicitOperands(MCInst const &MCI) {
|
||||
assert(MCI.getNumOperands() >= 2 && "At least the two implicit operands");
|
||||
assert(MCI.getOperand(MCI.getNumOperands() - 1).isInst() &&
|
||||
"Implicit bits and flags");
|
||||
assert(MCI.getOperand(MCI.getNumOperands() - 2).isImm() && "Parent pointer");
|
||||
}
|
||||
|
||||
void SetImplicitBits(MCInst &MCI, std::bitset<16> Bits);
|
||||
|
||||
void setPacketBegin(MCInst &MCI, bool Y);
|
||||
|
||||
void setPacketEnd(MCInst &MCI, bool Y);
|
||||
// Marks a bundle as endloop1
|
||||
void setOuterLoop(MCInst &MCI);
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
@ -1,4 +1,5 @@
|
||||
; RUN: llc -march=hexagon -mcpu=hexagonv4 < %s | FileCheck %s
|
||||
; XFAIL:
|
||||
|
||||
; Check that the packetizer generates valid packets with constant
|
||||
; extended instructions.
|
||||
|
||||
@ -1,4 +1,5 @@
|
||||
; RUN: llc -march=hexagon -mcpu=hexagonv4 < %s | FileCheck %s
|
||||
; XFAIL:
|
||||
; Check that the packetizer generates valid packets with constant
|
||||
; extended add and base+offset store instructions.
|
||||
|
||||
|
||||
@ -1,5 +1,5 @@
|
||||
;; RUN: llc -mtriple=hexagon-unknown-elf -filetype=obj %s -o - \
|
||||
;; RUN: | llvm-objdump -s - | FileCheck %s
|
||||
;; RUN: | llvm-objdump -d - | FileCheck %s
|
||||
|
||||
define i1 @foo (i32 %a, i32 %b)
|
||||
{
|
||||
@ -7,4 +7,6 @@ define i1 @foo (i32 %a, i32 %b)
|
||||
ret i1 %1
|
||||
}
|
||||
|
||||
; CHECK: 0000 004100f2 00404089 00c09f52
|
||||
; CHECK: p0 = cmp.eq(r0, r1)
|
||||
; CHECK: r0 = p0
|
||||
; CHECK: jumpr r31
|
||||
|
||||
@ -1,5 +1,5 @@
|
||||
;; RUN: llc -mtriple=hexagon-unknown-elf -filetype=obj %s -o - \
|
||||
;; RUN: | llvm-objdump -s - | FileCheck %s
|
||||
;; RUN: | llvm-objdump -d - | FileCheck %s
|
||||
|
||||
define i1 @foo (i32 %a)
|
||||
{
|
||||
@ -7,4 +7,6 @@ define i1 @foo (i32 %a)
|
||||
ret i1 %1
|
||||
}
|
||||
|
||||
; CHECK: 0000 40450075 00404089 00c09f52
|
||||
; CHECK: p0 = cmp.eq(r0, #42)
|
||||
; CHECK: r0 = p0
|
||||
; CHECK: jumpr r31
|
||||
|
||||
@ -1,5 +1,5 @@
|
||||
;; RUN: llc -mtriple=hexagon-unknown-elf -filetype=obj %s -o - \
|
||||
;; RUN: | llvm-objdump -s - | FileCheck %s
|
||||
;; RUN: | llvm-objdump -d - | FileCheck %s
|
||||
|
||||
define i1 @foo (i32 %a, i32 %b)
|
||||
{
|
||||
@ -7,4 +7,6 @@ define i1 @foo (i32 %a, i32 %b)
|
||||
ret i1 %1
|
||||
}
|
||||
|
||||
; CHECK: 0000 004140f2 00404089 00c09f52
|
||||
; CHECK: p0 = cmp.gt(r0, r1)
|
||||
; CHECK: r0 = p0
|
||||
; CHECK: jumpr r31 }
|
||||
@ -1,5 +1,5 @@
|
||||
;; RUN: llc -mtriple=hexagon-unknown-elf -filetype=obj %s -o - \
|
||||
;; RUN: | llvm-objdump -s - | FileCheck %s
|
||||
;; RUN: | llvm-objdump -d - | FileCheck %s
|
||||
|
||||
define i1 @foo (i32 %a)
|
||||
{
|
||||
@ -7,4 +7,6 @@ define i1 @foo (i32 %a)
|
||||
ret i1 %1
|
||||
}
|
||||
|
||||
; CHECK: 0000 40454075 00404089 00c09f52
|
||||
; CHECK: p0 = cmp.gt(r0, #42)
|
||||
; CHECK: r0 = p0
|
||||
; CHECK: jumpr r31
|
||||
|
||||
@ -1,5 +1,5 @@
|
||||
;; RUN: llc -mtriple=hexagon-unknown-elf -filetype=obj %s -o - \
|
||||
;; RUN: | llvm-objdump -s - | FileCheck %s
|
||||
;; RUN: | llvm-objdump -d - | FileCheck %s
|
||||
|
||||
define i1 @foo (i32 %a, i32 %b)
|
||||
{
|
||||
@ -7,4 +7,6 @@ define i1 @foo (i32 %a, i32 %b)
|
||||
ret i1 %1
|
||||
}
|
||||
|
||||
; CHECK: 0000 004041f2 00404089 00c09f52
|
||||
; CHECK: p0 = cmp.gt(r1, r0)
|
||||
; CHECK: r0 = p0
|
||||
; CHECK: jumpr r31
|
||||
|
||||
@ -1,5 +1,5 @@
|
||||
;; RUN: llc -mtriple=hexagon-unknown-elf -filetype=obj %s -o - \
|
||||
;; RUN: | llvm-objdump -s - | FileCheck %s
|
||||
;; RUN: | llvm-objdump -d - | FileCheck %s
|
||||
|
||||
define i1 @foo (i32 %a, i32 %b)
|
||||
{
|
||||
@ -7,4 +7,6 @@ define i1 @foo (i32 %a, i32 %b)
|
||||
ret i1 %1
|
||||
}
|
||||
|
||||
; CHECK: 0000 004160f2 00404089 00c09f52
|
||||
; CHECK: p0 = cmp.gtu(r0, r1)
|
||||
; CHECK: r0 = p0
|
||||
; CHECK: jumpr r31
|
||||
|
||||
@ -1,5 +1,5 @@
|
||||
;; RUN: llc -mtriple=hexagon-unknown-elf -filetype=obj %s -o - \
|
||||
;; RUN: | llvm-objdump -s - | FileCheck %s
|
||||
;; RUN: | llvm-objdump -d - | FileCheck %s
|
||||
|
||||
define i1 @foo (i32 %a)
|
||||
{
|
||||
@ -7,4 +7,6 @@ define i1 @foo (i32 %a)
|
||||
ret i1 %1
|
||||
}
|
||||
|
||||
; CHECK: 0000 40458075 00404089 00c09f52
|
||||
; CHECK: p0 = cmp.gtu(r0, #42)
|
||||
; CHECK: r0 = p0
|
||||
; CHECK: jumpr r31
|
||||
|
||||
@ -1,5 +1,5 @@
|
||||
;; RUN: llc -mtriple=hexagon-unknown-elf -filetype=obj %s -o - \
|
||||
;; RUN: | llvm-objdump -s - | FileCheck %s
|
||||
;; RUN: | llvm-objdump -d - | FileCheck %s
|
||||
|
||||
define i1 @foo (i32 %a, i32 %b)
|
||||
{
|
||||
@ -7,4 +7,6 @@ define i1 @foo (i32 %a, i32 %b)
|
||||
ret i1 %1
|
||||
}
|
||||
|
||||
; CHECK: 0000 004061f2 00404089 00c09f52
|
||||
; CHECK: p0 = cmp.gtu(r1, r0)
|
||||
; CHECK: r0 = p0
|
||||
; CHECK: jumpr r31
|
||||
@ -205,7 +205,7 @@ namespace {
|
||||
class PrettyPrinter {
|
||||
public:
|
||||
virtual ~PrettyPrinter(){}
|
||||
virtual void printInst(MCInstPrinter &IP, const MCInst *MI, bool ShowRawInsn,
|
||||
virtual void printInst(MCInstPrinter &IP, const MCInst *MI,
|
||||
ArrayRef<uint8_t> Bytes, uint64_t Address,
|
||||
raw_ostream &OS, StringRef Annot,
|
||||
MCSubtargetInfo const &STI) {
|
||||
@ -218,8 +218,66 @@ public:
|
||||
}
|
||||
};
|
||||
PrettyPrinter PrettyPrinterInst;
|
||||
class HexagonPrettyPrinter : public PrettyPrinter {
|
||||
public:
|
||||
void printLead(ArrayRef<uint8_t> Bytes, uint64_t Address,
|
||||
raw_ostream &OS) {
|
||||
uint32_t opcode =
|
||||
(Bytes[3] << 24) | (Bytes[2] << 16) | (Bytes[1] << 8) | Bytes[0];
|
||||
OS << format("%8" PRIx64 ":", Address);
|
||||
if (!NoShowRawInsn) {
|
||||
OS << "\t";
|
||||
dumpBytes(Bytes.slice(0, 4), OS);
|
||||
OS << format("%08" PRIx32, opcode);
|
||||
}
|
||||
}
|
||||
void printInst(MCInstPrinter &IP, const MCInst *MI,
|
||||
ArrayRef<uint8_t> Bytes, uint64_t Address,
|
||||
raw_ostream &OS, StringRef Annot,
|
||||
MCSubtargetInfo const &STI) override {
|
||||
std::string Buffer;
|
||||
{
|
||||
raw_string_ostream TempStream(Buffer);
|
||||
IP.printInst(MI, TempStream, "", STI);
|
||||
}
|
||||
StringRef Contents(Buffer);
|
||||
// Split off bundle attributes
|
||||
auto PacketBundle = Contents.rsplit('\n');
|
||||
// Split off first instruction from the rest
|
||||
auto HeadTail = PacketBundle.first.split('\n');
|
||||
auto Preamble = " { ";
|
||||
auto Separator = "";
|
||||
while(!HeadTail.first.empty()) {
|
||||
OS << Separator;
|
||||
Separator = "\n";
|
||||
printLead(Bytes, Address, OS);
|
||||
OS << Preamble;
|
||||
Preamble = " ";
|
||||
StringRef Inst;
|
||||
auto Duplex = HeadTail.first.split('\v');
|
||||
if(!Duplex.second.empty()){
|
||||
OS << Duplex.first;
|
||||
OS << "; ";
|
||||
Inst = Duplex.second;
|
||||
}
|
||||
else
|
||||
Inst = HeadTail.first;
|
||||
OS << Inst;
|
||||
Bytes = Bytes.slice(4);
|
||||
Address += 4;
|
||||
HeadTail = HeadTail.second.split('\n');
|
||||
}
|
||||
OS << " } " << PacketBundle.second;
|
||||
}
|
||||
};
|
||||
HexagonPrettyPrinter HexagonPrettyPrinterInst;
|
||||
PrettyPrinter &selectPrettyPrinter(Triple const &Triple, MCInstPrinter &IP) {
|
||||
return PrettyPrinterInst;
|
||||
switch(Triple.getArch()) {
|
||||
default:
|
||||
return PrettyPrinterInst;
|
||||
case Triple::hexagon:
|
||||
return HexagonPrettyPrinterInst;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
@ -406,7 +464,7 @@ static void DisassembleObject(const ObjectFile *Obj, bool InlineRelocs) {
|
||||
if (DisAsm->getInstruction(Inst, Size, Bytes.slice(Index),
|
||||
SectionAddr + Index, DebugOut,
|
||||
CommentStream)) {
|
||||
PIP.printInst(*IP, &Inst, !NoShowRawInsn,
|
||||
PIP.printInst(*IP, &Inst,
|
||||
Bytes.slice(Index, Size),
|
||||
SectionAddr + Index, outs(), "", *STI);
|
||||
outs() << CommentStream.str();
|
||||
|
||||
Loading…
Reference in New Issue
Block a user