mirror of
https://github.com/RPCS3/llvm-mirror.git
synced 2024-11-26 04:32:44 +01:00
expose the set of values types holdable in a regclass to clients
llvm-svn: 26307
This commit is contained in:
parent
b5b7cc99c4
commit
086fd0f862
@ -44,8 +44,9 @@ public:
|
||||
typedef const unsigned* iterator;
|
||||
typedef const unsigned* const_iterator;
|
||||
|
||||
typedef const MVT::ValueType* vt_iterator;
|
||||
private:
|
||||
const MVT::ValueType* VTs;
|
||||
const vt_iterator VTs;
|
||||
const unsigned RegSize, Alignment; // Size & Alignment of register in bytes
|
||||
const iterator RegsBegin, RegsEnd;
|
||||
public:
|
||||
@ -84,6 +85,21 @@ public:
|
||||
return false;
|
||||
}
|
||||
|
||||
/// vt_begin - Loop over all of the value types that can be represented by
|
||||
/// values in this register class.
|
||||
vt_iterator vt_begin() const {
|
||||
return VTs;
|
||||
}
|
||||
|
||||
/// vt_begin - Loop over all of the value types that can be represented by
|
||||
/// values in this register class.
|
||||
vt_iterator vt_end() const {
|
||||
vt_iterator I = VTs;
|
||||
while (*I != MVT::Other) ++I;
|
||||
return I;
|
||||
}
|
||||
|
||||
|
||||
/// allocation_order_begin/end - These methods define a range of registers
|
||||
/// which specify the registers in this class that are valid to register
|
||||
/// allocate, and the preferred order to allocate them in. For example,
|
||||
|
Loading…
Reference in New Issue
Block a user