diff --git a/include/llvm/CodeGen/DFAPacketizer.h b/include/llvm/CodeGen/DFAPacketizer.h index 9d25fd377b7..a0826059e09 100644 --- a/include/llvm/CodeGen/DFAPacketizer.h +++ b/include/llvm/CodeGen/DFAPacketizer.h @@ -107,9 +107,7 @@ protected: std::map MIToSUnit; public: - VLIWPacketizerList( - MachineFunction &MF, MachineLoopInfo &MLI, MachineDominatorTree &MDT, - bool IsPostRA); + VLIWPacketizerList(MachineFunction &MF, MachineLoopInfo &MLI, bool IsPostRA); virtual ~VLIWPacketizerList(); diff --git a/include/llvm/CodeGen/MachineScheduler.h b/include/llvm/CodeGen/MachineScheduler.h index 6f48b8102b8..c5f66a86a5e 100644 --- a/include/llvm/CodeGen/MachineScheduler.h +++ b/include/llvm/CodeGen/MachineScheduler.h @@ -250,7 +250,7 @@ protected: public: ScheduleDAGMI(MachineSchedContext *C, std::unique_ptr S, bool IsPostRA) - : ScheduleDAGInstrs(*C->MF, C->MLI, C->MDT, IsPostRA, + : ScheduleDAGInstrs(*C->MF, C->MLI, IsPostRA, /*RemoveKillFlags=*/IsPostRA, C->LIS), AA(C->AA), SchedImpl(std::move(S)), Topo(SUnits, &ExitSU), CurrentTop(), CurrentBottom(), NextClusterPred(nullptr), NextClusterSucc(nullptr) { diff --git a/include/llvm/CodeGen/ScheduleDAGInstrs.h b/include/llvm/CodeGen/ScheduleDAGInstrs.h index 9a6c848bfea..00dd8f9a633 100644 --- a/include/llvm/CodeGen/ScheduleDAGInstrs.h +++ b/include/llvm/CodeGen/ScheduleDAGInstrs.h @@ -76,7 +76,6 @@ namespace llvm { class ScheduleDAGInstrs : public ScheduleDAG { protected: const MachineLoopInfo *MLI; - const MachineDominatorTree *MDT; const MachineFrameInfo *MFI; /// Live Intervals provides reaching defs in preRA scheduling. @@ -155,7 +154,6 @@ namespace llvm { public: explicit ScheduleDAGInstrs(MachineFunction &mf, const MachineLoopInfo *mli, - const MachineDominatorTree *mdt, bool IsPostRAFlag, bool RemoveKillFlags = false, LiveIntervals *LIS = nullptr); diff --git a/lib/CodeGen/DFAPacketizer.cpp b/lib/CodeGen/DFAPacketizer.cpp index 67a2664d56a..e0266cace2e 100644 --- a/lib/CodeGen/DFAPacketizer.cpp +++ b/lib/CodeGen/DFAPacketizer.cpp @@ -106,16 +106,15 @@ namespace llvm { class DefaultVLIWScheduler : public ScheduleDAGInstrs { public: DefaultVLIWScheduler(MachineFunction &MF, MachineLoopInfo &MLI, - MachineDominatorTree &MDT, bool IsPostRA); + bool IsPostRA); // Schedule - Actual scheduling work. void schedule() override; }; } -DefaultVLIWScheduler::DefaultVLIWScheduler( - MachineFunction &MF, MachineLoopInfo &MLI, MachineDominatorTree &MDT, - bool IsPostRA) : - ScheduleDAGInstrs(MF, &MLI, &MDT, IsPostRA) { +DefaultVLIWScheduler::DefaultVLIWScheduler(MachineFunction &MF, + MachineLoopInfo &MLI, bool IsPostRA) + : ScheduleDAGInstrs(MF, &MLI, IsPostRA) { CanHandleTerminators = true; } @@ -125,12 +124,12 @@ void DefaultVLIWScheduler::schedule() { } // VLIWPacketizerList Ctor -VLIWPacketizerList::VLIWPacketizerList( - MachineFunction &MF, MachineLoopInfo &MLI, MachineDominatorTree &MDT, - bool IsPostRA) : TM(MF.getTarget()), MF(MF) { +VLIWPacketizerList::VLIWPacketizerList(MachineFunction &MF, + MachineLoopInfo &MLI, bool IsPostRA) + : TM(MF.getTarget()), MF(MF) { TII = TM.getSubtargetImpl()->getInstrInfo(); ResourceTracker = TII->CreateTargetScheduleState(&TM, nullptr); - VLIWScheduler = new DefaultVLIWScheduler(MF, MLI, MDT, IsPostRA); + VLIWScheduler = new DefaultVLIWScheduler(MF, MLI, IsPostRA); } // VLIWPacketizerList Dtor diff --git a/lib/CodeGen/PostRASchedulerList.cpp b/lib/CodeGen/PostRASchedulerList.cpp index 5a87fd938ea..b95e7c3042e 100644 --- a/lib/CodeGen/PostRASchedulerList.cpp +++ b/lib/CodeGen/PostRASchedulerList.cpp @@ -137,10 +137,10 @@ namespace { public: SchedulePostRATDList( - MachineFunction &MF, MachineLoopInfo &MLI, MachineDominatorTree &MDT, - AliasAnalysis *AA, const RegisterClassInfo&, - TargetSubtargetInfo::AntiDepBreakMode AntiDepMode, - SmallVectorImpl &CriticalPathRCs); + MachineFunction &MF, MachineLoopInfo &MLI, AliasAnalysis *AA, + const RegisterClassInfo &, + TargetSubtargetInfo::AntiDepBreakMode AntiDepMode, + SmallVectorImpl &CriticalPathRCs); ~SchedulePostRATDList(); @@ -193,11 +193,11 @@ INITIALIZE_PASS(PostRAScheduler, "post-RA-sched", "Post RA top-down list latency scheduler", false, false) SchedulePostRATDList::SchedulePostRATDList( - MachineFunction &MF, MachineLoopInfo &MLI, MachineDominatorTree &MDT, - AliasAnalysis *AA, const RegisterClassInfo &RCI, - TargetSubtargetInfo::AntiDepBreakMode AntiDepMode, - SmallVectorImpl &CriticalPathRCs) - : ScheduleDAGInstrs(MF, &MLI, &MDT, /*IsPostRA=*/true), AA(AA), EndIndex(0) { + MachineFunction &MF, MachineLoopInfo &MLI, AliasAnalysis *AA, + const RegisterClassInfo &RCI, + TargetSubtargetInfo::AntiDepBreakMode AntiDepMode, + SmallVectorImpl &CriticalPathRCs) + : ScheduleDAGInstrs(MF, &MLI, /*IsPostRA=*/true), AA(AA), EndIndex(0) { const TargetMachine &TM = MF.getTarget(); const InstrItineraryData *InstrItins = @@ -269,7 +269,6 @@ bool PostRAScheduler::runOnMachineFunction(MachineFunction &Fn) { TII = Fn.getSubtarget().getInstrInfo(); MachineLoopInfo &MLI = getAnalysis(); - MachineDominatorTree &MDT = getAnalysis(); AliasAnalysis *AA = &getAnalysis(); TargetPassConfig *PassConfig = &getAnalysis(); @@ -303,7 +302,7 @@ bool PostRAScheduler::runOnMachineFunction(MachineFunction &Fn) { DEBUG(dbgs() << "PostRAScheduler\n"); - SchedulePostRATDList Scheduler(Fn, MLI, MDT, AA, RegClassInfo, AntiDepMode, + SchedulePostRATDList Scheduler(Fn, MLI, AA, RegClassInfo, AntiDepMode, CriticalPathRCs); // Loop over all of the basic blocks diff --git a/lib/CodeGen/ScheduleDAGInstrs.cpp b/lib/CodeGen/ScheduleDAGInstrs.cpp index e1278d05597..2ce6f8b9823 100644 --- a/lib/CodeGen/ScheduleDAGInstrs.cpp +++ b/lib/CodeGen/ScheduleDAGInstrs.cpp @@ -51,11 +51,10 @@ static cl::opt UseTBAA("use-tbaa-in-sched-mi", cl::Hidden, ScheduleDAGInstrs::ScheduleDAGInstrs(MachineFunction &mf, const MachineLoopInfo *mli, - const MachineDominatorTree *mdt, bool IsPostRAFlag, bool RemoveKillFlags, LiveIntervals *lis) - : ScheduleDAG(mf), MLI(mli), MDT(mdt), MFI(mf.getFrameInfo()), LIS(lis), + : ScheduleDAG(mf), MLI(mli), MFI(mf.getFrameInfo()), LIS(lis), IsPostRA(IsPostRAFlag), RemoveKillFlags(RemoveKillFlags), CanHandleTerminators(false), FirstDbgValue(nullptr) { assert((IsPostRA || LIS) && "PreRA scheduling requires LiveIntervals"); diff --git a/lib/Target/Hexagon/HexagonVLIWPacketizer.cpp b/lib/Target/Hexagon/HexagonVLIWPacketizer.cpp index 632be030102..ee7e00befd4 100644 --- a/lib/Target/Hexagon/HexagonVLIWPacketizer.cpp +++ b/lib/Target/Hexagon/HexagonVLIWPacketizer.cpp @@ -118,7 +118,6 @@ namespace { public: // Ctor. HexagonPacketizerList(MachineFunction &MF, MachineLoopInfo &MLI, - MachineDominatorTree &MDT, const MachineBranchProbabilityInfo *MBPI); // initPacketizerState - initialize some internal flags. @@ -184,20 +183,19 @@ INITIALIZE_PASS_END(HexagonPacketizer, "packets", "Hexagon Packetizer", // HexagonPacketizerList Ctor. HexagonPacketizerList::HexagonPacketizerList( - MachineFunction &MF, MachineLoopInfo &MLI,MachineDominatorTree &MDT, - const MachineBranchProbabilityInfo *MBPI) - : VLIWPacketizerList(MF, MLI, MDT, true){ + MachineFunction &MF, MachineLoopInfo &MLI, + const MachineBranchProbabilityInfo *MBPI) + : VLIWPacketizerList(MF, MLI, true) { this->MBPI = MBPI; } bool HexagonPacketizer::runOnMachineFunction(MachineFunction &Fn) { const TargetInstrInfo *TII = Fn.getSubtarget().getInstrInfo(); MachineLoopInfo &MLI = getAnalysis(); - MachineDominatorTree &MDT = getAnalysis(); const MachineBranchProbabilityInfo *MBPI = &getAnalysis(); // Instantiate the packetizer. - HexagonPacketizerList Packetizer(Fn, MLI, MDT, MBPI); + HexagonPacketizerList Packetizer(Fn, MLI, MBPI); // DFA state table should not be empty. assert(Packetizer.getResourceTracker() && "Empty DFA table!"); diff --git a/lib/Target/R600/R600Packetizer.cpp b/lib/Target/R600/R600Packetizer.cpp index cb2eeeaaf7d..ddf68c91cdf 100644 --- a/lib/Target/R600/R600Packetizer.cpp +++ b/lib/Target/R600/R600Packetizer.cpp @@ -148,9 +148,8 @@ private: } public: // Ctor. - R600PacketizerList(MachineFunction &MF, MachineLoopInfo &MLI, - MachineDominatorTree &MDT) - : VLIWPacketizerList(MF, MLI, MDT, true), + R600PacketizerList(MachineFunction &MF, MachineLoopInfo &MLI) + : VLIWPacketizerList(MF, MLI, true), TII(static_cast( MF.getSubtarget().getInstrInfo())), TRI(TII->getRegisterInfo()) { @@ -331,10 +330,9 @@ public: bool R600Packetizer::runOnMachineFunction(MachineFunction &Fn) { const TargetInstrInfo *TII = Fn.getSubtarget().getInstrInfo(); MachineLoopInfo &MLI = getAnalysis(); - MachineDominatorTree &MDT = getAnalysis(); // Instantiate the packetizer. - R600PacketizerList Packetizer(Fn, MLI, MDT); + R600PacketizerList Packetizer(Fn, MLI); // DFA state table should not be empty. assert(Packetizer.getResourceTracker() && "Empty DFA table!");