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https://github.com/RPCS3/llvm-mirror.git
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[X86] Updated test checks script to generalise LCPI symbol refs
The script now replace '.LCPI888_8' style asm symbols with the {{\.LCPI.*}} re pattern - this helps stop hardcoded symbols in 32-bit x86 tests changing with every edit of the file
Refreshed some tests to demonstrate the new check
llvm-svn: 272488
This commit is contained in:
Simon Pilgrim
parent
2b98b76820
commit
08b5ad90a3
@ -215,7 +215,7 @@ define <4 x i32> @var_rotate_v4i32(<4 x i32> %a, <4 x i32> %b) nounwind {
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; X32-SSE-NEXT: movdqa {{.*#+}} xmm2 = [32,32,32,32]
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; X32-SSE-NEXT: psubd %xmm1, %xmm2
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; X32-SSE-NEXT: pslld $23, %xmm1
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; X32-SSE-NEXT: paddd .LCPI1_1, %xmm1
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; X32-SSE-NEXT: paddd {{\.LCPI.*}}, %xmm1
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; X32-SSE-NEXT: cvttps2dq %xmm1, %xmm1
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; X32-SSE-NEXT: pshufd {{.*#+}} xmm3 = xmm1[1,1,3,3]
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; X32-SSE-NEXT: pmuludq %xmm0, %xmm1
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@ -667,7 +667,7 @@ define <16 x i8> @var_rotate_v16i8(<16 x i8> %a, <16 x i8> %b) nounwind {
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; X32-SSE-NEXT: pcmpgtb %xmm1, %xmm2
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; X32-SSE-NEXT: movdqa %xmm0, %xmm5
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; X32-SSE-NEXT: psllw $4, %xmm5
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; X32-SSE-NEXT: pand .LCPI3_1, %xmm5
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; X32-SSE-NEXT: pand {{\.LCPI.*}}, %xmm5
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; X32-SSE-NEXT: pand %xmm2, %xmm5
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; X32-SSE-NEXT: pandn %xmm0, %xmm2
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; X32-SSE-NEXT: por %xmm5, %xmm2
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@ -677,7 +677,7 @@ define <16 x i8> @var_rotate_v16i8(<16 x i8> %a, <16 x i8> %b) nounwind {
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; X32-SSE-NEXT: movdqa %xmm5, %xmm6
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; X32-SSE-NEXT: pandn %xmm2, %xmm6
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; X32-SSE-NEXT: psllw $2, %xmm2
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; X32-SSE-NEXT: pand .LCPI3_2, %xmm2
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; X32-SSE-NEXT: pand {{\.LCPI.*}}, %xmm2
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; X32-SSE-NEXT: pand %xmm5, %xmm2
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; X32-SSE-NEXT: por %xmm6, %xmm2
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; X32-SSE-NEXT: paddb %xmm1, %xmm1
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@ -693,7 +693,7 @@ define <16 x i8> @var_rotate_v16i8(<16 x i8> %a, <16 x i8> %b) nounwind {
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; X32-SSE-NEXT: movdqa %xmm5, %xmm6
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; X32-SSE-NEXT: pandn %xmm0, %xmm6
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; X32-SSE-NEXT: psrlw $4, %xmm0
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; X32-SSE-NEXT: pand .LCPI3_3, %xmm0
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; X32-SSE-NEXT: pand {{\.LCPI.*}}, %xmm0
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; X32-SSE-NEXT: pand %xmm5, %xmm0
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; X32-SSE-NEXT: por %xmm6, %xmm0
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; X32-SSE-NEXT: paddb %xmm4, %xmm4
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@ -702,7 +702,7 @@ define <16 x i8> @var_rotate_v16i8(<16 x i8> %a, <16 x i8> %b) nounwind {
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; X32-SSE-NEXT: movdqa %xmm5, %xmm6
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; X32-SSE-NEXT: pandn %xmm0, %xmm6
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; X32-SSE-NEXT: psrlw $2, %xmm0
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; X32-SSE-NEXT: pand .LCPI3_4, %xmm0
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; X32-SSE-NEXT: pand {{\.LCPI.*}}, %xmm0
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; X32-SSE-NEXT: pand %xmm5, %xmm0
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; X32-SSE-NEXT: por %xmm6, %xmm0
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; X32-SSE-NEXT: paddb %xmm4, %xmm4
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@ -710,7 +710,7 @@ define <16 x i8> @var_rotate_v16i8(<16 x i8> %a, <16 x i8> %b) nounwind {
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; X32-SSE-NEXT: movdqa %xmm3, %xmm4
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; X32-SSE-NEXT: pandn %xmm0, %xmm4
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; X32-SSE-NEXT: psrlw $1, %xmm0
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; X32-SSE-NEXT: pand .LCPI3_5, %xmm0
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; X32-SSE-NEXT: pand {{\.LCPI.*}}, %xmm0
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; X32-SSE-NEXT: pand %xmm3, %xmm0
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; X32-SSE-NEXT: por %xmm4, %xmm0
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; X32-SSE-NEXT: por %xmm1, %xmm0
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@ -1191,7 +1191,7 @@ define <16 x i8> @constant_rotate_v16i8(<16 x i8> %a) nounwind {
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; X32-SSE-NEXT: pcmpgtb %xmm3, %xmm1
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; X32-SSE-NEXT: movdqa %xmm0, %xmm4
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; X32-SSE-NEXT: psllw $4, %xmm4
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; X32-SSE-NEXT: pand .LCPI7_1, %xmm4
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; X32-SSE-NEXT: pand {{\.LCPI.*}}, %xmm4
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; X32-SSE-NEXT: pand %xmm1, %xmm4
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; X32-SSE-NEXT: pandn %xmm0, %xmm1
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; X32-SSE-NEXT: por %xmm4, %xmm1
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@ -1201,7 +1201,7 @@ define <16 x i8> @constant_rotate_v16i8(<16 x i8> %a) nounwind {
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; X32-SSE-NEXT: movdqa %xmm4, %xmm5
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; X32-SSE-NEXT: pandn %xmm1, %xmm5
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; X32-SSE-NEXT: psllw $2, %xmm1
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; X32-SSE-NEXT: pand .LCPI7_2, %xmm1
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; X32-SSE-NEXT: pand {{\.LCPI.*}}, %xmm1
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; X32-SSE-NEXT: pand %xmm4, %xmm1
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; X32-SSE-NEXT: por %xmm5, %xmm1
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; X32-SSE-NEXT: paddb %xmm3, %xmm3
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@ -1218,7 +1218,7 @@ define <16 x i8> @constant_rotate_v16i8(<16 x i8> %a) nounwind {
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; X32-SSE-NEXT: movdqa %xmm5, %xmm6
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; X32-SSE-NEXT: pandn %xmm0, %xmm6
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; X32-SSE-NEXT: psrlw $4, %xmm0
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; X32-SSE-NEXT: pand .LCPI7_4, %xmm0
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; X32-SSE-NEXT: pand {{\.LCPI.*}}, %xmm0
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; X32-SSE-NEXT: pand %xmm5, %xmm0
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; X32-SSE-NEXT: por %xmm6, %xmm0
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; X32-SSE-NEXT: paddb %xmm4, %xmm4
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@ -1227,7 +1227,7 @@ define <16 x i8> @constant_rotate_v16i8(<16 x i8> %a) nounwind {
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; X32-SSE-NEXT: movdqa %xmm5, %xmm6
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; X32-SSE-NEXT: pandn %xmm0, %xmm6
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; X32-SSE-NEXT: psrlw $2, %xmm0
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; X32-SSE-NEXT: pand .LCPI7_5, %xmm0
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; X32-SSE-NEXT: pand {{\.LCPI.*}}, %xmm0
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; X32-SSE-NEXT: pand %xmm5, %xmm0
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; X32-SSE-NEXT: por %xmm6, %xmm0
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; X32-SSE-NEXT: paddb %xmm4, %xmm4
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@ -1235,7 +1235,7 @@ define <16 x i8> @constant_rotate_v16i8(<16 x i8> %a) nounwind {
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; X32-SSE-NEXT: movdqa %xmm2, %xmm4
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; X32-SSE-NEXT: pandn %xmm0, %xmm4
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; X32-SSE-NEXT: psrlw $1, %xmm0
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; X32-SSE-NEXT: pand .LCPI7_6, %xmm0
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; X32-SSE-NEXT: pand {{\.LCPI.*}}, %xmm0
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; X32-SSE-NEXT: pand %xmm2, %xmm0
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; X32-SSE-NEXT: por %xmm4, %xmm0
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; X32-SSE-NEXT: por %xmm3, %xmm0
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@ -1382,9 +1382,9 @@ define <16 x i8> @splatconstant_rotate_v16i8(<16 x i8> %a) nounwind {
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; X32-SSE: # BB#0:
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; X32-SSE-NEXT: movdqa %xmm0, %xmm1
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; X32-SSE-NEXT: psllw $4, %xmm1
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; X32-SSE-NEXT: pand .LCPI11_0, %xmm1
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; X32-SSE-NEXT: pand {{\.LCPI.*}}, %xmm1
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; X32-SSE-NEXT: psrlw $4, %xmm0
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; X32-SSE-NEXT: pand .LCPI11_1, %xmm0
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; X32-SSE-NEXT: pand {{\.LCPI.*}}, %xmm0
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; X32-SSE-NEXT: por %xmm1, %xmm0
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; X32-SSE-NEXT: retl
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%shl = shl <16 x i8> %a, <i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4>
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@ -1429,8 +1429,8 @@ define <2 x i64> @splatconstant_rotate_mask_v2i64(<2 x i64> %a) nounwind {
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; X32-SSE-NEXT: movdqa %xmm0, %xmm1
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; X32-SSE-NEXT: psllq $15, %xmm1
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; X32-SSE-NEXT: psrlq $49, %xmm0
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; X32-SSE-NEXT: pand .LCPI12_0, %xmm0
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; X32-SSE-NEXT: pand .LCPI12_1, %xmm1
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; X32-SSE-NEXT: pand {{\.LCPI.*}}, %xmm0
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; X32-SSE-NEXT: pand {{\.LCPI.*}}, %xmm1
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; X32-SSE-NEXT: por %xmm0, %xmm1
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; X32-SSE-NEXT: movdqa %xmm1, %xmm0
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; X32-SSE-NEXT: retl
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@ -1474,8 +1474,8 @@ define <4 x i32> @splatconstant_rotate_mask_v4i32(<4 x i32> %a) nounwind {
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; X32-SSE-NEXT: movdqa %xmm0, %xmm1
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; X32-SSE-NEXT: pslld $4, %xmm1
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; X32-SSE-NEXT: psrld $28, %xmm0
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; X32-SSE-NEXT: pand .LCPI13_0, %xmm0
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; X32-SSE-NEXT: pand .LCPI13_1, %xmm1
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; X32-SSE-NEXT: pand {{\.LCPI.*}}, %xmm0
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; X32-SSE-NEXT: pand {{\.LCPI.*}}, %xmm1
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; X32-SSE-NEXT: por %xmm0, %xmm1
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; X32-SSE-NEXT: movdqa %xmm1, %xmm0
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; X32-SSE-NEXT: retl
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@ -1519,8 +1519,8 @@ define <8 x i16> @splatconstant_rotate_mask_v8i16(<8 x i16> %a) nounwind {
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; X32-SSE-NEXT: movdqa %xmm0, %xmm1
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; X32-SSE-NEXT: psllw $5, %xmm1
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; X32-SSE-NEXT: psrlw $11, %xmm0
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; X32-SSE-NEXT: pand .LCPI14_0, %xmm0
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; X32-SSE-NEXT: pand .LCPI14_1, %xmm1
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; X32-SSE-NEXT: pand {{\.LCPI.*}}, %xmm0
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; X32-SSE-NEXT: pand {{\.LCPI.*}}, %xmm1
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; X32-SSE-NEXT: por %xmm0, %xmm1
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; X32-SSE-NEXT: movdqa %xmm1, %xmm0
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; X32-SSE-NEXT: retl
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@ -1567,11 +1567,11 @@ define <16 x i8> @splatconstant_rotate_mask_v16i8(<16 x i8> %a) nounwind {
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; X32-SSE: # BB#0:
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; X32-SSE-NEXT: movdqa %xmm0, %xmm1
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; X32-SSE-NEXT: psllw $4, %xmm1
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; X32-SSE-NEXT: pand .LCPI15_0, %xmm1
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; X32-SSE-NEXT: pand {{\.LCPI.*}}, %xmm1
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; X32-SSE-NEXT: psrlw $4, %xmm0
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; X32-SSE-NEXT: pand .LCPI15_1, %xmm0
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; X32-SSE-NEXT: pand .LCPI15_2, %xmm0
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; X32-SSE-NEXT: pand .LCPI15_3, %xmm1
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; X32-SSE-NEXT: pand {{\.LCPI.*}}, %xmm0
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; X32-SSE-NEXT: pand {{\.LCPI.*}}, %xmm0
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; X32-SSE-NEXT: pand {{\.LCPI.*}}, %xmm1
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; X32-SSE-NEXT: por %xmm0, %xmm1
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; X32-SSE-NEXT: movdqa %xmm1, %xmm0
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; X32-SSE-NEXT: retl
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@ -1083,7 +1083,7 @@ define <4 x i64> @load_sext_4i1_to_4i64(<4 x i1> *%ptr) {
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; X32-SSE41-NEXT: pinsrd $2, %ecx, %xmm1
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; X32-SSE41-NEXT: shrl $3, %eax
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; X32-SSE41-NEXT: pinsrd $3, %eax, %xmm1
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; X32-SSE41-NEXT: pand .LCPI17_0, %xmm1
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; X32-SSE41-NEXT: pand {{\.LCPI.*}}, %xmm1
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; X32-SSE41-NEXT: pmovzxdq {{.*#+}} xmm0 = xmm1[0],zero,xmm1[1],zero
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; X32-SSE41-NEXT: psllq $63, %xmm0
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; X32-SSE41-NEXT: psrad $31, %xmm0
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@ -1638,7 +1638,7 @@ define <16 x i8> @splatconstant_shift_v16i8(<16 x i8> %a) nounwind {
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; X32-SSE-LABEL: splatconstant_shift_v16i8:
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; X32-SSE: # BB#0:
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; X32-SSE-NEXT: psrlw $3, %xmm0
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; X32-SSE-NEXT: pand .LCPI15_0, %xmm0
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; X32-SSE-NEXT: pand {{\.LCPI.*}}, %xmm0
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; X32-SSE-NEXT: movdqa {{.*#+}} xmm1 = [16,16,16,16,16,16,16,16,16,16,16,16,16,16,16,16]
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; X32-SSE-NEXT: pxor %xmm1, %xmm0
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; X32-SSE-NEXT: psubb %xmm1, %xmm0
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@ -437,7 +437,7 @@ define <16 x i8> @var_shift_v16i8(<16 x i8> %a, <16 x i8> %b) nounwind {
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; X32-SSE-NEXT: movdqa %xmm3, %xmm4
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; X32-SSE-NEXT: pandn %xmm0, %xmm4
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; X32-SSE-NEXT: psrlw $4, %xmm0
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; X32-SSE-NEXT: pand .LCPI3_0, %xmm0
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; X32-SSE-NEXT: pand {{\.LCPI.*}}, %xmm0
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; X32-SSE-NEXT: pand %xmm3, %xmm0
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; X32-SSE-NEXT: por %xmm4, %xmm0
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; X32-SSE-NEXT: paddb %xmm1, %xmm1
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@ -446,7 +446,7 @@ define <16 x i8> @var_shift_v16i8(<16 x i8> %a, <16 x i8> %b) nounwind {
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; X32-SSE-NEXT: movdqa %xmm3, %xmm4
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; X32-SSE-NEXT: pandn %xmm0, %xmm4
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; X32-SSE-NEXT: psrlw $2, %xmm0
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; X32-SSE-NEXT: pand .LCPI3_1, %xmm0
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; X32-SSE-NEXT: pand {{\.LCPI.*}}, %xmm0
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; X32-SSE-NEXT: pand %xmm3, %xmm0
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; X32-SSE-NEXT: por %xmm4, %xmm0
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; X32-SSE-NEXT: paddb %xmm1, %xmm1
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@ -454,7 +454,7 @@ define <16 x i8> @var_shift_v16i8(<16 x i8> %a, <16 x i8> %b) nounwind {
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; X32-SSE-NEXT: movdqa %xmm2, %xmm1
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; X32-SSE-NEXT: pandn %xmm0, %xmm1
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; X32-SSE-NEXT: psrlw $1, %xmm0
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; X32-SSE-NEXT: pand .LCPI3_2, %xmm0
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; X32-SSE-NEXT: pand {{\.LCPI.*}}, %xmm0
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; X32-SSE-NEXT: pand %xmm2, %xmm0
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; X32-SSE-NEXT: por %xmm1, %xmm0
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; X32-SSE-NEXT: retl
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@ -735,7 +735,7 @@ define <16 x i8> @splatvar_shift_v16i8(<16 x i8> %a, <16 x i8> %b) nounwind {
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; X32-SSE-NEXT: movdqa %xmm3, %xmm4
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; X32-SSE-NEXT: pandn %xmm0, %xmm4
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; X32-SSE-NEXT: psrlw $4, %xmm0
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; X32-SSE-NEXT: pand .LCPI7_0, %xmm0
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; X32-SSE-NEXT: pand {{\.LCPI.*}}, %xmm0
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; X32-SSE-NEXT: pand %xmm3, %xmm0
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; X32-SSE-NEXT: por %xmm4, %xmm0
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; X32-SSE-NEXT: paddb %xmm2, %xmm2
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@ -744,7 +744,7 @@ define <16 x i8> @splatvar_shift_v16i8(<16 x i8> %a, <16 x i8> %b) nounwind {
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; X32-SSE-NEXT: movdqa %xmm3, %xmm4
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; X32-SSE-NEXT: pandn %xmm0, %xmm4
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; X32-SSE-NEXT: psrlw $2, %xmm0
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; X32-SSE-NEXT: pand .LCPI7_1, %xmm0
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; X32-SSE-NEXT: pand {{\.LCPI.*}}, %xmm0
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; X32-SSE-NEXT: pand %xmm3, %xmm0
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; X32-SSE-NEXT: por %xmm4, %xmm0
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; X32-SSE-NEXT: paddb %xmm2, %xmm2
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@ -752,7 +752,7 @@ define <16 x i8> @splatvar_shift_v16i8(<16 x i8> %a, <16 x i8> %b) nounwind {
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; X32-SSE-NEXT: movdqa %xmm1, %xmm2
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; X32-SSE-NEXT: pandn %xmm0, %xmm2
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; X32-SSE-NEXT: psrlw $1, %xmm0
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; X32-SSE-NEXT: pand .LCPI7_2, %xmm0
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; X32-SSE-NEXT: pand {{\.LCPI.*}}, %xmm0
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; X32-SSE-NEXT: pand %xmm1, %xmm0
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; X32-SSE-NEXT: por %xmm2, %xmm0
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; X32-SSE-NEXT: retl
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@ -1094,7 +1094,7 @@ define <16 x i8> @constant_shift_v16i8(<16 x i8> %a) nounwind {
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; X32-SSE-NEXT: movdqa %xmm3, %xmm4
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; X32-SSE-NEXT: pandn %xmm0, %xmm4
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; X32-SSE-NEXT: psrlw $4, %xmm0
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; X32-SSE-NEXT: pand .LCPI11_1, %xmm0
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; X32-SSE-NEXT: pand {{\.LCPI.*}}, %xmm0
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; X32-SSE-NEXT: pand %xmm3, %xmm0
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; X32-SSE-NEXT: por %xmm4, %xmm0
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; X32-SSE-NEXT: paddb %xmm2, %xmm2
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@ -1103,7 +1103,7 @@ define <16 x i8> @constant_shift_v16i8(<16 x i8> %a) nounwind {
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; X32-SSE-NEXT: movdqa %xmm3, %xmm4
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; X32-SSE-NEXT: pandn %xmm0, %xmm4
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; X32-SSE-NEXT: psrlw $2, %xmm0
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; X32-SSE-NEXT: pand .LCPI11_2, %xmm0
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; X32-SSE-NEXT: pand {{\.LCPI.*}}, %xmm0
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; X32-SSE-NEXT: pand %xmm3, %xmm0
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; X32-SSE-NEXT: por %xmm4, %xmm0
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; X32-SSE-NEXT: paddb %xmm2, %xmm2
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@ -1111,7 +1111,7 @@ define <16 x i8> @constant_shift_v16i8(<16 x i8> %a) nounwind {
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; X32-SSE-NEXT: movdqa %xmm1, %xmm2
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; X32-SSE-NEXT: pandn %xmm0, %xmm2
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; X32-SSE-NEXT: psrlw $1, %xmm0
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; X32-SSE-NEXT: pand .LCPI11_3, %xmm0
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; X32-SSE-NEXT: pand {{\.LCPI.*}}, %xmm0
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; X32-SSE-NEXT: pand %xmm1, %xmm0
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; X32-SSE-NEXT: por %xmm2, %xmm0
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; X32-SSE-NEXT: retl
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@ -1239,7 +1239,7 @@ define <16 x i8> @splatconstant_shift_v16i8(<16 x i8> %a) nounwind {
|
||||
; X32-SSE-LABEL: splatconstant_shift_v16i8:
|
||||
; X32-SSE: # BB#0:
|
||||
; X32-SSE-NEXT: psrlw $3, %xmm0
|
||||
; X32-SSE-NEXT: pand .LCPI15_0, %xmm0
|
||||
; X32-SSE-NEXT: pand {{\.LCPI.*}}, %xmm0
|
||||
; X32-SSE-NEXT: retl
|
||||
%shift = lshr <16 x i8> %a, <i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3>
|
||||
ret <16 x i8> %shift
|
||||
|
||||
@ -131,7 +131,7 @@ define <4 x i32> @var_shift_v4i32(<4 x i32> %a, <4 x i32> %b) nounwind {
|
||||
; X32-SSE-LABEL: var_shift_v4i32:
|
||||
; X32-SSE: # BB#0:
|
||||
; X32-SSE-NEXT: pslld $23, %xmm1
|
||||
; X32-SSE-NEXT: paddd .LCPI1_0, %xmm1
|
||||
; X32-SSE-NEXT: paddd {{\.LCPI.*}}, %xmm1
|
||||
; X32-SSE-NEXT: cvttps2dq %xmm1, %xmm1
|
||||
; X32-SSE-NEXT: pshufd {{.*#+}} xmm2 = xmm1[1,1,3,3]
|
||||
; X32-SSE-NEXT: pmuludq %xmm0, %xmm1
|
||||
@ -386,7 +386,7 @@ define <16 x i8> @var_shift_v16i8(<16 x i8> %a, <16 x i8> %b) nounwind {
|
||||
; X32-SSE-NEXT: movdqa %xmm3, %xmm4
|
||||
; X32-SSE-NEXT: pandn %xmm0, %xmm4
|
||||
; X32-SSE-NEXT: psllw $4, %xmm0
|
||||
; X32-SSE-NEXT: pand .LCPI3_0, %xmm0
|
||||
; X32-SSE-NEXT: pand {{\.LCPI.*}}, %xmm0
|
||||
; X32-SSE-NEXT: pand %xmm3, %xmm0
|
||||
; X32-SSE-NEXT: por %xmm4, %xmm0
|
||||
; X32-SSE-NEXT: paddb %xmm1, %xmm1
|
||||
@ -395,7 +395,7 @@ define <16 x i8> @var_shift_v16i8(<16 x i8> %a, <16 x i8> %b) nounwind {
|
||||
; X32-SSE-NEXT: movdqa %xmm3, %xmm4
|
||||
; X32-SSE-NEXT: pandn %xmm0, %xmm4
|
||||
; X32-SSE-NEXT: psllw $2, %xmm0
|
||||
; X32-SSE-NEXT: pand .LCPI3_1, %xmm0
|
||||
; X32-SSE-NEXT: pand {{\.LCPI.*}}, %xmm0
|
||||
; X32-SSE-NEXT: pand %xmm3, %xmm0
|
||||
; X32-SSE-NEXT: por %xmm4, %xmm0
|
||||
; X32-SSE-NEXT: paddb %xmm1, %xmm1
|
||||
@ -675,7 +675,7 @@ define <16 x i8> @splatvar_shift_v16i8(<16 x i8> %a, <16 x i8> %b) nounwind {
|
||||
; X32-SSE-NEXT: movdqa %xmm3, %xmm4
|
||||
; X32-SSE-NEXT: pandn %xmm0, %xmm4
|
||||
; X32-SSE-NEXT: psllw $4, %xmm0
|
||||
; X32-SSE-NEXT: pand .LCPI7_0, %xmm0
|
||||
; X32-SSE-NEXT: pand {{\.LCPI.*}}, %xmm0
|
||||
; X32-SSE-NEXT: pand %xmm3, %xmm0
|
||||
; X32-SSE-NEXT: por %xmm4, %xmm0
|
||||
; X32-SSE-NEXT: paddb %xmm2, %xmm2
|
||||
@ -684,7 +684,7 @@ define <16 x i8> @splatvar_shift_v16i8(<16 x i8> %a, <16 x i8> %b) nounwind {
|
||||
; X32-SSE-NEXT: movdqa %xmm3, %xmm4
|
||||
; X32-SSE-NEXT: pandn %xmm0, %xmm4
|
||||
; X32-SSE-NEXT: psllw $2, %xmm0
|
||||
; X32-SSE-NEXT: pand .LCPI7_1, %xmm0
|
||||
; X32-SSE-NEXT: pand {{\.LCPI.*}}, %xmm0
|
||||
; X32-SSE-NEXT: pand %xmm3, %xmm0
|
||||
; X32-SSE-NEXT: por %xmm4, %xmm0
|
||||
; X32-SSE-NEXT: paddb %xmm2, %xmm2
|
||||
@ -843,7 +843,7 @@ define <8 x i16> @constant_shift_v8i16(<8 x i16> %a) nounwind {
|
||||
;
|
||||
; X32-SSE-LABEL: constant_shift_v8i16:
|
||||
; X32-SSE: # BB#0:
|
||||
; X32-SSE-NEXT: pmullw .LCPI10_0, %xmm0
|
||||
; X32-SSE-NEXT: pmullw {{\.LCPI.*}}, %xmm0
|
||||
; X32-SSE-NEXT: retl
|
||||
%shift = shl <8 x i16> %a, <i16 0, i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7>
|
||||
ret <8 x i16> %shift
|
||||
@ -949,7 +949,7 @@ define <16 x i8> @constant_shift_v16i8(<16 x i8> %a) nounwind {
|
||||
; X32-SSE-NEXT: movdqa %xmm3, %xmm4
|
||||
; X32-SSE-NEXT: pandn %xmm0, %xmm4
|
||||
; X32-SSE-NEXT: psllw $4, %xmm0
|
||||
; X32-SSE-NEXT: pand .LCPI11_1, %xmm0
|
||||
; X32-SSE-NEXT: pand {{\.LCPI.*}}, %xmm0
|
||||
; X32-SSE-NEXT: pand %xmm3, %xmm0
|
||||
; X32-SSE-NEXT: por %xmm4, %xmm0
|
||||
; X32-SSE-NEXT: paddb %xmm2, %xmm2
|
||||
@ -958,7 +958,7 @@ define <16 x i8> @constant_shift_v16i8(<16 x i8> %a) nounwind {
|
||||
; X32-SSE-NEXT: movdqa %xmm3, %xmm4
|
||||
; X32-SSE-NEXT: pandn %xmm0, %xmm4
|
||||
; X32-SSE-NEXT: psllw $2, %xmm0
|
||||
; X32-SSE-NEXT: pand .LCPI11_2, %xmm0
|
||||
; X32-SSE-NEXT: pand {{\.LCPI.*}}, %xmm0
|
||||
; X32-SSE-NEXT: pand %xmm3, %xmm0
|
||||
; X32-SSE-NEXT: por %xmm4, %xmm0
|
||||
; X32-SSE-NEXT: paddb %xmm2, %xmm2
|
||||
@ -1091,7 +1091,7 @@ define <16 x i8> @splatconstant_shift_v16i8(<16 x i8> %a) nounwind {
|
||||
; X32-SSE-LABEL: splatconstant_shift_v16i8:
|
||||
; X32-SSE: # BB#0:
|
||||
; X32-SSE-NEXT: psllw $3, %xmm0
|
||||
; X32-SSE-NEXT: pand .LCPI15_0, %xmm0
|
||||
; X32-SSE-NEXT: pand {{\.LCPI.*}}, %xmm0
|
||||
; X32-SSE-NEXT: retl
|
||||
%shift = shl <16 x i8> %a, <i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3>
|
||||
ret <16 x i8> %shift
|
||||
|
||||
@ -1,4 +1,4 @@
|
||||
; NOTE: Assertions have been autogenerated by update_llc_test_checks.py
|
||||
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
|
||||
; RUN: llc < %s -mcpu=x86-64 -mattr=+avx512f | FileCheck %s --check-prefix=ALL --check-prefix=AVX512F
|
||||
; RUN: llc < %s -mtriple=i386-unknown-linux-gnu -mattr=+avx512f | FileCheck %s --check-prefix=ALL --check-prefix=AVX512F-32
|
||||
|
||||
@ -2160,7 +2160,7 @@ define <8 x double> @test_vshuff64x2_512_maskz(<8 x double> %x, <8 x double> %x1
|
||||
; AVX512F-32-LABEL: test_vshuff64x2_512_maskz:
|
||||
; AVX512F-32: # BB#0:
|
||||
; AVX512F-32-NEXT: vpmovsxwq %xmm2, %zmm2
|
||||
; AVX512F-32-NEXT: vpsllvq .LCPI126_0, %zmm2, %zmm2
|
||||
; AVX512F-32-NEXT: vpsllvq {{\.LCPI.*}}, %zmm2, %zmm2
|
||||
; AVX512F-32-NEXT: vptestmq %zmm2, %zmm2, %k1
|
||||
; AVX512F-32-NEXT: vshuff64x2 {{.*#+}} zmm0 = zmm0[0,1,4,5],zmm1[2,3,0,1]
|
||||
; AVX512F-32-NEXT: retl
|
||||
@ -2181,7 +2181,7 @@ define <8 x i64> @test_vshufi64x2_512_mask(<8 x i64> %x, <8 x i64> %x1, <8 x i1>
|
||||
; AVX512F-32-LABEL: test_vshufi64x2_512_mask:
|
||||
; AVX512F-32: # BB#0:
|
||||
; AVX512F-32-NEXT: vpmovsxwq %xmm2, %zmm2
|
||||
; AVX512F-32-NEXT: vpsllvq .LCPI127_0, %zmm2, %zmm2
|
||||
; AVX512F-32-NEXT: vpsllvq {{\.LCPI.*}}, %zmm2, %zmm2
|
||||
; AVX512F-32-NEXT: vptestmq %zmm2, %zmm2, %k1
|
||||
; AVX512F-32-NEXT: vshufi64x2 {{.*#+}} zmm0 = zmm0[0,1,4,5],zmm1[2,3,0,1]
|
||||
; AVX512F-32-NEXT: retl
|
||||
@ -2218,7 +2218,7 @@ define <8 x double> @test_vshuff64x2_512_mem_mask(<8 x double> %x, <8 x double>
|
||||
; AVX512F-32-LABEL: test_vshuff64x2_512_mem_mask:
|
||||
; AVX512F-32: # BB#0:
|
||||
; AVX512F-32-NEXT: vpmovsxwq %xmm1, %zmm1
|
||||
; AVX512F-32-NEXT: vpsllvq .LCPI129_0, %zmm1, %zmm1
|
||||
; AVX512F-32-NEXT: vpsllvq {{\.LCPI.*}}, %zmm1, %zmm1
|
||||
; AVX512F-32-NEXT: vptestmq %zmm1, %zmm1, %k1
|
||||
; AVX512F-32-NEXT: movl {{[0-9]+}}(%esp), %eax
|
||||
; AVX512F-32-NEXT: vshuff64x2 {{.*#+}} zmm0 = zmm0[0,1,4,5],mem[2,3,0,1]
|
||||
@ -2241,7 +2241,7 @@ define <8 x double> @test_vshuff64x2_512_mem_maskz(<8 x double> %x, <8 x double>
|
||||
; AVX512F-32-LABEL: test_vshuff64x2_512_mem_maskz:
|
||||
; AVX512F-32: # BB#0:
|
||||
; AVX512F-32-NEXT: vpmovsxwq %xmm1, %zmm1
|
||||
; AVX512F-32-NEXT: vpsllvq .LCPI130_0, %zmm1, %zmm1
|
||||
; AVX512F-32-NEXT: vpsllvq {{\.LCPI.*}}, %zmm1, %zmm1
|
||||
; AVX512F-32-NEXT: vptestmq %zmm1, %zmm1, %k1
|
||||
; AVX512F-32-NEXT: movl {{[0-9]+}}(%esp), %eax
|
||||
; AVX512F-32-NEXT: vshuff64x2 {{.*#+}} zmm0 = zmm0[0,1,4,5],mem[2,3,0,1]
|
||||
|
||||
@ -1,4 +1,4 @@
|
||||
; NOTE: Assertions have been autogenerated by update_llc_test_checks.py
|
||||
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
|
||||
; RUN: llc < %s -mtriple=x86_64-unknown-unknown | FileCheck %s --check-prefix=ALL --check-prefix=SSE --check-prefix=SSE2
|
||||
; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+sse3 | FileCheck %s --check-prefix=ALL --check-prefix=SSE --check-prefix=SSE3
|
||||
; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+ssse3 | FileCheck %s --check-prefix=ALL --check-prefix=SSE --check-prefix=SSSE3
|
||||
@ -435,7 +435,7 @@ define <4 x i32> @testv4i32(<4 x i32> %in) nounwind {
|
||||
; X32-SSE-NEXT: pxor %xmm2, %xmm2
|
||||
; X32-SSE-NEXT: psubd %xmm0, %xmm2
|
||||
; X32-SSE-NEXT: pand %xmm0, %xmm2
|
||||
; X32-SSE-NEXT: psubd .LCPI2_0, %xmm2
|
||||
; X32-SSE-NEXT: psubd {{\.LCPI.*}}, %xmm2
|
||||
; X32-SSE-NEXT: movdqa {{.*#+}} xmm3 = [15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15]
|
||||
; X32-SSE-NEXT: movdqa %xmm2, %xmm4
|
||||
; X32-SSE-NEXT: pand %xmm3, %xmm4
|
||||
@ -635,7 +635,7 @@ define <4 x i32> @testv4i32u(<4 x i32> %in) nounwind {
|
||||
; X32-SSE-NEXT: pxor %xmm2, %xmm2
|
||||
; X32-SSE-NEXT: psubd %xmm0, %xmm2
|
||||
; X32-SSE-NEXT: pand %xmm0, %xmm2
|
||||
; X32-SSE-NEXT: psubd .LCPI3_0, %xmm2
|
||||
; X32-SSE-NEXT: psubd {{\.LCPI.*}}, %xmm2
|
||||
; X32-SSE-NEXT: movdqa {{.*#+}} xmm3 = [15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15]
|
||||
; X32-SSE-NEXT: movdqa %xmm2, %xmm4
|
||||
; X32-SSE-NEXT: pand %xmm3, %xmm4
|
||||
@ -835,7 +835,7 @@ define <8 x i16> @testv8i16(<8 x i16> %in) nounwind {
|
||||
; X32-SSE-NEXT: pxor %xmm1, %xmm1
|
||||
; X32-SSE-NEXT: psubw %xmm0, %xmm1
|
||||
; X32-SSE-NEXT: pand %xmm0, %xmm1
|
||||
; X32-SSE-NEXT: psubw .LCPI4_0, %xmm1
|
||||
; X32-SSE-NEXT: psubw {{\.LCPI.*}}, %xmm1
|
||||
; X32-SSE-NEXT: movdqa {{.*#+}} xmm0 = [15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15]
|
||||
; X32-SSE-NEXT: movdqa %xmm1, %xmm2
|
||||
; X32-SSE-NEXT: pand %xmm0, %xmm2
|
||||
@ -1033,7 +1033,7 @@ define <8 x i16> @testv8i16u(<8 x i16> %in) nounwind {
|
||||
; X32-SSE-NEXT: pxor %xmm1, %xmm1
|
||||
; X32-SSE-NEXT: psubw %xmm0, %xmm1
|
||||
; X32-SSE-NEXT: pand %xmm0, %xmm1
|
||||
; X32-SSE-NEXT: psubw .LCPI5_0, %xmm1
|
||||
; X32-SSE-NEXT: psubw {{\.LCPI.*}}, %xmm1
|
||||
; X32-SSE-NEXT: movdqa {{.*#+}} xmm0 = [15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15]
|
||||
; X32-SSE-NEXT: movdqa %xmm1, %xmm2
|
||||
; X32-SSE-NEXT: pand %xmm0, %xmm2
|
||||
@ -1203,7 +1203,7 @@ define <16 x i8> @testv16i8(<16 x i8> %in) nounwind {
|
||||
; X32-SSE-NEXT: pxor %xmm1, %xmm1
|
||||
; X32-SSE-NEXT: psubb %xmm0, %xmm1
|
||||
; X32-SSE-NEXT: pand %xmm0, %xmm1
|
||||
; X32-SSE-NEXT: psubb .LCPI6_0, %xmm1
|
||||
; X32-SSE-NEXT: psubb {{\.LCPI.*}}, %xmm1
|
||||
; X32-SSE-NEXT: movdqa {{.*#+}} xmm2 = [15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15]
|
||||
; X32-SSE-NEXT: movdqa %xmm1, %xmm3
|
||||
; X32-SSE-NEXT: pand %xmm2, %xmm3
|
||||
@ -1369,7 +1369,7 @@ define <16 x i8> @testv16i8u(<16 x i8> %in) nounwind {
|
||||
; X32-SSE-NEXT: pxor %xmm1, %xmm1
|
||||
; X32-SSE-NEXT: psubb %xmm0, %xmm1
|
||||
; X32-SSE-NEXT: pand %xmm0, %xmm1
|
||||
; X32-SSE-NEXT: psubb .LCPI7_0, %xmm1
|
||||
; X32-SSE-NEXT: psubb {{\.LCPI.*}}, %xmm1
|
||||
; X32-SSE-NEXT: movdqa {{.*#+}} xmm2 = [15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15]
|
||||
; X32-SSE-NEXT: movdqa %xmm1, %xmm3
|
||||
; X32-SSE-NEXT: pand %xmm2, %xmm3
|
||||
|
||||
@ -80,7 +80,7 @@ define <16 x i8> @vpperm_shuffle_binary_zero(<16 x i8> %a0, <16 x i8> %a1) {
|
||||
define <16 x i8> @vpperm_shuffle_general(<16 x i8> %a0, <16 x i8> %a1) {
|
||||
; X32-LABEL: vpperm_shuffle_general:
|
||||
; X32: # BB#0:
|
||||
; X32-NEXT: vpperm .LCPI5_0, %xmm0, %xmm0, %xmm0
|
||||
; X32-NEXT: vpperm {{\.LCPI.*}}, %xmm0, %xmm0, %xmm0
|
||||
; X32-NEXT: retl
|
||||
;
|
||||
; X64-LABEL: vpperm_shuffle_general:
|
||||
|
||||
@ -36,6 +36,7 @@ SCRUB_X86_SHUFFLES_RE = (
|
||||
flags=re.M))
|
||||
SCRUB_X86_SP_RE = re.compile(r'\d+\(%(esp|rsp)\)')
|
||||
SCRUB_X86_RIP_RE = re.compile(r'[.\w]+\(%rip\)')
|
||||
SCRUB_X86_LCP_RE = re.compile(r'\.LCPI[0-9]+_[0-9]+')
|
||||
SCRUB_KILL_COMMENT_RE = re.compile(r'^ *#+ +kill:.*\n')
|
||||
|
||||
RUN_LINE_RE = re.compile('^\s*;\s*RUN:\s*(.*)$')
|
||||
@ -61,6 +62,8 @@ def scrub_asm(asm):
|
||||
asm = SCRUB_X86_SP_RE.sub(r'{{[0-9]+}}(%\1)', asm)
|
||||
# Generically match a RIP-relative memory operand.
|
||||
asm = SCRUB_X86_RIP_RE.sub(r'{{.*}}(%rip)', asm)
|
||||
# Generically match a LCP symbol.
|
||||
asm = SCRUB_X86_LCP_RE.sub(r'{{\.LCPI.*}}', asm)
|
||||
# Strip kill operands inserted into the asm.
|
||||
asm = SCRUB_KILL_COMMENT_RE.sub('', asm)
|
||||
# Strip trailing whitespace.
|
||||
@ -144,7 +147,7 @@ def main():
|
||||
args = parser.parse_args()
|
||||
|
||||
autogenerated_note = ('; NOTE: Assertions have been autogenerated by '
|
||||
+ os.path.basename(__file__))
|
||||
'utils/' + os.path.basename(__file__))
|
||||
|
||||
for test in args.tests:
|
||||
if args.verbose:
|
||||
|
||||
@ -51,6 +51,7 @@ SCRUB_X86_SHUFFLES_RE = (
|
||||
flags=re.M))
|
||||
SCRUB_X86_SP_RE = re.compile(r'\d+\(%(esp|rsp)\)')
|
||||
SCRUB_X86_RIP_RE = re.compile(r'[.\w]+\(%rip\)')
|
||||
SCRUB_X86_LCP_RE = re.compile(r'\.LCPI[0-9]+_[0-9]+')
|
||||
SCRUB_KILL_COMMENT_RE = re.compile(r'^ *#+ +kill:.*\n')
|
||||
SCRUB_IR_COMMENT_RE = re.compile(r'\s*;.*')
|
||||
|
||||
@ -88,6 +89,8 @@ def scrub_asm(asm):
|
||||
asm = SCRUB_X86_SP_RE.sub(r'{{[0-9]+}}(%\1)', asm)
|
||||
# Generically match a RIP-relative memory operand.
|
||||
asm = SCRUB_X86_RIP_RE.sub(r'{{.*}}(%rip)', asm)
|
||||
# Generically match a LCP symbol.
|
||||
asm = SCRUB_X86_LCP_RE.sub(r'{{\.LCPI.*}}', asm)
|
||||
# Strip kill operands inserted into the asm.
|
||||
asm = SCRUB_KILL_COMMENT_RE.sub('', asm)
|
||||
return asm
|
||||
|
||||
Loading…
Reference in New Issue
Block a user