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[ARM] Constant long shift combines
This changes the way that asrl and lsrl intrinsics are lowered, going via a the ISEL ASRL and LSLL nodes instead of straight to machine nodes. On top of that, it adds some constant folds for long shifts, in case it turns out that the shift amount was either constant or 0. Differential Revision: https://reviews.llvm.org/D75553
This commit is contained in:
David Green
parent
8574f053c4
commit
08ce568726
@ -4681,12 +4681,6 @@ void ARMDAGToDAGISel::Select(SDNode *N) {
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case Intrinsic::arm_mve_sqrshrl:
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SelectMVE_LongShift(N, ARM::MVE_SQRSHRL, false, true);
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return;
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case Intrinsic::arm_mve_lsll:
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SelectMVE_LongShift(N, ARM::MVE_LSLLr, false, false);
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return;
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case Intrinsic::arm_mve_asrl:
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SelectMVE_LongShift(N, ARM::MVE_ASRLr, false, false);
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return;
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case Intrinsic::arm_mve_vadc:
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case Intrinsic::arm_mve_vadc_predicated:
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@ -3808,6 +3808,12 @@ ARMTargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG,
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case Intrinsic::arm_mve_vreinterpretq:
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return DAG.getNode(ARMISD::VECTOR_REG_CAST, SDLoc(Op), Op.getValueType(),
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Op.getOperand(1));
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case Intrinsic::arm_mve_lsll:
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return DAG.getNode(ARMISD::LSLL, SDLoc(Op), Op->getVTList(),
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Op.getOperand(1), Op.getOperand(2), Op.getOperand(3));
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case Intrinsic::arm_mve_asrl:
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return DAG.getNode(ARMISD::ASRL, SDLoc(Op), Op->getVTList(),
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Op.getOperand(1), Op.getOperand(2), Op.getOperand(3));
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}
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}
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@ -14138,6 +14144,34 @@ static SDValue PerformVECREDUCE_ADDCombine(SDNode *N, SelectionDAG &DAG,
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return SDValue();
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}
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static SDValue PerformLongShiftCombine(SDNode *N, SelectionDAG &DAG) {
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SDLoc DL(N);
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SDValue Op0 = N->getOperand(0);
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SDValue Op1 = N->getOperand(1);
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// Turn X << -C -> X >> C and viceversa. The negative shifts can come up from
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// uses of the intrinsics.
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if (auto C = dyn_cast<ConstantSDNode>(N->getOperand(2))) {
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int ShiftAmt = C->getSExtValue();
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if (ShiftAmt == 0) {
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SDValue Merge = DAG.getMergeValues({Op0, Op1}, DL);
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DAG.ReplaceAllUsesWith(N, Merge.getNode());
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return SDValue();
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}
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if (ShiftAmt >= -32 && ShiftAmt < 0) {
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unsigned NewOpcode =
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N->getOpcode() == ARMISD::LSLL ? ARMISD::LSRL : ARMISD::LSLL;
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SDValue NewShift = DAG.getNode(NewOpcode, DL, N->getVTList(), Op0, Op1,
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DAG.getConstant(-ShiftAmt, DL, MVT::i32));
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DAG.ReplaceAllUsesWith(N, NewShift.getNode());
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return NewShift;
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}
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}
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return SDValue();
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}
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/// PerformIntrinsicCombine - ARM-specific DAG combining for intrinsics.
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static SDValue PerformIntrinsicCombine(SDNode *N, SelectionDAG &DAG) {
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unsigned IntNo = cast<ConstantSDNode>(N->getOperand(0))->getZExtValue();
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@ -15033,6 +15067,10 @@ SDValue ARMTargetLowering::PerformDAGCombine(SDNode *N,
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return PerformVCMPCombine(N, DCI, Subtarget);
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case ISD::VECREDUCE_ADD:
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return PerformVECREDUCE_ADDCombine(N, DCI.DAG, Subtarget);
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case ARMISD::ASRL:
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case ARMISD::LSRL:
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case ARMISD::LSLL:
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return PerformLongShiftCombine(N, DCI.DAG);
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case ARMISD::SMULWB: {
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unsigned BitWidth = N->getValueType(0).getSizeInBits();
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APInt DemandedMask = APInt::getLowBitsSet(BitWidth, 16);
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@ -7,8 +7,6 @@ declare {i32, i32} @llvm.arm.mve.lsll(i32, i32, i32)
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define i64 @asrl_0(i64 %X) {
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; CHECK-LABEL: asrl_0:
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; CHECK: @ %bb.0: @ %entry
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; CHECK-NEXT: movs r2, #0
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; CHECK-NEXT: asrl r0, r1, r2
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; CHECK-NEXT: bx lr
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entry:
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%0 = lshr i64 %X, 32
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@ -27,8 +25,7 @@ entry:
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define i64 @asrl_23(i64 %X) {
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; CHECK-LABEL: asrl_23:
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; CHECK: @ %bb.0: @ %entry
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; CHECK-NEXT: movs r2, #23
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; CHECK-NEXT: asrl r0, r1, r2
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; CHECK-NEXT: asrl r0, r1, #23
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; CHECK-NEXT: bx lr
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entry:
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%0 = lshr i64 %X, 32
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@ -47,8 +44,7 @@ entry:
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define i64 @asrl_32(i64 %X) {
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; CHECK-LABEL: asrl_32:
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; CHECK: @ %bb.0: @ %entry
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; CHECK-NEXT: movs r2, #32
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; CHECK-NEXT: asrl r0, r1, r2
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; CHECK-NEXT: asrl r0, r1, #32
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; CHECK-NEXT: bx lr
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entry:
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%0 = lshr i64 %X, 32
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@ -127,8 +123,7 @@ entry:
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define i64 @asrl_m2(i64 %X) {
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; CHECK-LABEL: asrl_m2:
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; CHECK: @ %bb.0: @ %entry
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; CHECK-NEXT: mvn r2, #1
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; CHECK-NEXT: asrl r0, r1, r2
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; CHECK-NEXT: lsll r0, r1, #2
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; CHECK-NEXT: bx lr
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entry:
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%0 = lshr i64 %X, 32
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@ -147,8 +142,7 @@ entry:
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define i64 @asrl_m32(i64 %X) {
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; CHECK-LABEL: asrl_m32:
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; CHECK: @ %bb.0: @ %entry
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; CHECK-NEXT: mvn r2, #31
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; CHECK-NEXT: asrl r0, r1, r2
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; CHECK-NEXT: lsll r0, r1, #32
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; CHECK-NEXT: bx lr
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entry:
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%0 = lshr i64 %X, 32
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@ -210,8 +204,6 @@ entry:
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define i64 @lsll_0(i64 %X) {
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; CHECK-LABEL: lsll_0:
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; CHECK: @ %bb.0: @ %entry
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; CHECK-NEXT: movs r2, #0
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; CHECK-NEXT: lsll r0, r1, r2
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; CHECK-NEXT: bx lr
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entry:
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%0 = lshr i64 %X, 32
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@ -230,8 +222,7 @@ entry:
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define i64 @lsll_23(i64 %X) {
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; CHECK-LABEL: lsll_23:
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; CHECK: @ %bb.0: @ %entry
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; CHECK-NEXT: movs r2, #23
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; CHECK-NEXT: lsll r0, r1, r2
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; CHECK-NEXT: lsll r0, r1, #23
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; CHECK-NEXT: bx lr
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entry:
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%0 = lshr i64 %X, 32
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@ -250,8 +241,7 @@ entry:
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define i64 @lsll_32(i64 %X) {
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; CHECK-LABEL: lsll_32:
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; CHECK: @ %bb.0: @ %entry
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; CHECK-NEXT: movs r2, #32
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; CHECK-NEXT: lsll r0, r1, r2
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; CHECK-NEXT: lsll r0, r1, #32
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; CHECK-NEXT: bx lr
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entry:
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%0 = lshr i64 %X, 32
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@ -330,8 +320,7 @@ entry:
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define i64 @lsll_m2(i64 %X) {
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; CHECK-LABEL: lsll_m2:
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; CHECK: @ %bb.0: @ %entry
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; CHECK-NEXT: mvn r2, #1
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; CHECK-NEXT: lsll r0, r1, r2
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; CHECK-NEXT: lsrl r0, r1, #2
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; CHECK-NEXT: bx lr
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entry:
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%0 = lshr i64 %X, 32
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@ -350,8 +339,7 @@ entry:
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define i64 @lsll_m32(i64 %X) {
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; CHECK-LABEL: lsll_m32:
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; CHECK: @ %bb.0: @ %entry
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; CHECK-NEXT: mvn r2, #31
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; CHECK-NEXT: lsll r0, r1, r2
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; CHECK-NEXT: lsrl r0, r1, #32
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; CHECK-NEXT: bx lr
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entry:
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%0 = lshr i64 %X, 32
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@ -7,8 +7,7 @@ declare {i32, i32} @llvm.arm.mve.lsll(i32, i32, i32)
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define i32 @ashr_demand_bottom3(i64 %X) {
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; CHECK-LABEL: ashr_demand_bottom3:
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; CHECK: @ %bb.0: @ %entry
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; CHECK-NEXT: movs r2, #3
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; CHECK-NEXT: asrl r0, r1, r2
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; CHECK-NEXT: asrl r0, r1, #3
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; CHECK-NEXT: bx lr
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entry:
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%0 = lshr i64 %X, 32
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@ -28,8 +27,7 @@ entry:
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define i32 @lsll_demand_bottom3(i64 %X) {
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; CHECK-LABEL: lsll_demand_bottom3:
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; CHECK: @ %bb.0: @ %entry
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; CHECK-NEXT: movs r2, #3
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; CHECK-NEXT: lsll r0, r1, r2
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; CHECK-NEXT: lsll r0, r1, #3
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; CHECK-NEXT: bx lr
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entry:
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%0 = lshr i64 %X, 32
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@ -49,8 +47,7 @@ entry:
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define i32 @ashr_demand_bottomm3(i64 %X) {
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; CHECK-LABEL: ashr_demand_bottomm3:
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; CHECK: @ %bb.0: @ %entry
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; CHECK-NEXT: mvn r2, #2
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; CHECK-NEXT: asrl r0, r1, r2
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; CHECK-NEXT: lsll r0, r1, #3
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; CHECK-NEXT: bx lr
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entry:
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%0 = lshr i64 %X, 32
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@ -70,8 +67,7 @@ entry:
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define i32 @lsll_demand_bottomm3(i64 %X) {
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; CHECK-LABEL: lsll_demand_bottomm3:
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; CHECK: @ %bb.0: @ %entry
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; CHECK-NEXT: mvn r2, #2
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; CHECK-NEXT: lsll r0, r1, r2
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; CHECK-NEXT: lsrl r0, r1, #3
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; CHECK-NEXT: bx lr
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entry:
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%0 = lshr i64 %X, 32
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@ -92,8 +88,7 @@ entry:
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define i32 @ashr_demand_bottom31(i64 %X) {
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; CHECK-LABEL: ashr_demand_bottom31:
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; CHECK: @ %bb.0: @ %entry
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; CHECK-NEXT: movs r2, #31
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; CHECK-NEXT: asrl r0, r1, r2
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; CHECK-NEXT: asrl r0, r1, #31
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; CHECK-NEXT: bx lr
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entry:
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%0 = lshr i64 %X, 32
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@ -113,8 +108,7 @@ entry:
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define i32 @lsll_demand_bottom31(i64 %X) {
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; CHECK-LABEL: lsll_demand_bottom31:
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; CHECK: @ %bb.0: @ %entry
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; CHECK-NEXT: movs r2, #31
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; CHECK-NEXT: lsll r0, r1, r2
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; CHECK-NEXT: lsll r0, r1, #31
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; CHECK-NEXT: bx lr
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entry:
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%0 = lshr i64 %X, 32
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@ -134,8 +128,7 @@ entry:
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define i32 @ashr_demand_bottomm31(i64 %X) {
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; CHECK-LABEL: ashr_demand_bottomm31:
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; CHECK: @ %bb.0: @ %entry
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; CHECK-NEXT: mvn r2, #30
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; CHECK-NEXT: asrl r0, r1, r2
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; CHECK-NEXT: lsll r0, r1, #31
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; CHECK-NEXT: bx lr
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entry:
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%0 = lshr i64 %X, 32
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@ -155,8 +148,7 @@ entry:
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define i32 @lsll_demand_bottomm31(i64 %X) {
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; CHECK-LABEL: lsll_demand_bottomm31:
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; CHECK: @ %bb.0: @ %entry
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; CHECK-NEXT: mvn r2, #30
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; CHECK-NEXT: lsll r0, r1, r2
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; CHECK-NEXT: lsrl r0, r1, #31
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; CHECK-NEXT: bx lr
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entry:
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%0 = lshr i64 %X, 32
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@ -177,8 +169,7 @@ entry:
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define i32 @ashr_demand_bottom32(i64 %X) {
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; CHECK-LABEL: ashr_demand_bottom32:
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; CHECK: @ %bb.0: @ %entry
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; CHECK-NEXT: movs r2, #32
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; CHECK-NEXT: asrl r0, r1, r2
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; CHECK-NEXT: asrl r0, r1, #32
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; CHECK-NEXT: bx lr
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entry:
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%0 = lshr i64 %X, 32
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@ -198,8 +189,7 @@ entry:
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define i32 @lsll_demand_bottom32(i64 %X) {
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; CHECK-LABEL: lsll_demand_bottom32:
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; CHECK: @ %bb.0: @ %entry
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; CHECK-NEXT: movs r2, #32
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; CHECK-NEXT: lsll r0, r1, r2
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; CHECK-NEXT: lsll r0, r1, #32
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; CHECK-NEXT: bx lr
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entry:
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%0 = lshr i64 %X, 32
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@ -219,8 +209,7 @@ entry:
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define i32 @ashr_demand_bottomm32(i64 %X) {
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; CHECK-LABEL: ashr_demand_bottomm32:
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; CHECK: @ %bb.0: @ %entry
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; CHECK-NEXT: mvn r2, #31
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; CHECK-NEXT: asrl r0, r1, r2
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; CHECK-NEXT: lsll r0, r1, #32
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; CHECK-NEXT: bx lr
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entry:
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%0 = lshr i64 %X, 32
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@ -240,8 +229,7 @@ entry:
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define i32 @lsll_demand_bottomm32(i64 %X) {
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; CHECK-LABEL: lsll_demand_bottomm32:
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; CHECK: @ %bb.0: @ %entry
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; CHECK-NEXT: mvn r2, #31
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; CHECK-NEXT: lsll r0, r1, r2
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; CHECK-NEXT: lsrl r0, r1, #32
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; CHECK-NEXT: bx lr
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entry:
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%0 = lshr i64 %X, 32
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@ -352,8 +340,7 @@ entry:
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define i32 @ashr_demand_top3(i64 %X) {
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; CHECK-LABEL: ashr_demand_top3:
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; CHECK: @ %bb.0: @ %entry
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; CHECK-NEXT: movs r2, #3
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; CHECK-NEXT: asrl r0, r1, r2
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; CHECK-NEXT: asrl r0, r1, #3
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; CHECK-NEXT: mov r0, r1
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; CHECK-NEXT: bx lr
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entry:
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@ -375,8 +362,7 @@ entry:
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define i32 @lsll_demand_top3(i64 %X) {
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; CHECK-LABEL: lsll_demand_top3:
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; CHECK: @ %bb.0: @ %entry
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; CHECK-NEXT: movs r2, #3
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; CHECK-NEXT: lsll r0, r1, r2
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; CHECK-NEXT: lsll r0, r1, #3
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; CHECK-NEXT: mov r0, r1
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; CHECK-NEXT: bx lr
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entry:
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@ -398,8 +384,7 @@ entry:
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define i32 @ashr_demand_topm3(i64 %X) {
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; CHECK-LABEL: ashr_demand_topm3:
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; CHECK: @ %bb.0: @ %entry
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; CHECK-NEXT: mvn r2, #2
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; CHECK-NEXT: asrl r0, r1, r2
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; CHECK-NEXT: lsll r0, r1, #3
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; CHECK-NEXT: mov r0, r1
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; CHECK-NEXT: bx lr
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entry:
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@ -421,8 +406,7 @@ entry:
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define i32 @lsll_demand_topm3(i64 %X) {
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; CHECK-LABEL: lsll_demand_topm3:
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; CHECK: @ %bb.0: @ %entry
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; CHECK-NEXT: mvn r2, #2
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; CHECK-NEXT: lsll r0, r1, r2
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; CHECK-NEXT: lsrl r0, r1, #3
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; CHECK-NEXT: mov r0, r1
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; CHECK-NEXT: bx lr
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entry:
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@ -445,8 +429,7 @@ entry:
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define i32 @ashr_demand_top31(i64 %X) {
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; CHECK-LABEL: ashr_demand_top31:
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; CHECK: @ %bb.0: @ %entry
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; CHECK-NEXT: movs r2, #31
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; CHECK-NEXT: asrl r0, r1, r2
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; CHECK-NEXT: asrl r0, r1, #31
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; CHECK-NEXT: mov r0, r1
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; CHECK-NEXT: bx lr
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entry:
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@ -468,8 +451,7 @@ entry:
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define i32 @lsll_demand_top31(i64 %X) {
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; CHECK-LABEL: lsll_demand_top31:
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; CHECK: @ %bb.0: @ %entry
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; CHECK-NEXT: movs r2, #31
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; CHECK-NEXT: lsll r0, r1, r2
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; CHECK-NEXT: lsll r0, r1, #31
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; CHECK-NEXT: mov r0, r1
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; CHECK-NEXT: bx lr
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entry:
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@ -491,8 +473,7 @@ entry:
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define i32 @ashr_demand_topm31(i64 %X) {
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; CHECK-LABEL: ashr_demand_topm31:
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; CHECK: @ %bb.0: @ %entry
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; CHECK-NEXT: mvn r2, #30
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; CHECK-NEXT: asrl r0, r1, r2
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; CHECK-NEXT: lsll r0, r1, #31
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; CHECK-NEXT: mov r0, r1
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; CHECK-NEXT: bx lr
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entry:
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@ -514,8 +495,7 @@ entry:
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define i32 @lsll_demand_topm31(i64 %X) {
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; CHECK-LABEL: lsll_demand_topm31:
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; CHECK: @ %bb.0: @ %entry
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; CHECK-NEXT: mvn r2, #30
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; CHECK-NEXT: lsll r0, r1, r2
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; CHECK-NEXT: lsrl r0, r1, #31
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; CHECK-NEXT: mov r0, r1
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; CHECK-NEXT: bx lr
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entry:
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@ -538,8 +518,7 @@ entry:
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define i32 @ashr_demand_top32(i64 %X) {
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; CHECK-LABEL: ashr_demand_top32:
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; CHECK: @ %bb.0: @ %entry
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; CHECK-NEXT: movs r2, #32
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; CHECK-NEXT: asrl r0, r1, r2
|
||||
; CHECK-NEXT: asrl r0, r1, #32
|
||||
; CHECK-NEXT: mov r0, r1
|
||||
; CHECK-NEXT: bx lr
|
||||
entry:
|
||||
@ -561,8 +540,7 @@ entry:
|
||||
define i32 @lsll_demand_top32(i64 %X) {
|
||||
; CHECK-LABEL: lsll_demand_top32:
|
||||
; CHECK: @ %bb.0: @ %entry
|
||||
; CHECK-NEXT: movs r2, #32
|
||||
; CHECK-NEXT: lsll r0, r1, r2
|
||||
; CHECK-NEXT: lsll r0, r1, #32
|
||||
; CHECK-NEXT: mov r0, r1
|
||||
; CHECK-NEXT: bx lr
|
||||
entry:
|
||||
@ -584,8 +562,7 @@ entry:
|
||||
define i32 @ashr_demand_topm32(i64 %X) {
|
||||
; CHECK-LABEL: ashr_demand_topm32:
|
||||
; CHECK: @ %bb.0: @ %entry
|
||||
; CHECK-NEXT: mvn r2, #31
|
||||
; CHECK-NEXT: asrl r0, r1, r2
|
||||
; CHECK-NEXT: lsll r0, r1, #32
|
||||
; CHECK-NEXT: mov r0, r1
|
||||
; CHECK-NEXT: bx lr
|
||||
entry:
|
||||
@ -607,8 +584,7 @@ entry:
|
||||
define i32 @lsll_demand_topm32(i64 %X) {
|
||||
; CHECK-LABEL: lsll_demand_topm32:
|
||||
; CHECK: @ %bb.0: @ %entry
|
||||
; CHECK-NEXT: mvn r2, #31
|
||||
; CHECK-NEXT: lsll r0, r1, r2
|
||||
; CHECK-NEXT: lsrl r0, r1, #32
|
||||
; CHECK-NEXT: mov r0, r1
|
||||
; CHECK-NEXT: bx lr
|
||||
entry:
|
||||
@ -725,8 +701,7 @@ entry:
|
||||
define i32 @ashr_demand_bottommask3(i64 %X) {
|
||||
; CHECK-LABEL: ashr_demand_bottommask3:
|
||||
; CHECK: @ %bb.0: @ %entry
|
||||
; CHECK-NEXT: movs r2, #3
|
||||
; CHECK-NEXT: asrl r0, r1, r2
|
||||
; CHECK-NEXT: asrl r0, r1, #3
|
||||
; CHECK-NEXT: bic r0, r0, #1
|
||||
; CHECK-NEXT: bx lr
|
||||
entry:
|
||||
@ -748,8 +723,7 @@ entry:
|
||||
define i32 @lsll_demand_bottommask3(i64 %X) {
|
||||
; CHECK-LABEL: lsll_demand_bottommask3:
|
||||
; CHECK: @ %bb.0: @ %entry
|
||||
; CHECK-NEXT: movs r2, #3
|
||||
; CHECK-NEXT: lsll r0, r1, r2
|
||||
; CHECK-NEXT: lsll r0, r1, #3
|
||||
; CHECK-NEXT: bic r0, r0, #1
|
||||
; CHECK-NEXT: bx lr
|
||||
entry:
|
||||
@ -771,8 +745,7 @@ entry:
|
||||
define i32 @ashr_demand_bottommaskm3(i64 %X) {
|
||||
; CHECK-LABEL: ashr_demand_bottommaskm3:
|
||||
; CHECK: @ %bb.0: @ %entry
|
||||
; CHECK-NEXT: mvn r2, #2
|
||||
; CHECK-NEXT: asrl r0, r1, r2
|
||||
; CHECK-NEXT: lsll r0, r1, #3
|
||||
; CHECK-NEXT: bic r0, r0, #1
|
||||
; CHECK-NEXT: bx lr
|
||||
entry:
|
||||
@ -794,8 +767,7 @@ entry:
|
||||
define i32 @lsll_demand_bottommaskm3(i64 %X) {
|
||||
; CHECK-LABEL: lsll_demand_bottommaskm3:
|
||||
; CHECK: @ %bb.0: @ %entry
|
||||
; CHECK-NEXT: mvn r2, #2
|
||||
; CHECK-NEXT: lsll r0, r1, r2
|
||||
; CHECK-NEXT: lsrl r0, r1, #3
|
||||
; CHECK-NEXT: bic r0, r0, #1
|
||||
; CHECK-NEXT: bx lr
|
||||
entry:
|
||||
@ -818,8 +790,7 @@ entry:
|
||||
define i32 @ashr_demand_bottommask32(i64 %X) {
|
||||
; CHECK-LABEL: ashr_demand_bottommask32:
|
||||
; CHECK: @ %bb.0: @ %entry
|
||||
; CHECK-NEXT: movs r2, #32
|
||||
; CHECK-NEXT: asrl r0, r1, r2
|
||||
; CHECK-NEXT: asrl r0, r1, #32
|
||||
; CHECK-NEXT: bic r0, r0, #1
|
||||
; CHECK-NEXT: bx lr
|
||||
entry:
|
||||
@ -841,8 +812,7 @@ entry:
|
||||
define i32 @lsll_demand_bottommask32(i64 %X) {
|
||||
; CHECK-LABEL: lsll_demand_bottommask32:
|
||||
; CHECK: @ %bb.0: @ %entry
|
||||
; CHECK-NEXT: movs r2, #32
|
||||
; CHECK-NEXT: lsll r0, r1, r2
|
||||
; CHECK-NEXT: lsll r0, r1, #32
|
||||
; CHECK-NEXT: bic r0, r0, #1
|
||||
; CHECK-NEXT: bx lr
|
||||
entry:
|
||||
@ -864,8 +834,7 @@ entry:
|
||||
define i32 @ashr_demand_bottommaskm32(i64 %X) {
|
||||
; CHECK-LABEL: ashr_demand_bottommaskm32:
|
||||
; CHECK: @ %bb.0: @ %entry
|
||||
; CHECK-NEXT: mvn r2, #31
|
||||
; CHECK-NEXT: asrl r0, r1, r2
|
||||
; CHECK-NEXT: lsll r0, r1, #32
|
||||
; CHECK-NEXT: bic r0, r0, #1
|
||||
; CHECK-NEXT: bx lr
|
||||
entry:
|
||||
@ -887,8 +856,7 @@ entry:
|
||||
define i32 @lsll_demand_bottommaskm32(i64 %X) {
|
||||
; CHECK-LABEL: lsll_demand_bottommaskm32:
|
||||
; CHECK: @ %bb.0: @ %entry
|
||||
; CHECK-NEXT: mvn r2, #31
|
||||
; CHECK-NEXT: lsll r0, r1, r2
|
||||
; CHECK-NEXT: lsrl r0, r1, #32
|
||||
; CHECK-NEXT: bic r0, r0, #1
|
||||
; CHECK-NEXT: bx lr
|
||||
entry:
|
||||
|
||||
Loading…
Reference in New Issue
Block a user