mirror of
https://github.com/RPCS3/llvm-mirror.git
synced 2024-10-20 19:42:54 +02:00
Fixed a bug in the IT mask printing where T means the cond bit in the mask
matches that of Firstcond[0] and E means otherwise. The Firstcond[0] is also tagged in the Mask to facilitate Asm printing. The disassembler also depends on this arrangement. This is similar to what's described in A2.5.2 ITSTATE. Ran: utils/lit/lit.py test/CodeGen/ARM test/CodeGen/Thumb test/CodeGen/Thumb2 successfully. llvm-svn: 98775
This commit is contained in:
parent
5c58c86098
commit
08d7095c33
@ -78,14 +78,16 @@ bool Thumb2ITBlockPass::InsertITBlocks(MachineBasicBlock &MBB) {
|
|||||||
DebugLoc ndl = NMI->getDebugLoc();
|
DebugLoc ndl = NMI->getDebugLoc();
|
||||||
unsigned NPredReg = 0;
|
unsigned NPredReg = 0;
|
||||||
ARMCC::CondCodes NCC = getPredicate(NMI, NPredReg);
|
ARMCC::CondCodes NCC = getPredicate(NMI, NPredReg);
|
||||||
if (NCC == OCC) {
|
if (NCC == CC || NCC == OCC)
|
||||||
Mask |= (1 << Pos);
|
Mask |= (NCC & 1) << Pos;
|
||||||
} else if (NCC != CC)
|
else
|
||||||
break;
|
break;
|
||||||
--Pos;
|
--Pos;
|
||||||
++MBBI;
|
++MBBI;
|
||||||
}
|
}
|
||||||
Mask |= (1 << Pos);
|
Mask |= (1 << Pos);
|
||||||
|
// Tag along (firstcond[0] << 4) with the mask.
|
||||||
|
Mask |= (CC & 1) << 4;
|
||||||
MIB.addImm(Mask);
|
MIB.addImm(Mask);
|
||||||
Modified = true;
|
Modified = true;
|
||||||
++NumITs;
|
++NumITs;
|
||||||
|
Loading…
Reference in New Issue
Block a user