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Add support for llvm.arm.neon.vmull* intrinsics to InstCombine. This fixes
<rdar://problem/11291436>. llvm-svn: 155468
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Lang Hames
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commit
08eb5f2340
@ -14,6 +14,7 @@
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#include "InstCombine.h"
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#include "llvm/Support/CallSite.h"
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#include "llvm/Target/TargetData.h"
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#include "llvm/Analysis/InstructionSimplify.h"
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#include "llvm/Analysis/MemoryBuiltins.h"
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#include "llvm/Transforms/Utils/BuildLibCalls.h"
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#include "llvm/Transforms/Utils/Local.h"
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@ -694,6 +695,40 @@ Instruction *InstCombiner::visitCallInst(CallInst &CI) {
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break;
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}
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case Intrinsic::arm_neon_vmulls:
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case Intrinsic::arm_neon_vmullu: {
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// Zext/sext intrinsic operands according to the intrinsic type, then try to
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// simplify them. This lets us try a SimplifyMulInst on the extended
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// operands. If the zext/sext instructions are unused when we're done then
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// delete them from the block.
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Value* Arg0 = II->getArgOperand(0);
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Value* Arg1 = II->getArgOperand(1);
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bool Zext = (II->getIntrinsicID() == Intrinsic::arm_neon_vmullu);
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Instruction *Arg0W =
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Zext ? CastInst::CreateZExtOrBitCast(Arg0, II->getType(), "", II) :
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CastInst::CreateSExtOrBitCast(Arg0, II->getType(), "", II);
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Value* Arg0WS = SimplifyInstruction(Arg0W);
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if (Arg0WS == 0) // If simplification fails just pass through the ext'd val.
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Arg0WS = Arg0W;
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Instruction *Arg1W =
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Zext ? CastInst::CreateZExtOrBitCast(Arg1, II->getType(), "", II) :
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CastInst::CreateSExtOrBitCast(Arg1, II->getType(), "", II);
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Value* Arg1WS = SimplifyInstruction(Arg1W);
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if (Arg1WS == 0)
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Arg1WS = Arg1W;
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Instruction *SimplifiedInst = 0;
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if (Value* V = SimplifyMulInst(Arg0WS, Arg1WS, TD)) {
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SimplifiedInst = ReplaceInstUsesWith(CI, V);
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}
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if (Arg0W->use_empty())
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Arg0W->eraseFromParent();
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if (Arg1W->use_empty())
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Arg1W->eraseFromParent();
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if (SimplifiedInst != 0)
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return SimplifiedInst;
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break;
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}
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case Intrinsic::stackrestore: {
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// If the save is right next to the restore, remove the restore. This can
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// happen when variable allocas are DCE'd.
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68
test/Transforms/InstCombine/2012-04-23-Neon-Intrinsics.ll
Normal file
68
test/Transforms/InstCombine/2012-04-23-Neon-Intrinsics.ll
Normal file
@ -0,0 +1,68 @@
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target datalayout = "e-p:32:32:32-i1:8:32-i8:8:32-i16:16:32-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:32:64-v128:32:128-a0:0:32-n32-S32"
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target triple = "thumbv7-apple-ios0"
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; RUN: opt -S -instcombine < %s | FileCheck %s
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define <4 x i32> @mulByZero(<4 x i16> %x) nounwind readnone ssp {
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entry:
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%a = tail call <4 x i32> @llvm.arm.neon.vmulls.v4i32(<4 x i16> %x, <4 x i16> zeroinitializer) nounwind
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ret <4 x i32> %a
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; CHECK: entry:
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; CHECK-NEXT: ret <4 x i32> zeroinitializer
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}
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define <4 x i32> @mulByOne(<4 x i16> %x) nounwind readnone ssp {
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entry:
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%a = tail call <4 x i32> @llvm.arm.neon.vmulls.v4i32(<4 x i16> %x, <4 x i16> <i16 1, i16 1, i16 1, i16 1>) nounwind
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ret <4 x i32> %a
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; CHECK: entry:
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; CHECK-NEXT: %0 = sext <4 x i16> %x to <4 x i32>
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; CHECK-NEXT: ret <4 x i32> %0
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}
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define <4 x i32> @constantMul() nounwind readnone ssp {
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entry:
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%a = tail call <4 x i32> @llvm.arm.neon.vmulls.v4i32(<4 x i16> <i16 3, i16 3, i16 3, i16 3>, <4 x i16> <i16 2, i16 2, i16 2, i16 2>) nounwind
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ret <4 x i32> %a
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; CHECK: entry:
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; CHECK-NEXT: ret <4 x i32> <i32 6, i32 6, i32 6, i32 6>
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}
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define <4 x i32> @constantMulS() nounwind readnone ssp {
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entry:
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%b = tail call <4 x i32> @llvm.arm.neon.vmulls.v4i32(<4 x i16> <i16 -1, i16 -1, i16 -1, i16 -1>, <4 x i16> <i16 1, i16 1, i16 1, i16 1>) nounwind
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ret <4 x i32> %b
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; CHECK: entry:
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; CHECK-NEXT: ret <4 x i32> <i32 -1, i32 -1, i32 -1, i32 -1>
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}
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define <4 x i32> @constantMulU() nounwind readnone ssp {
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entry:
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%b = tail call <4 x i32> @llvm.arm.neon.vmullu.v4i32(<4 x i16> <i16 -1, i16 -1, i16 -1, i16 -1>, <4 x i16> <i16 1, i16 1, i16 1, i16 1>) nounwind
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ret <4 x i32> %b
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; CHECK: entry:
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; CHECK-NEXT: ret <4 x i32> <i32 65535, i32 65535, i32 65535, i32 65535>
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}
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define <4 x i32> @complex1(<4 x i16> %x) nounwind readnone ssp {
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entry:
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%a = tail call <4 x i32> @llvm.arm.neon.vmulls.v4i32(<4 x i16> <i16 2, i16 2, i16 2, i16 2>, <4 x i16> %x) nounwind
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%b = add <4 x i32> zeroinitializer, %a
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ret <4 x i32> %b
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; CHECK: entry:
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; CHECK-NEXT: %a = tail call <4 x i32> @llvm.arm.neon.vmulls.v4i32(<4 x i16> <i16 2, i16 2, i16 2, i16 2>, <4 x i16> %x) nounwind
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; CHECK-NEXT: ret <4 x i32> %a
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}
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define <4 x i32> @complex2(<4 x i32> %x) nounwind readnone ssp {
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entry:
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%a = tail call <4 x i32> @llvm.arm.neon.vmulls.v4i32(<4 x i16> <i16 3, i16 3, i16 3, i16 3>, <4 x i16> <i16 2, i16 2, i16 2, i16 2>) nounwind
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%b = add <4 x i32> %x, %a
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ret <4 x i32> %b
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; CHECK: entry:
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; CHECK-NEXT: %b = add <4 x i32> %x, <i32 6, i32 6, i32 6, i32 6>
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; CHECK-NEXT: ret <4 x i32> %b
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}
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declare <4 x i32> @llvm.arm.neon.vmulls.v4i32(<4 x i16>, <4 x i16>) nounwind readnone
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declare <4 x i32> @llvm.arm.neon.vmullu.v4i32(<4 x i16>, <4 x i16>) nounwind readnone
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