mirror of
https://github.com/RPCS3/llvm-mirror.git
synced 2025-01-31 12:41:49 +01:00
Do not insert prefetches with unsupported memory operands.
Summary: Ignore advices where the memory operand of the 'anchor' instruction uses unsupported register types. Reviewers: davidxl Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D54983 llvm-svn: 347724
This commit is contained in:
parent
f3afb84186
commit
0953e7ad7b
@ -76,6 +76,19 @@ ErrorOr<PrefetchHints> getPrefetchHints(const FunctionSamples *TopSamples,
|
||||
return std::error_code();
|
||||
}
|
||||
|
||||
// The prefetch instruction can't take memory operands involving vector
|
||||
// registers.
|
||||
bool IsMemOpCompatibleWithPrefetch(const MachineInstr &MI, int Op) {
|
||||
unsigned BaseReg = MI.getOperand(Op + X86::AddrBaseReg).getReg();
|
||||
unsigned IndexReg = MI.getOperand(Op + X86::AddrIndexReg).getReg();
|
||||
return (BaseReg == 0 ||
|
||||
X86MCRegisterClasses[X86::GR64RegClassID].contains(BaseReg) ||
|
||||
X86MCRegisterClasses[X86::GR32RegClassID].contains(BaseReg)) &&
|
||||
(IndexReg == 0 ||
|
||||
X86MCRegisterClasses[X86::GR64RegClassID].contains(IndexReg) ||
|
||||
X86MCRegisterClasses[X86::GR32RegClassID].contains(IndexReg));
|
||||
}
|
||||
|
||||
} // end anonymous namespace
|
||||
|
||||
//===----------------------------------------------------------------------===//
|
||||
@ -182,6 +195,11 @@ bool X86InsertPrefetch::runOnMachineFunction(MachineFunction &MF) {
|
||||
int Offset = X86II::getMemoryOperandNo(Current->getDesc().TSFlags);
|
||||
if (Offset < 0)
|
||||
continue;
|
||||
unsigned Bias = X86II::getOperandBias(Current->getDesc());
|
||||
int MemOpOffset = Offset + Bias;
|
||||
// FIXME(mtrofin): ORE message when the recommendation cannot be taken.
|
||||
if (!IsMemOpCompatibleWithPrefetch(*Current, MemOpOffset))
|
||||
continue;
|
||||
Prefetches.clear();
|
||||
if (!findPrefetchInfo(Samples, *Current, Prefetches))
|
||||
continue;
|
||||
@ -195,8 +213,6 @@ bool X86InsertPrefetch::runOnMachineFunction(MachineFunction &MF) {
|
||||
MachineInstr *PFetch =
|
||||
MF.CreateMachineInstr(Desc, Current->getDebugLoc(), true);
|
||||
MachineInstrBuilder MIB(MF, PFetch);
|
||||
unsigned Bias = X86II::getOperandBias(Current->getDesc());
|
||||
int MemOpOffset = Offset + Bias;
|
||||
|
||||
assert(X86::AddrBaseReg == 0 && X86::AddrScaleAmt == 1 &&
|
||||
X86::AddrIndexReg == 2 && X86::AddrDisp == 3 &&
|
||||
|
@ -1,4 +1,4 @@
|
||||
; RUN: llc < %s -prefetch-hints-file=%S/insert-prefetch-nomemop.afdo | FileCheck %s
|
||||
; RUN: llc < %s -prefetch-hints-file=%S/insert-prefetch-invalid-instr.afdo | FileCheck %s
|
||||
; ModuleID = 'prefetch.cc'
|
||||
source_filename = "prefetch.cc"
|
||||
target datalayout = "e-m:e-i64:64-f80:128-n8:16:32:64-S128"
|
||||
@ -42,5 +42,5 @@ attributes #2 = { argmemonly nounwind }
|
||||
;CHECK-LABEL: main:
|
||||
;CHECK: # %bb.0:
|
||||
;CHECK: prefetchnta 291
|
||||
;CHECK: prefetchnta 42(%rax,%ymm0)
|
||||
;CHECK-NEXT: vgatherpf1dpd (%rax,%ymm0) {%k1}
|
||||
;CHECK-NOT: prefetchnta 42(%rax,%ymm0)
|
||||
;CHECK: vgatherpf1dpd (%rax,%ymm0) {%k1}
|
Loading…
x
Reference in New Issue
Block a user