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[MachineOperand][Target] MachineOperand::isRenamable semantics changes

Browse Source 
Summary:
Add a target option AllowRegisterRenaming that is used to opt in to
post-register-allocation renaming of registers.  This is set to 0 by
default, which causes the hasExtraSrcRegAllocReq/hasExtraDstRegAllocReq
fields of all opcodes to be set to 1, causing
MachineOperand::isRenamable to always return false.

Set the AllowRegisterRenaming flag to 1 for all in-tree targets that
have lit tests that were effected by enabling COPY forwarding in
MachineCopyPropagation (AArch64, AMDGPU, ARM, Hexagon, Mips, PowerPC,
RISCV, Sparc, SystemZ and X86).

Add some more comments describing the semantics of the
MachineOperand::isRenamable function and how it is set and maintained.

Change isRenamable to check the operand's opcode
hasExtraSrcRegAllocReq/hasExtraDstRegAllocReq bit directly instead of
relying on it being consistently reflected in the IsRenamable bit
setting.

Clear the IsRenamable bit when changing an operand's register value.

Remove target code that was clearing the IsRenamable bit when changing
registers/opcodes now that this is done conservatively by default.

Change setting of hasExtraSrcRegAllocReq in AMDGPU target to be done in
one place covering all opcodes that have constant pipe read limit
restrictions.

Reviewers: qcolombet, MatzeB

Subscribers: aemerson, arsenm, jyknight, mcrosier, sdardis, nhaehnle, javed.absar, tpr, arichardson, kristof.beyls, kbarton, fedor.sergeev, asb, rbar, johnrusso, simoncook, jordy.potman.lists, apazos, sabuasal, niosHD, escha, nemanjai, llvm-commits

Differential Revision: https://reviews.llvm.org/D43042

llvm-svn: 325931
This commit is contained in:
Geoff Berry 2018-02-23 18:25:08 +00:00
parent 4463a15855
commit 097bf66bf4
31 changed files with 100 additions and 71 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

3
include/llvm/CodeGen/MachineInstr.h
View File

@ -1126,8 +1126,7 @@ public:
/// Replace all occurrences of FromReg with ToReg:SubIdx,
/// properly composing subreg indices where necessary.
void substituteRegister(unsigned FromReg, unsigned ToReg, unsigned SubIdx,
const TargetRegisterInfo &RegInfo,
bool ClearIsRenamable = false);
const TargetRegisterInfo &RegInfo);
/// We have determined MI kills a register. Look for the
/// operand that uses it and mark it as IsKill. If AddIfNotFound is true,

39
include/llvm/CodeGen/MachineOperand.h
View File

@ -105,11 +105,7 @@ private:
/// This is only valid on register operands.
unsigned IsDeadOrKill : 1;
/// IsRenamable - True if this register may be renamed, i.e. it does not
/// generate a value that is somehow read in a way that is not represented by
/// the Machine IR (e.g. to meet an ABI or ISA requirement). This is only
/// valid on physical register operands. Virtual registers are assumed to
/// always be renamable regardless of the value of this field.
/// See isRenamable().
unsigned IsRenamable : 1;
/// IsUndef - True if this register operand reads an "undef" value, i.e. the
@ -384,6 +380,35 @@ public:
return IsUndef;
}
/// isRenamable - Returns true if this register may be renamed, i.e. it does
/// not generate a value that is somehow read in a way that is not represented
/// by the Machine IR (e.g. to meet an ABI or ISA requirement). This is only
/// valid on physical register operands. Virtual registers are assumed to
/// always be renamable regardless of the value of this field.
///
/// Operands that are renamable can freely be changed to any other register
/// that is a member of the register class returned by
/// MI->getRegClassConstraint().
///
/// isRenamable can return false for several different reasons:
///
/// - ABI constraints (since liveness is not always precisely modeled). We
/// conservatively handle these cases by setting all physical register
/// operands that didn’t start out as virtual regs to not be renamable.
/// Also any physical register operands created after register allocation or
/// whose register is changed after register allocation will not be
/// renamable. This state is tracked in the MachineOperand::IsRenamable
/// bit.
///
/// - Opcode/target constraints: for opcodes that have complex register class
/// requirements (e.g. that depend on other operands/instructions), we set
/// hasExtraSrcRegAllocReq/hasExtraDstRegAllocReq in the machine opcode
/// description. Operands belonging to instructions with opcodes that are
/// marked hasExtraSrcRegAllocReq/hasExtraDstRegAllocReq return false from
/// isRenamable(). Additionally, the AllowRegisterRenaming target property
/// prevents any operands from being marked renamable for targets that don't
/// have detailed opcode hasExtraSrcRegAllocReq/hasExtraDstRegAllocReq
/// values.
bool isRenamable() const;
bool isInternalRead() const {
@ -473,10 +498,6 @@ public:
void setIsRenamable(bool Val = true);
/// Set IsRenamable to true if there are no extra register allocation
/// requirements placed on this operand by the parent instruction's opcode.
void setIsRenamableIfNoExtraRegAllocReq();
void setIsInternalRead(bool Val = true) {
assert(isReg() && "Wrong MachineOperand mutator");
IsInternalRead = Val;

6
include/llvm/Target/Target.td
View File

@ -1362,6 +1362,12 @@ class Target {
// AssemblyWriters - The AsmWriter instances available for this target.
list<AsmWriter> AssemblyWriters = [DefaultAsmWriter];
// AllowRegisterRenaming - Controls whether this target allows
// post-register-allocation renaming of registers. This is done by
// setting hasExtraDefRegAllocReq and hasExtraSrcRegAllocReq to 1
// for all opcodes if this flag is set to 0.
int AllowRegisterRenaming = 0;
}
//===----------------------------------------------------------------------===//

6
lib/CodeGen/MachineInstr.cpp
View File

@ -930,8 +930,7 @@ void MachineInstr::clearKillInfo() {
void MachineInstr::substituteRegister(unsigned FromReg, unsigned ToReg,
unsigned SubIdx,
const TargetRegisterInfo &RegInfo,
bool ClearIsRenamable) {
const TargetRegisterInfo &RegInfo) {
if (TargetRegisterInfo::isPhysicalRegister(ToReg)) {
if (SubIdx)
ToReg = RegInfo.getSubReg(ToReg, SubIdx);
@ -939,11 +938,8 @@ void MachineInstr::substituteRegister(unsigned FromReg, unsigned ToReg,
if (!MO.isReg() || MO.getReg() != FromReg)
continue;
MO.substPhysReg(ToReg, RegInfo);
if (ClearIsRenamable)
MO.setIsRenamable(false);
}
} else {
assert(!ClearIsRenamable && "IsRenamable invalid for virtual registers");
for (MachineOperand &MO : operands()) {
if (!MO.isReg() || MO.getReg() != FromReg)
continue;

30
lib/CodeGen/MachineOperand.cpp
View File

@ -50,6 +50,9 @@ void MachineOperand::setReg(unsigned Reg) {
if (getReg() == Reg)
return; // No change.
// Clear the IsRenamable bit to keep it conservatively correct.
IsRenamable = false;
// Otherwise, we have to change the register. If this operand is embedded
// into a machine function, we need to update the old and new register's
// use/def lists.
@ -110,30 +113,27 @@ bool MachineOperand::isRenamable() const {
assert(isReg() && "Wrong MachineOperand accessor");
assert(TargetRegisterInfo::isPhysicalRegister(getReg()) &&
"isRenamable should only be checked on physical registers");
return IsRenamable;
if (!IsRenamable)
return false;
const MachineInstr *MI = getParent();
if (!MI)
return true;
if (isDef())
return !MI->hasExtraDefRegAllocReq(MachineInstr::IgnoreBundle);
assert(isUse() && "Reg is not def or use");
return !MI->hasExtraSrcRegAllocReq(MachineInstr::IgnoreBundle);
}
void MachineOperand::setIsRenamable(bool Val) {
assert(isReg() && "Wrong MachineOperand accessor");
assert(TargetRegisterInfo::isPhysicalRegister(getReg()) &&
"setIsRenamable should only be called on physical registers");
if (const MachineInstr *MI = getParent())
if ((isDef() && MI->hasExtraDefRegAllocReq()) ||
(isUse() && MI->hasExtraSrcRegAllocReq()))
assert(!Val && "isRenamable should be false for "
"hasExtraDefRegAllocReq/hasExtraSrcRegAllocReq opcodes");
IsRenamable = Val;
}
void MachineOperand::setIsRenamableIfNoExtraRegAllocReq() {
if (const MachineInstr *MI = getParent())
if ((isDef() && MI->hasExtraDefRegAllocReq()) ||
(isUse() && MI->hasExtraSrcRegAllocReq()))
return;
setIsRenamable(true);
}
// If this operand is currently a register operand, and if this is in a
// function, deregister the operand from the register's use/def list.
void MachineOperand::removeRegFromUses() {

8
lib/CodeGen/MachineVerifier.cpp
View File

@ -1132,15 +1132,11 @@ MachineVerifier::visitMachineOperand(const MachineOperand *MO, unsigned MONum) {
}
}
if (MO->isRenamable()) {
if ((MO->isDef() && MI->hasExtraDefRegAllocReq()) ||
(MO->isUse() && MI->hasExtraSrcRegAllocReq()))
report("Illegal isRenamable setting for opcode with extra regalloc "
"requirements",
MO, MONum);
if (MRI->isReserved(Reg))
if (MRI->isReserved(Reg)) {
report("isRenamable set on reserved register", MO, MONum);
return;
}
}
} else {
// Virtual register.
const TargetRegisterClass *RC = MRI->getRegClassOrNull(Reg);

4
lib/CodeGen/RegAllocFast.cpp
View File

@ -699,13 +699,13 @@ bool RegAllocFast::setPhysReg(MachineInstr &MI, unsigned OpNum,
bool Dead = MO.isDead();
if (!MO.getSubReg()) {
MO.setReg(PhysReg);
MO.setIsRenamableIfNoExtraRegAllocReq();
MO.setIsRenamable(true);
return MO.isKill() || Dead;
}
// Handle subregister index.
MO.setReg(PhysReg ? TRI->getSubReg(PhysReg, MO.getSubReg()) : 0);
MO.setIsRenamableIfNoExtraRegAllocReq();
MO.setIsRenamable(true);
MO.setSubReg(0);
// A kill flag implies killing the full register. Add corresponding super

2
lib/CodeGen/VirtRegMap.cpp
View File

@ -530,7 +530,7 @@ void VirtRegRewriter::rewrite() {
// Rewrite. Note we could have used MachineOperand::substPhysReg(), but
// we need the inlining here.
MO.setReg(PhysReg);
MO.setIsRenamableIfNoExtraRegAllocReq();
MO.setIsRenamable(true);
}
// Add any missing super-register kills after rewriting the whole

1
lib/Target/AArch64/AArch64.td
View File

@ -538,4 +538,5 @@ def AArch64 : Target {
let InstructionSet = AArch64InstrInfo;
let AssemblyParserVariants = [GenericAsmParserVariant, AppleAsmParserVariant];
let AssemblyWriters = [GenericAsmWriter, AppleAsmWriter];
let AllowRegisterRenaming = 1;
}

1
lib/Target/AMDGPU/AMDGPU.td
View File

@ -686,6 +686,7 @@ def AMDGPU : Target {
SDWA9AsmParserVariant,
DPPAsmParserVariant];
let AssemblyWriters = [AMDGPUAsmWriter];
let AllowRegisterRenaming = 1;
}
// Dummy Instruction itineraries for pseudo instructions

5
lib/Target/AMDGPU/SIInsertSkips.cpp
View File

@ -278,11 +278,6 @@ void SIInsertSkips::kill(MachineInstr &MI) {
.add(MI.getOperand(0))
.addImm(0); // omod
}
// Clear isRenamable bit if new opcode requires it to be 0.
if (NewMI->hasExtraSrcRegAllocReq())
for (MachineOperand &NewMO : NewMI->uses())
if (NewMO.isReg() && NewMO.isUse())
NewMO.setIsRenamable(false);
break;
}
case AMDGPU::SI_KILL_I1_TERMINATOR: {

5
lib/Target/AMDGPU/SIInstrFormats.td
View File

@ -186,6 +186,9 @@ class InstSI <dag outs, dag ins, string asm = "",
let isAsmParserOnly = !if(!eq(DisableDecoder{0}, {0}), 0, 1);
let AsmVariantName = AMDGPUAsmVariants.Default;
// Avoid changing source registers in a way that violates constant bus read limitations.
let hasExtraSrcRegAllocReq = !if(VOP1,1,!if(VOP2,1,!if(VOP3,1,!if(VOPC,1,!if(SDWA,1, !if(VALU,1,0))))));
}
class PseudoInstSI<dag outs, dag ins, list<dag> pattern = [], string asm = "">
@ -203,8 +206,6 @@ class VPseudoInstSI<dag outs, dag ins, list<dag> pattern = [], string asm = "">
: PseudoInstSI<outs, ins, pattern, asm> {
let VALU = 1;
let Uses = [EXEC];
// Avoid changing source registers in a way that violates constant bus read limitations.
let hasExtraSrcRegAllocReq = 1;
}
class CFPseudoInstSI<dag outs, dag ins, list<dag> pattern = [],

4
lib/Target/AMDGPU/SIOptimizeExecMasking.cpp
View File

@ -246,7 +246,6 @@ bool SIOptimizeExecMasking::runOnMachineFunction(MachineFunction &MF) {
DEBUG(dbgs() << "Fold exec copy: " << *PrepareExecInst);
PrepareExecInst->getOperand(0).setReg(AMDGPU::EXEC);
PrepareExecInst->getOperand(0).setIsRenamable(false);
DEBUG(dbgs() << "into: " << *PrepareExecInst << '\n');
@ -353,8 +352,7 @@ bool SIOptimizeExecMasking::runOnMachineFunction(MachineFunction &MF) {
for (MachineInstr *OtherInst : OtherUseInsts) {
OtherInst->substituteRegister(CopyToExec, AMDGPU::EXEC,
AMDGPU::NoSubRegister, *TRI,
/*ClearIsRenamable=*/true);
AMDGPU::NoSubRegister, *TRI);
}
}

2
lib/Target/AMDGPU/VOPInstructions.td
View File

@ -81,8 +81,6 @@ class VOP3_Pseudo <string opName, VOPProfile P, list<dag> pattern = [],
let UseNamedOperandTable = 1;
let VOP3_OPSEL = isVop3OpSel;
let IsPacked = P.IsPacked;
// Avoid changing source registers in a way that violates constant bus read limitations.
let hasExtraSrcRegAllocReq = 1;
string Mnemonic = opName;
string AsmOperands = !if(isVop3OpSel,

1
lib/Target/ARM/ARM.td
View File

@ -1043,4 +1043,5 @@ def ARM : Target {
let AssemblyWriters = [ARMAsmWriter];
let AssemblyParsers = [ARMAsmParser];
let AssemblyParserVariants = [ARMAsmParserVariant];
let AllowRegisterRenaming = 1;
}

4
lib/Target/ARM/ARMBaseInstrInfo.cpp
View File

@ -1378,7 +1378,6 @@ void ARMBaseInstrInfo::expandMEMCPY(MachineBasicBlock::iterator MI) const {
MachineInstrBuilder LDM, STM;
if (isThumb1 || !MI->getOperand(1).isDead()) {
MachineOperand LDWb(MI->getOperand(1));
LDWb.setIsRenamable(false);
LDM = BuildMI(*BB, MI, dl, TII->get(isThumb2 ? ARM::t2LDMIA_UPD
: isThumb1 ? ARM::tLDMIA_UPD
: ARM::LDMIA_UPD))
@ -1389,7 +1388,6 @@ void ARMBaseInstrInfo::expandMEMCPY(MachineBasicBlock::iterator MI) const {
if (isThumb1 || !MI->getOperand(0).isDead()) {
MachineOperand STWb(MI->getOperand(0));
STWb.setIsRenamable(false);
STM = BuildMI(*BB, MI, dl, TII->get(isThumb2 ? ARM::t2STMIA_UPD
: isThumb1 ? ARM::tSTMIA_UPD
: ARM::STMIA_UPD))
@ -1399,11 +1397,9 @@ void ARMBaseInstrInfo::expandMEMCPY(MachineBasicBlock::iterator MI) const {
}
MachineOperand LDBase(MI->getOperand(3));
LDBase.setIsRenamable(false);
LDM.add(LDBase).add(predOps(ARMCC::AL));
MachineOperand STBase(MI->getOperand(2));
STBase.setIsRenamable(false);
STM.add(STBase).add(predOps(ARMCC::AL));
// Sort the scratch registers into ascending order.

3
lib/Target/ARM/ARMExpandPseudoInsts.cpp
View File

@ -608,7 +608,6 @@ void ARMExpandPseudo::ExpandVTBL(MachineBasicBlock::iterator &MBBI,
MIB.add(MI.getOperand(OpIdx++));
if (IsExt) {
MachineOperand VdSrc(MI.getOperand(OpIdx++));
VdSrc.setIsRenamable(false);
MIB.add(VdSrc);
}
@ -620,7 +619,6 @@ void ARMExpandPseudo::ExpandVTBL(MachineBasicBlock::iterator &MBBI,
// Copy the other source register operand.
MachineOperand VmSrc(MI.getOperand(OpIdx++));
VmSrc.setIsRenamable(false);
MIB.add(VmSrc);
// Copy the predicate operands.
@ -1470,7 +1468,6 @@ bool ARMExpandPseudo::ExpandMI(MachineBasicBlock &MBB,
// Copy the destination register.
MachineOperand Dst(MI.getOperand(OpIdx++));
Dst.setIsRenamable(false);
MIB.add(Dst);
// Copy the predicate operands.

2
lib/Target/ARM/ARMISelLowering.cpp
View File

@ -9196,8 +9196,6 @@ ARMTargetLowering::EmitInstrWithCustomInserter(MachineInstr &MI,
// Thumb1 post-indexed loads are really just single-register LDMs.
case ARM::tLDR_postidx: {
MachineOperand Def(MI.getOperand(1));
if (TargetRegisterInfo::isPhysicalRegister(Def.getReg()))
Def.setIsRenamable(false);
BuildMI(*BB, MI, dl, TII->get(ARM::tLDMIA_UPD))
.add(Def) // Rn_wb
.add(MI.getOperand(2)) // Rn

1
lib/Target/Hexagon/Hexagon.td
View File

@ -359,4 +359,5 @@ def Hexagon : Target {
let AssemblyParsers = [HexagonAsmParser];
let AssemblyParserVariants = [HexagonAsmParserVariant];
let AssemblyWriters = [HexagonAsmWriter];
let AllowRegisterRenaming = 1;
}

3
lib/Target/Hexagon/RDFCopy.cpp
View File

@ -101,7 +101,6 @@ NodeId CopyPropagation::getLocalReachingDef(RegisterRef RefRR,
bool CopyPropagation::run() {
scanBlock(&DFG.getMF().front());
MachineRegisterInfo &MRI = DFG.getMF().getRegInfo();
if (trace()) {
dbgs() << "Copies:\n";
@ -181,8 +180,6 @@ bool CopyPropagation::run() {
unsigned NewReg = MinPhysReg(SR);
Op.setReg(NewReg);
Op.setSubReg(0);
if (MRI.isReserved(NewReg))
Op.setIsRenamable(false);
DFG.unlinkUse(UA, false);
if (AtCopy != 0) {
UA.Addr->linkToDef(UA.Id, DFG.addr<DefNode*>(AtCopy));

1
lib/Target/Mips/Mips.td
View File

@ -242,4 +242,5 @@ def Mips : Target {
let InstructionSet = MipsInstrInfo;
let AssemblyParsers = [MipsAsmParser];
let AssemblyParserVariants = [MipsAsmParserVariant];
let AllowRegisterRenaming = 1;
}

1
lib/Target/PowerPC/PPC.td
View File

@ -465,4 +465,5 @@ def PPC : Target {
let AssemblyParsers = [PPCAsmParser];
let AssemblyParserVariants = [PPCAsmParserVariant];
let AllowRegisterRenaming = 1;
}

1
lib/Target/RISCV/RISCV.td
View File

@ -92,4 +92,5 @@ def RISCV : Target {
let InstructionSet = RISCVInstrInfo;
let AssemblyParsers = [RISCVAsmParser];
let AssemblyWriters = [RISCVAsmWriter];
let AllowRegisterRenaming = 1;
}

1
lib/Target/Sparc/Sparc.td
View File

@ -176,4 +176,5 @@ def Sparc : Target {
let InstructionSet = SparcInstrInfo;
let AssemblyParsers = [SparcAsmParser];
let AssemblyWriters = [SparcAsmWriter];
let AllowRegisterRenaming = 1;
}

1
lib/Target/SystemZ/SystemZ.td
View File

@ -75,4 +75,5 @@ def SystemZAsmParser : AsmParser {
def SystemZ : Target {
let InstructionSet = SystemZInstrInfo;
let AssemblyParsers = [SystemZAsmParser];
let AllowRegisterRenaming = 1;
}

1
lib/Target/X86/X86.td
View File

@ -1130,4 +1130,5 @@ def X86 : Target {
let InstructionSet = X86InstrInfo;
let AssemblyParserVariants = [ATTAsmParserVariant, IntelAsmParserVariant];
let AssemblyWriters = [ATTAsmWriter, IntelAsmWriter];
let AllowRegisterRenaming = 1;
}

3
lib/Target/X86/X86FloatingPoint.cpp
View File

@ -1383,7 +1383,6 @@ void FPS::handleCompareFP(MachineBasicBlock::iterator &I) {
// Change from the pseudo instruction to the concrete instruction.
MI.getOperand(0).setReg(getSTReg(Op1));
MI.getOperand(0).setIsRenamable(false);
MI.RemoveOperand(1);
MI.setDesc(TII->get(getConcreteOpcode(MI.getOpcode())));
@ -1411,7 +1410,6 @@ void FPS::handleCondMovFP(MachineBasicBlock::iterator &I) {
MI.RemoveOperand(0);
MI.RemoveOperand(1);
MI.getOperand(0).setReg(getSTReg(Op1));
MI.getOperand(0).setIsRenamable(false);
MI.setDesc(TII->get(getConcreteOpcode(MI.getOpcode())));
// If we kill the second operand, make sure to pop it from the stack.
@ -1628,7 +1626,6 @@ void FPS::handleSpecialFP(MachineBasicBlock::iterator &Inst) {
else
// Operand with a single register class constraint ("t" or "u").
Op.setReg(X86::ST0 + FPReg);
Op.setIsRenamable(false);
}
// Simulate the inline asm popping its inputs and pushing its outputs.

13
test/CodeGen/AMDGPU/postra-norename.mir Normal file
View File

@ -0,0 +1,13 @@
# RUN: llc -march=amdgcn -mcpu=gfx900 -run-pass postrapseudos %s -o - | FileCheck -check-prefix=GCN %s
# Check that post-RA expanded COPY doesn't have renamable operands
# since V_MOV_B32_e32 has hasExtraSrcRegAllocReq set.
# GCN-LABEL: name: test1
# GCN: $vgpr1 = V_MOV_B32_e32 $vgpr0, implicit $exec
name: test1
tracksRegLiveness: true
body: |
bb.0:
liveins: $vgpr0
renamable $vgpr1 = COPY renamable $vgpr0
...

3
utils/TableGen/CodeGenTarget.cpp
View File

@ -224,6 +224,9 @@ Record *CodeGenTarget::getInstructionSet() const {
return TargetRec->getValueAsDef("InstructionSet");
}
bool CodeGenTarget::getAllowRegisterRenaming() const {
return TargetRec->getValueAsInt("AllowRegisterRenaming");
}
/// getAsmParser - Return the AssemblyParser definition for this target.
///

5
utils/TableGen/CodeGenTarget.h
View File

@ -77,6 +77,11 @@ public:
///
Record *getInstructionSet() const;
/// getAllowRegisterRenaming - Return the AllowRegisterRenaming flag value for
/// this target.
///
bool getAllowRegisterRenaming() const;
/// getAsmParser - Return the AssemblyParser definition for this target.
///
Record *getAsmParser() const;

9
utils/TableGen/InstrInfoEmitter.cpp
View File

@ -480,6 +480,8 @@ void InstrInfoEmitter::emitRecord(const CodeGenInstruction &Inst, unsigned Num,
<< Inst.TheDef->getValueAsInt("Size") << ",\t"
<< SchedModels.getSchedClassIdx(Inst) << ",\t0";
CodeGenTarget &Target = CDP.getTargetInfo();
// Emit all of the target independent flags...
if (Inst.isPseudo) OS << "|(1ULL<<MCID::Pseudo)";
if (Inst.isReturn) OS << "|(1ULL<<MCID::Return)";
@ -508,8 +510,10 @@ void InstrInfoEmitter::emitRecord(const CodeGenInstruction &Inst, unsigned Num,
if (Inst.Operands.isVariadic)OS << "|(1ULL<<MCID::Variadic)";
if (Inst.hasSideEffects) OS << "|(1ULL<<MCID::UnmodeledSideEffects)";
if (Inst.isAsCheapAsAMove) OS << "|(1ULL<<MCID::CheapAsAMove)";
if (Inst.hasExtraSrcRegAllocReq) OS << "|(1ULL<<MCID::ExtraSrcRegAllocReq)";
if (Inst.hasExtraDefRegAllocReq) OS << "|(1ULL<<MCID::ExtraDefRegAllocReq)";
if (!Target.getAllowRegisterRenaming() || Inst.hasExtraSrcRegAllocReq)
OS << "|(1ULL<<MCID::ExtraSrcRegAllocReq)";
if (!Target.getAllowRegisterRenaming() || Inst.hasExtraDefRegAllocReq)
OS << "|(1ULL<<MCID::ExtraDefRegAllocReq)";
if (Inst.isRegSequence) OS << "|(1ULL<<MCID::RegSequence)";
if (Inst.isExtractSubreg) OS << "|(1ULL<<MCID::ExtractSubreg)";
if (Inst.isInsertSubreg) OS << "|(1ULL<<MCID::InsertSubreg)";
@ -550,7 +554,6 @@ void InstrInfoEmitter::emitRecord(const CodeGenInstruction &Inst, unsigned Num,
else
OS << "OperandInfo" << OpInfo.find(OperandInfo)->second;
CodeGenTarget &Target = CDP.getTargetInfo();
if (Inst.HasComplexDeprecationPredicate)
// Emit a function pointer to the complex predicate method.
OS << ", -1 "