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Teaching MBlaze backend how to reverse branch conditions.
llvm-svn: 120707
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@ -234,6 +234,36 @@ unsigned MBlazeInstrInfo::RemoveBranch(MachineBasicBlock &MBB) const {
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return 2;
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}
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bool MBlazeInstrInfo::ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const {
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assert(Cond.size() == 2 && "Invalid MBlaze branch opcode!");
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switch (Cond[0].getImm()) {
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default: return true;
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case MBlaze::BEQ: Cond[0].setImm(MBlaze::BNE); return false;
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case MBlaze::BNE: Cond[0].setImm(MBlaze::BEQ); return false;
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case MBlaze::BGT: Cond[0].setImm(MBlaze::BLE); return false;
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case MBlaze::BGE: Cond[0].setImm(MBlaze::BLT); return false;
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case MBlaze::BLT: Cond[0].setImm(MBlaze::BGE); return false;
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case MBlaze::BLE: Cond[0].setImm(MBlaze::BGT); return false;
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case MBlaze::BEQI: Cond[0].setImm(MBlaze::BNEI); return false;
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case MBlaze::BNEI: Cond[0].setImm(MBlaze::BEQI); return false;
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case MBlaze::BGTI: Cond[0].setImm(MBlaze::BLEI); return false;
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case MBlaze::BGEI: Cond[0].setImm(MBlaze::BLTI); return false;
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case MBlaze::BLTI: Cond[0].setImm(MBlaze::BGEI); return false;
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case MBlaze::BLEI: Cond[0].setImm(MBlaze::BGTI); return false;
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case MBlaze::BEQD: Cond[0].setImm(MBlaze::BNED); return false;
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case MBlaze::BNED: Cond[0].setImm(MBlaze::BEQD); return false;
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case MBlaze::BGTD: Cond[0].setImm(MBlaze::BLED); return false;
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case MBlaze::BGED: Cond[0].setImm(MBlaze::BLTD); return false;
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case MBlaze::BLTD: Cond[0].setImm(MBlaze::BGED); return false;
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case MBlaze::BLED: Cond[0].setImm(MBlaze::BGTD); return false;
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case MBlaze::BEQID: Cond[0].setImm(MBlaze::BNEID); return false;
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case MBlaze::BNEID: Cond[0].setImm(MBlaze::BEQID); return false;
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case MBlaze::BGTID: Cond[0].setImm(MBlaze::BLEID); return false;
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case MBlaze::BGEID: Cond[0].setImm(MBlaze::BLTID); return false;
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case MBlaze::BLTID: Cond[0].setImm(MBlaze::BGEID); return false;
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case MBlaze::BLEID: Cond[0].setImm(MBlaze::BGTID); return false;
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}
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}
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/// getGlobalBaseReg - Return a virtual register initialized with the
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/// the global base register value. Output instructions required to
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@ -257,6 +257,11 @@ public:
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const SmallVectorImpl<MachineOperand> &Cond,
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DebugLoc DL) const;
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virtual unsigned RemoveBranch(MachineBasicBlock &MBB) const;
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virtual bool ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond)
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const;
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virtual void copyPhysReg(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator I, DebugLoc DL,
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unsigned DestReg, unsigned SrcReg,
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