mirror of
https://github.com/RPCS3/llvm-mirror.git
synced 2024-10-19 11:02:59 +02:00
[PowerPC] Add options for PPC to enable/disable using non-volatile CR
An option is added for PowerPC to disable use of non-volatile CR register fields and avoid CR spilling in the prologue. Differential Revision: https://reviews.llvm.org/D69835
This commit is contained in:
parent
5b7c2c7a93
commit
09d6419647
@ -10,10 +10,17 @@
|
||||
#include "llvm/ADT/Twine.h"
|
||||
#include "llvm/IR/DataLayout.h"
|
||||
#include "llvm/MC/MCContext.h"
|
||||
#include "llvm/Support/CommandLine.h"
|
||||
|
||||
using namespace llvm;
|
||||
static cl::opt<bool> PPCDisableNonVolatileCR(
|
||||
"ppc-disable-non-volatile-cr",
|
||||
cl::desc("Disable the use of non-volatile CR register fields"),
|
||||
cl::init(false), cl::Hidden);
|
||||
|
||||
void PPCFunctionInfo::anchor() {}
|
||||
PPCFunctionInfo::PPCFunctionInfo(MachineFunction &MF)
|
||||
: DisableNonVolatileCR(PPCDisableNonVolatileCR), MF(MF) {}
|
||||
|
||||
MCSymbol *PPCFunctionInfo::getPICOffsetSymbol() const {
|
||||
const DataLayout &DL = MF.getDataLayout();
|
||||
|
@ -65,6 +65,10 @@ class PPCFunctionInfo : public MachineFunctionInfo {
|
||||
/// SpillsCR - Indicates whether CR is spilled in the current function.
|
||||
bool SpillsCR = false;
|
||||
|
||||
/// DisableNonVolatileCR - Indicates whether non-volatile CR fields would be
|
||||
/// disabled.
|
||||
bool DisableNonVolatileCR = false;
|
||||
|
||||
/// Indicates whether VRSAVE is spilled in the current function.
|
||||
bool SpillsVRSAVE = false;
|
||||
|
||||
@ -129,7 +133,7 @@ class PPCFunctionInfo : public MachineFunctionInfo {
|
||||
std::vector<std::pair<unsigned, ISD::ArgFlagsTy>> LiveInAttrs;
|
||||
|
||||
public:
|
||||
explicit PPCFunctionInfo(MachineFunction &MF) : MF(MF) {}
|
||||
explicit PPCFunctionInfo(MachineFunction &MF);
|
||||
|
||||
int getFramePointerSaveIndex() const { return FramePointerSaveIndex; }
|
||||
void setFramePointerSaveIndex(int Idx) { FramePointerSaveIndex = Idx; }
|
||||
@ -175,6 +179,9 @@ public:
|
||||
void setSpillsCR() { SpillsCR = true; }
|
||||
bool isCRSpilled() const { return SpillsCR; }
|
||||
|
||||
void setDisableNonVolatileCR() { DisableNonVolatileCR = true; }
|
||||
bool isNonVolatileCRDisabled() const { return DisableNonVolatileCR; }
|
||||
|
||||
void setSpillsVRSAVE() { SpillsVRSAVE = true; }
|
||||
bool isVRSAVESpilled() const { return SpillsVRSAVE; }
|
||||
|
||||
|
@ -363,11 +363,23 @@ def CRBITRC : RegisterClass<"PPC", [i1], 32,
|
||||
CR1LT, CR1GT, CR1EQ, CR1UN,
|
||||
CR0LT, CR0GT, CR0EQ, CR0UN)> {
|
||||
let Size = 32;
|
||||
let AltOrders = [(sub CRBITRC, CR2LT, CR2GT, CR2EQ, CR2UN, CR3LT, CR3GT,
|
||||
CR3EQ, CR3UN, CR4LT, CR4GT, CR4EQ, CR4UN)];
|
||||
let AltOrderSelect = [{
|
||||
return MF.getSubtarget<PPCSubtarget>().isELFv2ABI() &&
|
||||
MF.getInfo<PPCFunctionInfo>()->isNonVolatileCRDisabled();
|
||||
}];
|
||||
}
|
||||
|
||||
def CRRC : RegisterClass<"PPC", [i32], 32, (add CR0, CR1, CR5, CR6,
|
||||
CR7, CR2, CR3, CR4)>;
|
||||
|
||||
def CRRC : RegisterClass<"PPC", [i32], 32,
|
||||
(add CR0, CR1, CR5, CR6,
|
||||
CR7, CR2, CR3, CR4)> {
|
||||
let AltOrders = [(sub CRRC, CR2, CR3, CR4)];
|
||||
let AltOrderSelect = [{
|
||||
return MF.getSubtarget<PPCSubtarget>().isELFv2ABI() &&
|
||||
MF.getInfo<PPCFunctionInfo>()->isNonVolatileCRDisabled();
|
||||
}];
|
||||
}
|
||||
// The CTR registers are not allocatable because they're used by the
|
||||
// decrement-and-branch instructions, and thus need to stay live across
|
||||
// multiple basic blocks.
|
||||
|
47
test/CodeGen/PowerPC/ppc-disable-non-volatile-cr.ll
Normal file
47
test/CodeGen/PowerPC/ppc-disable-non-volatile-cr.ll
Normal file
@ -0,0 +1,47 @@
|
||||
; Note: Test option to disable use of non-volatile CR to avoid CR spilling in prologue.
|
||||
; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -ppc-disable-non-volatile-cr\
|
||||
; RUN: -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr < %s | FileCheck --check-prefix=CHECK-DISABLE %s
|
||||
; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu\
|
||||
; RUN: -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr < %s | FileCheck --check-prefix=CHECK-ENABLE %s
|
||||
|
||||
; Function Attrs: nounwind
|
||||
define dso_local signext i32 @DisableNonVolatileCR(i32 signext %a, i32 signext %b) {
|
||||
; CHECK-DISABLE-LABEL: DisableNonVolatileCR:
|
||||
; CHECK-DISABLE: # %bb.0: # %entry
|
||||
; CHECK-DISABLE-NOT: mfocrf [[REG1:r[0-9]+]]
|
||||
; CHECK-DISABLE-NOT: stw [[REG1]]
|
||||
; CHECK-DISABLE: stdu r1
|
||||
; CHECK-DISABLE-DAG: mfocrf [[REG2:r[0-9]+]]
|
||||
; CHECK-DISABLE-DAG: stw [[REG2]]
|
||||
; CHECK-DISABLE: # %bb.1: # %if.then
|
||||
;
|
||||
; CHECK-ENABLE-LABEL: DisableNonVolatileCR:
|
||||
; CHECK-ENABLE: # %bb.0: # %entry
|
||||
; CHECK-ENABLE-DAG: mfocrf [[REG1:r[0-9]+]]
|
||||
; CHECK-ENABLE-DAG: stw [[REG1]]
|
||||
; CHECK-ENABLE: stdu r1
|
||||
; CHECK-ENABLE-NOT: mfocrf [[REG2:r[0-9]+]]
|
||||
; CHECK-ENABLE-NOT: stw [[REG2]]
|
||||
; CHECK-ENABLE: # %bb.1: # %if.then
|
||||
|
||||
entry:
|
||||
%cmp = icmp slt i32 %a, %b
|
||||
br i1 %cmp, label %if.then, label %if.else
|
||||
|
||||
if.then: ; preds = %entry
|
||||
tail call void bitcast (void (...)* @fa to void ()*)()
|
||||
br label %if.end
|
||||
|
||||
if.else: ; preds = %entry
|
||||
tail call void bitcast (void (...)* @fb to void ()*)()
|
||||
br label %if.end
|
||||
|
||||
if.end: ; preds = %if.else, %if.then
|
||||
%conv = zext i1 %cmp to i32
|
||||
%call = tail call signext i32 @callee(i32 signext %conv)
|
||||
ret i32 %call
|
||||
}
|
||||
|
||||
declare void @fa(...)
|
||||
declare void @fb(...)
|
||||
declare signext i32 @callee(i32 signext)
|
Loading…
Reference in New Issue
Block a user