mirror of
https://github.com/RPCS3/llvm-mirror.git
synced 2024-11-26 04:32:44 +01:00
[CodeGen] Increase the size of a SmallVector
The SmallVector reserve() call in MachineInstrExpressionTrait::getHashValue accounted for over 3% of all calls to malloc() when I compiled a bunch of graphics shaders for the AMDGPU target. Its initial size was only enough for machine instructions with up to 7 operands, but for AMDGPU 8 and 10 operands are very common. Here's a histogram of number of operands for each call to getHashValue, gathered from the same collection of shaders: 1 13503 2 254273 3 135781 4 422508 5 614997 6 194953 7 287248 8 1517255 9 31218 10 1191269 11 70731 12 24 13 77 15 84 17 4692 27 16 33 705 49 6 Typical instructions with 8 and 10 operands are floating point arithmetic and multiply-accumulate instructions like: %83:vgpr_32 = V_MUL_F32_e64 0, killed %82:vgpr_32, 0, killed %81:vgpr_32, 0, 0, implicit $exec %330:vgpr_32 = V_MAC_F32_e64 0, killed %327:vgpr_32, 0, killed %329:sgpr_32, 0, %328:vgpr_32(tied-def 0), 0, 0, implicit $exec Differential Revision: https://reviews.llvm.org/D70301
This commit is contained in:
parent
8d45c0c2df
commit
09df29855e
@ -1977,7 +1977,7 @@ void MachineInstr::setPhysRegsDeadExcept(ArrayRef<Register> UsedRegs,
|
||||
unsigned
|
||||
MachineInstrExpressionTrait::getHashValue(const MachineInstr* const &MI) {
|
||||
// Build up a buffer of hash code components.
|
||||
SmallVector<size_t, 8> HashComponents;
|
||||
SmallVector<size_t, 16> HashComponents;
|
||||
HashComponents.reserve(MI->getNumOperands() + 1);
|
||||
HashComponents.push_back(MI->getOpcode());
|
||||
for (const MachineOperand &MO : MI->operands()) {
|
||||
|
Loading…
Reference in New Issue
Block a user