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Add a build_vector node
llvm-svn: 26895
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@ -307,7 +307,7 @@ def extld : SDNode<"ISD::EXTLOAD" , SDTExtLoad, [SDNPHasChain]>;
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def truncst : SDNode<"ISD::TRUNCSTORE" , SDTTruncStore, [SDNPHasChain]>;
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def truncst : SDNode<"ISD::TRUNCSTORE" , SDTTruncStore, [SDNPHasChain]>;
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def vector_shuffle : SDNode<"ISD::VECTOR_SHUFFLE", SDTVecShuffle, []>;
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def vector_shuffle : SDNode<"ISD::VECTOR_SHUFFLE", SDTVecShuffle, []>;
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def build_vector : SDNode<"ISD::BUILD_VECTOR", SDTypeProfile<1, 0, []>, []>;
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//===----------------------------------------------------------------------===//
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//===----------------------------------------------------------------------===//
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// Selection DAG Condition Codes
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// Selection DAG Condition Codes
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@ -255,6 +255,7 @@ X86TargetLowering::X86TargetLowering(TargetMachine &TM)
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setOperationAction(ISD::SUB , (MVT::ValueType)VT, Expand);
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setOperationAction(ISD::SUB , (MVT::ValueType)VT, Expand);
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setOperationAction(ISD::MUL , (MVT::ValueType)VT, Expand);
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setOperationAction(ISD::MUL , (MVT::ValueType)VT, Expand);
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setOperationAction(ISD::LOAD, (MVT::ValueType)VT, Expand);
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setOperationAction(ISD::LOAD, (MVT::ValueType)VT, Expand);
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setOperationAction(ISD::VECTOR_SHUFFLE, (MVT::ValueType)VT, Expand);
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}
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}
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if (TM.getSubtarget<X86Subtarget>().hasMMX()) {
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if (TM.getSubtarget<X86Subtarget>().hasMMX()) {
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