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[AArch64][SVE] Add SVE2 mla unpredicated intrinsics.
Summary: Add intrinsics for the MLA unpredicated sve2 instructions: - smlalb, smlalt, umlalb, umlalt, smlslb, smlslt, umlslb, umlslt - sqdmlalb, sqdmlalt, sqdmlslb, sqdmlslt - sqdmlalbt, sqdmlslbt Reviewers: efriedma, sdesmalen, cameron.mcinally, c-rhodes, rengolin, kmclaughlin Subscribers: tschuett, kristof.beyls, hiraditya, rkruppe, psnobl, llvm-commits, amehsan Tags: #llvm Differential Revision: https://reviews.llvm.org/D73746
This commit is contained in:
Danilo Carvalho Grael
parent
64c9c18eba
commit
09eed610f2
@ -1816,6 +1816,7 @@ def int_aarch64_sve_sqshrunt : SVE2_2VectorArg_Imm_Narrowing_Intrinsic;
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def int_aarch64_sve_sqrshrunb : SVE2_1VectorArg_Imm_Narrowing_Intrinsic;
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def int_aarch64_sve_sqrshrunt : SVE2_2VectorArg_Imm_Narrowing_Intrinsic;
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// SVE2 MLA LANE.
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def int_aarch64_sve_smlalb_lane : SVE2_3VectorArg_Indexed_Intrinsic;
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def int_aarch64_sve_smlalt_lane : SVE2_3VectorArg_Indexed_Intrinsic;
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def int_aarch64_sve_umlalb_lane : SVE2_3VectorArg_Indexed_Intrinsic;
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@ -1829,4 +1830,22 @@ def int_aarch64_sve_sqdmlalt_lane : SVE2_3VectorArg_Indexed_Intrinsic;
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def int_aarch64_sve_sqdmlslb_lane : SVE2_3VectorArg_Indexed_Intrinsic;
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def int_aarch64_sve_sqdmlslt_lane : SVE2_3VectorArg_Indexed_Intrinsic;
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// SVE2 MLA Unpredicated.
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def int_aarch64_sve_smlalb : SVE2_3VectorArg_Long_Intrinsic;
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def int_aarch64_sve_smlalt : SVE2_3VectorArg_Long_Intrinsic;
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def int_aarch64_sve_umlalb : SVE2_3VectorArg_Long_Intrinsic;
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def int_aarch64_sve_umlalt : SVE2_3VectorArg_Long_Intrinsic;
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def int_aarch64_sve_smlslb : SVE2_3VectorArg_Long_Intrinsic;
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def int_aarch64_sve_smlslt : SVE2_3VectorArg_Long_Intrinsic;
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def int_aarch64_sve_umlslb : SVE2_3VectorArg_Long_Intrinsic;
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def int_aarch64_sve_umlslt : SVE2_3VectorArg_Long_Intrinsic;
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def int_aarch64_sve_sqdmlalb : SVE2_3VectorArg_Long_Intrinsic;
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def int_aarch64_sve_sqdmlalt : SVE2_3VectorArg_Long_Intrinsic;
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def int_aarch64_sve_sqdmlslb : SVE2_3VectorArg_Long_Intrinsic;
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def int_aarch64_sve_sqdmlslt : SVE2_3VectorArg_Long_Intrinsic;
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def int_aarch64_sve_sqdmlalbt : SVE2_3VectorArg_Long_Intrinsic;
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def int_aarch64_sve_sqdmlslbt : SVE2_3VectorArg_Long_Intrinsic;
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}
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@ -1477,14 +1477,14 @@ let Predicates = [HasSVE2] in {
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defm UMLSLT_ZZZI : sve2_int_mla_long_by_indexed_elem<0b1111, "umlslt", int_aarch64_sve_umlslt_lane>;
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// SVE2 integer multiply-add long (vectors, unpredicated)
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defm SMLALB_ZZZ : sve2_int_mla_long<0b10000, "smlalb">;
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defm SMLALT_ZZZ : sve2_int_mla_long<0b10001, "smlalt">;
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defm UMLALB_ZZZ : sve2_int_mla_long<0b10010, "umlalb">;
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defm UMLALT_ZZZ : sve2_int_mla_long<0b10011, "umlalt">;
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defm SMLSLB_ZZZ : sve2_int_mla_long<0b10100, "smlslb">;
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defm SMLSLT_ZZZ : sve2_int_mla_long<0b10101, "smlslt">;
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defm UMLSLB_ZZZ : sve2_int_mla_long<0b10110, "umlslb">;
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defm UMLSLT_ZZZ : sve2_int_mla_long<0b10111, "umlslt">;
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defm SMLALB_ZZZ : sve2_int_mla_long<0b10000, "smlalb", int_aarch64_sve_smlalb>;
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defm SMLALT_ZZZ : sve2_int_mla_long<0b10001, "smlalt", int_aarch64_sve_smlalt>;
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defm UMLALB_ZZZ : sve2_int_mla_long<0b10010, "umlalb", int_aarch64_sve_umlalb>;
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defm UMLALT_ZZZ : sve2_int_mla_long<0b10011, "umlalt", int_aarch64_sve_umlalt>;
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defm SMLSLB_ZZZ : sve2_int_mla_long<0b10100, "smlslb", int_aarch64_sve_smlslb>;
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defm SMLSLT_ZZZ : sve2_int_mla_long<0b10101, "smlslt", int_aarch64_sve_smlslt>;
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defm UMLSLB_ZZZ : sve2_int_mla_long<0b10110, "umlslb", int_aarch64_sve_umlslb>;
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defm UMLSLT_ZZZ : sve2_int_mla_long<0b10111, "umlslt", int_aarch64_sve_umlslt>;
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// SVE2 saturating multiply-add long (indexed)
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defm SQDMLALB_ZZZI : sve2_int_mla_long_by_indexed_elem<0b0100, "sqdmlalb", int_aarch64_sve_sqdmlalb_lane>;
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@ -1493,14 +1493,14 @@ let Predicates = [HasSVE2] in {
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defm SQDMLSLT_ZZZI : sve2_int_mla_long_by_indexed_elem<0b0111, "sqdmlslt", int_aarch64_sve_sqdmlslt_lane>;
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// SVE2 saturating multiply-add long (vectors, unpredicated)
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defm SQDMLALB_ZZZ : sve2_int_mla_long<0b11000, "sqdmlalb">;
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defm SQDMLALT_ZZZ : sve2_int_mla_long<0b11001, "sqdmlalt">;
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defm SQDMLSLB_ZZZ : sve2_int_mla_long<0b11010, "sqdmlslb">;
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defm SQDMLSLT_ZZZ : sve2_int_mla_long<0b11011, "sqdmlslt">;
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defm SQDMLALB_ZZZ : sve2_int_mla_long<0b11000, "sqdmlalb", int_aarch64_sve_sqdmlalb>;
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defm SQDMLALT_ZZZ : sve2_int_mla_long<0b11001, "sqdmlalt", int_aarch64_sve_sqdmlalt>;
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defm SQDMLSLB_ZZZ : sve2_int_mla_long<0b11010, "sqdmlslb", int_aarch64_sve_sqdmlslb>;
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defm SQDMLSLT_ZZZ : sve2_int_mla_long<0b11011, "sqdmlslt", int_aarch64_sve_sqdmlslt>;
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// SVE2 saturating multiply-add interleaved long
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defm SQDMLALBT_ZZZ : sve2_int_mla_long<0b00010, "sqdmlalbt">;
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defm SQDMLSLBT_ZZZ : sve2_int_mla_long<0b00011, "sqdmlslbt">;
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defm SQDMLALBT_ZZZ : sve2_int_mla_long<0b00010, "sqdmlalbt", int_aarch64_sve_sqdmlalbt>;
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defm SQDMLSLBT_ZZZ : sve2_int_mla_long<0b00011, "sqdmlslbt", int_aarch64_sve_sqdmlslbt>;
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// SVE2 integer halving add/subtract (predicated)
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defm SHADD_ZPmZ : sve2_int_arith_pred<0b100000, "shadd", int_aarch64_sve_shadd>;
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@ -2352,10 +2352,14 @@ multiclass sve2_int_mla<bit S, string asm, SDPatternOperator op> {
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def : SVE_3_Op_Pat<nxv2i64, op, nxv2i64, nxv2i64, nxv2i64, !cast<Instruction>(NAME # _D)>;
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}
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multiclass sve2_int_mla_long<bits<5> opc, string asm> {
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multiclass sve2_int_mla_long<bits<5> opc, string asm, SDPatternOperator op> {
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def _H : sve2_int_mla<0b01, opc, asm, ZPR16, ZPR8>;
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def _S : sve2_int_mla<0b10, opc, asm, ZPR32, ZPR16>;
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def _D : sve2_int_mla<0b11, opc, asm, ZPR64, ZPR32>;
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def : SVE_3_Op_Pat<nxv8i16, op, nxv8i16, nxv16i8, nxv16i8, !cast<Instruction>(NAME # _H)>;
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def : SVE_3_Op_Pat<nxv4i32, op, nxv4i32, nxv8i16, nxv8i16, !cast<Instruction>(NAME # _S)>;
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def : SVE_3_Op_Pat<nxv2i64, op, nxv2i64, nxv4i32, nxv4i32, !cast<Instruction>(NAME # _D)>;
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}
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//===----------------------------------------------------------------------===//
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590
test/CodeGen/AArch64/sve2-mla-unpredicated.ll
Normal file
590
test/CodeGen/AArch64/sve2-mla-unpredicated.ll
Normal file
@ -0,0 +1,590 @@
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; RUN: llc -mtriple=aarch64-linux-gnu -mattr=+sve2 < %s | FileCheck %s
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;
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; SMLALB
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;
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define <vscale x 8 x i16> @smlalb_i16(<vscale x 8 x i16> %a,
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<vscale x 16 x i8> %b,
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<vscale x 16 x i8> %c) {
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; CHECK-LABEL: smlalb_i16
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; CHECK: smlalb z0.h, z1.b, z2.b
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; CHECK-NEXT: ret
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%res = call <vscale x 8 x i16> @llvm.aarch64.sve.smlalb.nxv8i16(<vscale x 8 x i16> %a,
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<vscale x 16 x i8> %b,
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<vscale x 16 x i8> %c)
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ret <vscale x 8 x i16> %res
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}
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define <vscale x 4 x i32> @smlalb_i32(<vscale x 4 x i32> %a,
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<vscale x 8 x i16> %b,
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<vscale x 8 x i16> %c) {
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; CHECK-LABEL: smlalb_i32
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; CHECK: smlalb z0.s, z1.h, z2.h
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; CHECK-NEXT: ret
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%res = call <vscale x 4 x i32> @llvm.aarch64.sve.smlalb.nxv4i32(<vscale x 4 x i32> %a,
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<vscale x 8 x i16> %b,
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<vscale x 8 x i16> %c)
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ret <vscale x 4 x i32> %res
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}
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define <vscale x 2 x i64> @smlalb_i64(<vscale x 2 x i64> %a,
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<vscale x 4 x i32> %b,
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<vscale x 4 x i32> %c) {
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; CHECK-LABEL: smlalb_i64
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; CHECK: smlalb z0.d, z1.s, z2.s
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; CHECK-NEXT: ret
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%res = call <vscale x 2 x i64> @llvm.aarch64.sve.smlalb.nxv2i64(<vscale x 2 x i64> %a,
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<vscale x 4 x i32> %b,
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<vscale x 4 x i32> %c)
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ret <vscale x 2 x i64> %res
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}
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;
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; SMLALT
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;
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define <vscale x 8 x i16> @smlalt_i16(<vscale x 8 x i16> %a,
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<vscale x 16 x i8> %b,
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<vscale x 16 x i8> %c) {
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; CHECK-LABEL: smlalt_i16
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; CHECK: smlalt z0.h, z1.b, z2.b
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; CHECK-NEXT: ret
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%res = call <vscale x 8 x i16> @llvm.aarch64.sve.smlalt.nxv8i16(<vscale x 8 x i16> %a,
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<vscale x 16 x i8> %b,
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<vscale x 16 x i8> %c)
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ret <vscale x 8 x i16> %res
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}
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define <vscale x 4 x i32> @smlalt_i32(<vscale x 4 x i32> %a,
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<vscale x 8 x i16> %b,
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<vscale x 8 x i16> %c) {
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; CHECK-LABEL: smlalt_i32
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; CHECK: smlalt z0.s, z1.h, z2.h
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; CHECK-NEXT: ret
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%res = call <vscale x 4 x i32> @llvm.aarch64.sve.smlalt.nxv4i32(<vscale x 4 x i32> %a,
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<vscale x 8 x i16> %b,
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<vscale x 8 x i16> %c)
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ret <vscale x 4 x i32> %res
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}
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define <vscale x 2 x i64> @smlalt_i64(<vscale x 2 x i64> %a,
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<vscale x 4 x i32> %b,
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<vscale x 4 x i32> %c) {
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; CHECK-LABEL: smlalt_i64
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; CHECK: smlalt z0.d, z1.s, z2.s
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; CHECK-NEXT: ret
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%res = call <vscale x 2 x i64> @llvm.aarch64.sve.smlalt.nxv2i64(<vscale x 2 x i64> %a,
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<vscale x 4 x i32> %b,
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<vscale x 4 x i32> %c)
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ret <vscale x 2 x i64> %res
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}
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;
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; UMLALB
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;
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define <vscale x 8 x i16> @umlalb_i16(<vscale x 8 x i16> %a,
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<vscale x 16 x i8> %b,
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<vscale x 16 x i8> %c) {
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; CHECK-LABEL: umlalb_i16
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; CHECK: umlalb z0.h, z1.b, z2.b
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; CHECK-NEXT: ret
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%res = call <vscale x 8 x i16> @llvm.aarch64.sve.umlalb.nxv8i16(<vscale x 8 x i16> %a,
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<vscale x 16 x i8> %b,
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<vscale x 16 x i8> %c)
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ret <vscale x 8 x i16> %res
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}
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define <vscale x 4 x i32> @umlalb_i32(<vscale x 4 x i32> %a,
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<vscale x 8 x i16> %b,
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<vscale x 8 x i16> %c) {
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; CHECK-LABEL: umlalb_i32
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; CHECK: umlalb z0.s, z1.h, z2.h
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; CHECK-NEXT: ret
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%res = call <vscale x 4 x i32> @llvm.aarch64.sve.umlalb.nxv4i32(<vscale x 4 x i32> %a,
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<vscale x 8 x i16> %b,
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<vscale x 8 x i16> %c)
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ret <vscale x 4 x i32> %res
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}
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define <vscale x 2 x i64> @umlalb_i64(<vscale x 2 x i64> %a,
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<vscale x 4 x i32> %b,
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<vscale x 4 x i32> %c) {
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; CHECK-LABEL: umlalb_i64
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; CHECK: umlalb z0.d, z1.s, z2.s
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; CHECK-NEXT: ret
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%res = call <vscale x 2 x i64> @llvm.aarch64.sve.umlalb.nxv2i64(<vscale x 2 x i64> %a,
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<vscale x 4 x i32> %b,
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<vscale x 4 x i32> %c)
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ret <vscale x 2 x i64> %res
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}
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;
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; UMLALT
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;
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define <vscale x 8 x i16> @umlalt_i16(<vscale x 8 x i16> %a,
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<vscale x 16 x i8> %b,
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<vscale x 16 x i8> %c) {
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; CHECK-LABEL: umlalt_i16
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; CHECK: umlalt z0.h, z1.b, z2.b
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; CHECK-NEXT: ret
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%res = call <vscale x 8 x i16> @llvm.aarch64.sve.umlalt.nxv8i16(<vscale x 8 x i16> %a,
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<vscale x 16 x i8> %b,
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<vscale x 16 x i8> %c)
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ret <vscale x 8 x i16> %res
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}
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define <vscale x 4 x i32> @umlalt_i32(<vscale x 4 x i32> %a,
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<vscale x 8 x i16> %b,
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<vscale x 8 x i16> %c) {
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; CHECK-LABEL: umlalt_i32
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; CHECK: umlalt z0.s, z1.h, z2.h
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; CHECK-NEXT: ret
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%res = call <vscale x 4 x i32> @llvm.aarch64.sve.umlalt.nxv4i32(<vscale x 4 x i32> %a,
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<vscale x 8 x i16> %b,
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<vscale x 8 x i16> %c)
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ret <vscale x 4 x i32> %res
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}
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define <vscale x 2 x i64> @umlalt_i64(<vscale x 2 x i64> %a,
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<vscale x 4 x i32> %b,
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<vscale x 4 x i32> %c) {
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; CHECK-LABEL: umlalt_i64
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; CHECK: umlalt z0.d, z1.s, z2.s
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; CHECK-NEXT: ret
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%res = call <vscale x 2 x i64> @llvm.aarch64.sve.umlalt.nxv2i64(<vscale x 2 x i64> %a,
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<vscale x 4 x i32> %b,
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<vscale x 4 x i32> %c)
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ret <vscale x 2 x i64> %res
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}
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;
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; SMLSLB
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;
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define <vscale x 8 x i16> @smlslb_i16(<vscale x 8 x i16> %a,
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<vscale x 16 x i8> %b,
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<vscale x 16 x i8> %c) {
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; CHECK-LABEL: smlslb_i16
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; CHECK: smlslb z0.h, z1.b, z2.b
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; CHECK-NEXT: ret
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%res = call <vscale x 8 x i16> @llvm.aarch64.sve.smlslb.nxv8i16(<vscale x 8 x i16> %a,
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<vscale x 16 x i8> %b,
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<vscale x 16 x i8> %c)
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ret <vscale x 8 x i16> %res
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}
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define <vscale x 4 x i32> @smlslb_i32(<vscale x 4 x i32> %a,
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<vscale x 8 x i16> %b,
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<vscale x 8 x i16> %c) {
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; CHECK-LABEL: smlslb_i32
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; CHECK: smlslb z0.s, z1.h, z2.h
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; CHECK-NEXT: ret
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%res = call <vscale x 4 x i32> @llvm.aarch64.sve.smlslb.nxv4i32(<vscale x 4 x i32> %a,
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<vscale x 8 x i16> %b,
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<vscale x 8 x i16> %c)
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ret <vscale x 4 x i32> %res
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}
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define <vscale x 2 x i64> @smlslb_i64(<vscale x 2 x i64> %a,
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<vscale x 4 x i32> %b,
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<vscale x 4 x i32> %c) {
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; CHECK-LABEL: smlslb_i64
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; CHECK: smlslb z0.d, z1.s, z2.s
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; CHECK-NEXT: ret
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%res = call <vscale x 2 x i64> @llvm.aarch64.sve.smlslb.nxv2i64(<vscale x 2 x i64> %a,
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<vscale x 4 x i32> %b,
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<vscale x 4 x i32> %c)
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||||
ret <vscale x 2 x i64> %res
|
||||
}
|
||||
|
||||
;
|
||||
; SMLSLT
|
||||
;
|
||||
define <vscale x 8 x i16> @smlslt_i16(<vscale x 8 x i16> %a,
|
||||
<vscale x 16 x i8> %b,
|
||||
<vscale x 16 x i8> %c) {
|
||||
; CHECK-LABEL: smlslt_i16
|
||||
; CHECK: smlslt z0.h, z1.b, z2.b
|
||||
; CHECK-NEXT: ret
|
||||
%res = call <vscale x 8 x i16> @llvm.aarch64.sve.smlslt.nxv8i16(<vscale x 8 x i16> %a,
|
||||
<vscale x 16 x i8> %b,
|
||||
<vscale x 16 x i8> %c)
|
||||
ret <vscale x 8 x i16> %res
|
||||
}
|
||||
|
||||
define <vscale x 4 x i32> @smlslt_i32(<vscale x 4 x i32> %a,
|
||||
<vscale x 8 x i16> %b,
|
||||
<vscale x 8 x i16> %c) {
|
||||
; CHECK-LABEL: smlslt_i32
|
||||
; CHECK: smlslt z0.s, z1.h, z2.h
|
||||
; CHECK-NEXT: ret
|
||||
%res = call <vscale x 4 x i32> @llvm.aarch64.sve.smlslt.nxv4i32(<vscale x 4 x i32> %a,
|
||||
<vscale x 8 x i16> %b,
|
||||
<vscale x 8 x i16> %c)
|
||||
ret <vscale x 4 x i32> %res
|
||||
}
|
||||
|
||||
define <vscale x 2 x i64> @smlslt_i64(<vscale x 2 x i64> %a,
|
||||
<vscale x 4 x i32> %b,
|
||||
<vscale x 4 x i32> %c) {
|
||||
; CHECK-LABEL: smlslt_i64
|
||||
; CHECK: smlslt z0.d, z1.s, z2.s
|
||||
; CHECK-NEXT: ret
|
||||
%res = call <vscale x 2 x i64> @llvm.aarch64.sve.smlslt.nxv2i64(<vscale x 2 x i64> %a,
|
||||
<vscale x 4 x i32> %b,
|
||||
<vscale x 4 x i32> %c)
|
||||
ret <vscale x 2 x i64> %res
|
||||
}
|
||||
|
||||
;
|
||||
; UMLSLB
|
||||
;
|
||||
define <vscale x 8 x i16> @umlslb_i16(<vscale x 8 x i16> %a,
|
||||
<vscale x 16 x i8> %b,
|
||||
<vscale x 16 x i8> %c) {
|
||||
; CHECK-LABEL: umlslb_i16
|
||||
; CHECK: umlslb z0.h, z1.b, z2.b
|
||||
; CHECK-NEXT: ret
|
||||
%res = call <vscale x 8 x i16> @llvm.aarch64.sve.umlslb.nxv8i16(<vscale x 8 x i16> %a,
|
||||
<vscale x 16 x i8> %b,
|
||||
<vscale x 16 x i8> %c)
|
||||
ret <vscale x 8 x i16> %res
|
||||
}
|
||||
|
||||
define <vscale x 4 x i32> @umlslb_i32(<vscale x 4 x i32> %a,
|
||||
<vscale x 8 x i16> %b,
|
||||
<vscale x 8 x i16> %c) {
|
||||
; CHECK-LABEL: umlslb_i32
|
||||
; CHECK: umlslb z0.s, z1.h, z2.h
|
||||
; CHECK-NEXT: ret
|
||||
%res = call <vscale x 4 x i32> @llvm.aarch64.sve.umlslb.nxv4i32(<vscale x 4 x i32> %a,
|
||||
<vscale x 8 x i16> %b,
|
||||
<vscale x 8 x i16> %c)
|
||||
ret <vscale x 4 x i32> %res
|
||||
}
|
||||
|
||||
define <vscale x 2 x i64> @umlslb_i64(<vscale x 2 x i64> %a,
|
||||
<vscale x 4 x i32> %b,
|
||||
<vscale x 4 x i32> %c) {
|
||||
; CHECK-LABEL: umlslb_i64
|
||||
; CHECK: umlslb z0.d, z1.s, z2.s
|
||||
; CHECK-NEXT: ret
|
||||
%res = call <vscale x 2 x i64> @llvm.aarch64.sve.umlslb.nxv2i64(<vscale x 2 x i64> %a,
|
||||
<vscale x 4 x i32> %b,
|
||||
<vscale x 4 x i32> %c)
|
||||
ret <vscale x 2 x i64> %res
|
||||
}
|
||||
|
||||
;
|
||||
; UMLSLT
|
||||
;
|
||||
define <vscale x 8 x i16> @umlslt_i16(<vscale x 8 x i16> %a,
|
||||
<vscale x 16 x i8> %b,
|
||||
<vscale x 16 x i8> %c) {
|
||||
; CHECK-LABEL: umlslt_i16
|
||||
; CHECK: umlslt z0.h, z1.b, z2.b
|
||||
; CHECK-NEXT: ret
|
||||
%res = call <vscale x 8 x i16> @llvm.aarch64.sve.umlslt.nxv8i16(<vscale x 8 x i16> %a,
|
||||
<vscale x 16 x i8> %b,
|
||||
<vscale x 16 x i8> %c)
|
||||
ret <vscale x 8 x i16> %res
|
||||
}
|
||||
|
||||
define <vscale x 4 x i32> @umlslt_i32(<vscale x 4 x i32> %a,
|
||||
<vscale x 8 x i16> %b,
|
||||
<vscale x 8 x i16> %c) {
|
||||
; CHECK-LABEL: umlslt_i32
|
||||
; CHECK: umlslt z0.s, z1.h, z2.h
|
||||
; CHECK-NEXT: ret
|
||||
%res = call <vscale x 4 x i32> @llvm.aarch64.sve.umlslt.nxv4i32(<vscale x 4 x i32> %a,
|
||||
<vscale x 8 x i16> %b,
|
||||
<vscale x 8 x i16> %c)
|
||||
ret <vscale x 4 x i32> %res
|
||||
}
|
||||
|
||||
define <vscale x 2 x i64> @umlslt_i64(<vscale x 2 x i64> %a,
|
||||
<vscale x 4 x i32> %b,
|
||||
<vscale x 4 x i32> %c) {
|
||||
; CHECK-LABEL: umlslt_i64
|
||||
; CHECK: umlslt z0.d, z1.s, z2.s
|
||||
; CHECK-NEXT: ret
|
||||
%res = call <vscale x 2 x i64> @llvm.aarch64.sve.umlslt.nxv2i64(<vscale x 2 x i64> %a,
|
||||
<vscale x 4 x i32> %b,
|
||||
<vscale x 4 x i32> %c)
|
||||
ret <vscale x 2 x i64> %res
|
||||
}
|
||||
|
||||
;
|
||||
; SQDMLALB
|
||||
;
|
||||
define <vscale x 8 x i16> @sqdmlalb_i16(<vscale x 8 x i16> %a,
|
||||
<vscale x 16 x i8> %b,
|
||||
<vscale x 16 x i8> %c) {
|
||||
; CHECK-LABEL: sqdmlalb_i16
|
||||
; CHECK: sqdmlalb z0.h, z1.b, z2.b
|
||||
; CHECK-NEXT: ret
|
||||
%res = call <vscale x 8 x i16> @llvm.aarch64.sve.sqdmlalb.nxv8i16(<vscale x 8 x i16> %a,
|
||||
<vscale x 16 x i8> %b,
|
||||
<vscale x 16 x i8> %c)
|
||||
ret <vscale x 8 x i16> %res
|
||||
}
|
||||
|
||||
define <vscale x 4 x i32> @sqdmlalb_i32(<vscale x 4 x i32> %a,
|
||||
<vscale x 8 x i16> %b,
|
||||
<vscale x 8 x i16> %c) {
|
||||
; CHECK-LABEL: sqdmlalb_i32
|
||||
; CHECK: sqdmlalb z0.s, z1.h, z2.h
|
||||
; CHECK-NEXT: ret
|
||||
%res = call <vscale x 4 x i32> @llvm.aarch64.sve.sqdmlalb.nxv4i32(<vscale x 4 x i32> %a,
|
||||
<vscale x 8 x i16> %b,
|
||||
<vscale x 8 x i16> %c)
|
||||
ret <vscale x 4 x i32> %res
|
||||
}
|
||||
|
||||
define <vscale x 2 x i64> @sqdmlalb_i64(<vscale x 2 x i64> %a,
|
||||
<vscale x 4 x i32> %b,
|
||||
<vscale x 4 x i32> %c) {
|
||||
; CHECK-LABEL: sqdmlalb_i64
|
||||
; CHECK: sqdmlalb z0.d, z1.s, z2.s
|
||||
; CHECK-NEXT: ret
|
||||
%res = call <vscale x 2 x i64> @llvm.aarch64.sve.sqdmlalb.nxv2i64(<vscale x 2 x i64> %a,
|
||||
<vscale x 4 x i32> %b,
|
||||
<vscale x 4 x i32> %c)
|
||||
ret <vscale x 2 x i64> %res
|
||||
}
|
||||
|
||||
;
|
||||
; SQDMLALT
|
||||
;
|
||||
define <vscale x 8 x i16> @sqdmlalt_i16(<vscale x 8 x i16> %a,
|
||||
<vscale x 16 x i8> %b,
|
||||
<vscale x 16 x i8> %c) {
|
||||
; CHECK-LABEL: sqdmlalt_i16
|
||||
; CHECK: sqdmlalt z0.h, z1.b, z2.b
|
||||
; CHECK-NEXT: ret
|
||||
%res = call <vscale x 8 x i16> @llvm.aarch64.sve.sqdmlalt.nxv8i16(<vscale x 8 x i16> %a,
|
||||
<vscale x 16 x i8> %b,
|
||||
<vscale x 16 x i8> %c)
|
||||
ret <vscale x 8 x i16> %res
|
||||
}
|
||||
|
||||
define <vscale x 4 x i32> @sqdmlalt_i32(<vscale x 4 x i32> %a,
|
||||
<vscale x 8 x i16> %b,
|
||||
<vscale x 8 x i16> %c) {
|
||||
; CHECK-LABEL: sqdmlalt_i32
|
||||
; CHECK: sqdmlalt z0.s, z1.h, z2.h
|
||||
; CHECK-NEXT: ret
|
||||
%res = call <vscale x 4 x i32> @llvm.aarch64.sve.sqdmlalt.nxv4i32(<vscale x 4 x i32> %a,
|
||||
<vscale x 8 x i16> %b,
|
||||
<vscale x 8 x i16> %c)
|
||||
ret <vscale x 4 x i32> %res
|
||||
}
|
||||
|
||||
define <vscale x 2 x i64> @sqdmlalt_i64(<vscale x 2 x i64> %a,
|
||||
<vscale x 4 x i32> %b,
|
||||
<vscale x 4 x i32> %c) {
|
||||
; CHECK-LABEL: sqdmlalt_i64
|
||||
; CHECK: sqdmlalt z0.d, z1.s, z2.s
|
||||
; CHECK-NEXT: ret
|
||||
%res = call <vscale x 2 x i64> @llvm.aarch64.sve.sqdmlalt.nxv2i64(<vscale x 2 x i64> %a,
|
||||
<vscale x 4 x i32> %b,
|
||||
<vscale x 4 x i32> %c)
|
||||
ret <vscale x 2 x i64> %res
|
||||
}
|
||||
|
||||
;
|
||||
; SQDMLSLB
|
||||
;
|
||||
define <vscale x 8 x i16> @sqdmlslb_i16(<vscale x 8 x i16> %a,
|
||||
<vscale x 16 x i8> %b,
|
||||
<vscale x 16 x i8> %c) {
|
||||
; CHECK-LABEL: sqdmlslb_i16
|
||||
; CHECK: sqdmlslb z0.h, z1.b, z2.b
|
||||
; CHECK-NEXT: ret
|
||||
%res = call <vscale x 8 x i16> @llvm.aarch64.sve.sqdmlslb.nxv8i16(<vscale x 8 x i16> %a,
|
||||
<vscale x 16 x i8> %b,
|
||||
<vscale x 16 x i8> %c)
|
||||
ret <vscale x 8 x i16> %res
|
||||
}
|
||||
|
||||
define <vscale x 4 x i32> @sqdmlslb_i32(<vscale x 4 x i32> %a,
|
||||
<vscale x 8 x i16> %b,
|
||||
<vscale x 8 x i16> %c) {
|
||||
; CHECK-LABEL: sqdmlslb_i32
|
||||
; CHECK: sqdmlslb z0.s, z1.h, z2.h
|
||||
; CHECK-NEXT: ret
|
||||
%res = call <vscale x 4 x i32> @llvm.aarch64.sve.sqdmlslb.nxv4i32(<vscale x 4 x i32> %a,
|
||||
<vscale x 8 x i16> %b,
|
||||
<vscale x 8 x i16> %c)
|
||||
ret <vscale x 4 x i32> %res
|
||||
}
|
||||
|
||||
define <vscale x 2 x i64> @sqdmlslb_i64(<vscale x 2 x i64> %a,
|
||||
<vscale x 4 x i32> %b,
|
||||
<vscale x 4 x i32> %c) {
|
||||
; CHECK-LABEL: sqdmlslb_i64
|
||||
; CHECK: sqdmlslb z0.d, z1.s, z2.s
|
||||
; CHECK-NEXT: ret
|
||||
%res = call <vscale x 2 x i64> @llvm.aarch64.sve.sqdmlslb.nxv2i64(<vscale x 2 x i64> %a,
|
||||
<vscale x 4 x i32> %b,
|
||||
<vscale x 4 x i32> %c)
|
||||
ret <vscale x 2 x i64> %res
|
||||
}
|
||||
|
||||
;
|
||||
; SQDMLSLT
|
||||
;
|
||||
define <vscale x 8 x i16> @sqdmlslt_i16(<vscale x 8 x i16> %a,
|
||||
<vscale x 16 x i8> %b,
|
||||
<vscale x 16 x i8> %c) {
|
||||
; CHECK-LABEL: sqdmlslt_i16
|
||||
; CHECK: sqdmlslt z0.h, z1.b, z2.b
|
||||
; CHECK-NEXT: ret
|
||||
%res = call <vscale x 8 x i16> @llvm.aarch64.sve.sqdmlslt.nxv8i16(<vscale x 8 x i16> %a,
|
||||
<vscale x 16 x i8> %b,
|
||||
<vscale x 16 x i8> %c)
|
||||
ret <vscale x 8 x i16> %res
|
||||
}
|
||||
|
||||
define <vscale x 4 x i32> @sqdmlslt_i32(<vscale x 4 x i32> %a,
|
||||
<vscale x 8 x i16> %b,
|
||||
<vscale x 8 x i16> %c) {
|
||||
; CHECK-LABEL: sqdmlslt_i32
|
||||
; CHECK: sqdmlslt z0.s, z1.h, z2.h
|
||||
; CHECK-NEXT: ret
|
||||
%res = call <vscale x 4 x i32> @llvm.aarch64.sve.sqdmlslt.nxv4i32(<vscale x 4 x i32> %a,
|
||||
<vscale x 8 x i16> %b,
|
||||
<vscale x 8 x i16> %c)
|
||||
ret <vscale x 4 x i32> %res
|
||||
}
|
||||
|
||||
define <vscale x 2 x i64> @sqdmlslt_i64(<vscale x 2 x i64> %a,
|
||||
<vscale x 4 x i32> %b,
|
||||
<vscale x 4 x i32> %c) {
|
||||
; CHECK-LABEL: sqdmlslt_i64
|
||||
; CHECK: sqdmlslt z0.d, z1.s, z2.s
|
||||
; CHECK-NEXT: ret
|
||||
%res = call <vscale x 2 x i64> @llvm.aarch64.sve.sqdmlslt.nxv2i64(<vscale x 2 x i64> %a,
|
||||
<vscale x 4 x i32> %b,
|
||||
<vscale x 4 x i32> %c)
|
||||
ret <vscale x 2 x i64> %res
|
||||
}
|
||||
|
||||
;
|
||||
; SQDMLALBT
|
||||
;
|
||||
define <vscale x 8 x i16> @sqdmlalbt_i16(<vscale x 8 x i16> %a,
|
||||
<vscale x 16 x i8> %b,
|
||||
<vscale x 16 x i8> %c) {
|
||||
; CHECK-LABEL: sqdmlalbt_i16
|
||||
; CHECK: sqdmlalbt z0.h, z1.b, z2.b
|
||||
; CHECK-NEXT: ret
|
||||
%res = call <vscale x 8 x i16> @llvm.aarch64.sve.sqdmlalbt.nxv8i16(<vscale x 8 x i16> %a,
|
||||
<vscale x 16 x i8> %b,
|
||||
<vscale x 16 x i8> %c)
|
||||
ret <vscale x 8 x i16> %res
|
||||
}
|
||||
|
||||
define <vscale x 4 x i32> @sqdmlalbt_i32(<vscale x 4 x i32> %a,
|
||||
<vscale x 8 x i16> %b,
|
||||
<vscale x 8 x i16> %c) {
|
||||
; CHECK-LABEL: sqdmlalbt_i32
|
||||
; CHECK: sqdmlalbt z0.s, z1.h, z2.h
|
||||
; CHECK-NEXT: ret
|
||||
%res = call <vscale x 4 x i32> @llvm.aarch64.sve.sqdmlalbt.nxv4i32(<vscale x 4 x i32> %a,
|
||||
<vscale x 8 x i16> %b,
|
||||
<vscale x 8 x i16> %c)
|
||||
ret <vscale x 4 x i32> %res
|
||||
}
|
||||
|
||||
define <vscale x 2 x i64> @sqdmlalbt_i64(<vscale x 2 x i64> %a,
|
||||
<vscale x 4 x i32> %b,
|
||||
<vscale x 4 x i32> %c) {
|
||||
; CHECK-LABEL: sqdmlalbt_i64
|
||||
; CHECK: sqdmlalbt z0.d, z1.s, z2.s
|
||||
; CHECK-NEXT: ret
|
||||
%res = call <vscale x 2 x i64> @llvm.aarch64.sve.sqdmlalbt.nxv2i64(<vscale x 2 x i64> %a,
|
||||
<vscale x 4 x i32> %b,
|
||||
<vscale x 4 x i32> %c)
|
||||
ret <vscale x 2 x i64> %res
|
||||
}
|
||||
|
||||
;
|
||||
; SQDMLSLBT
|
||||
;
|
||||
define <vscale x 8 x i16> @sqdmlslbt_i16(<vscale x 8 x i16> %a,
|
||||
<vscale x 16 x i8> %b,
|
||||
<vscale x 16 x i8> %c) {
|
||||
; CHECK-LABEL: sqdmlslbt_i16
|
||||
; CHECK: sqdmlslbt z0.h, z1.b, z2.b
|
||||
; CHECK-NEXT: ret
|
||||
%res = call <vscale x 8 x i16> @llvm.aarch64.sve.sqdmlslbt.nxv8i16(<vscale x 8 x i16> %a,
|
||||
<vscale x 16 x i8> %b,
|
||||
<vscale x 16 x i8> %c)
|
||||
ret <vscale x 8 x i16> %res
|
||||
}
|
||||
|
||||
define <vscale x 4 x i32> @sqdmlslbt_i32(<vscale x 4 x i32> %a,
|
||||
<vscale x 8 x i16> %b,
|
||||
<vscale x 8 x i16> %c) {
|
||||
; CHECK-LABEL: sqdmlslbt_i32
|
||||
; CHECK: sqdmlslbt z0.s, z1.h, z2.h
|
||||
; CHECK-NEXT: ret
|
||||
%res = call <vscale x 4 x i32> @llvm.aarch64.sve.sqdmlslbt.nxv4i32(<vscale x 4 x i32> %a,
|
||||
<vscale x 8 x i16> %b,
|
||||
<vscale x 8 x i16> %c)
|
||||
ret <vscale x 4 x i32> %res
|
||||
}
|
||||
|
||||
define <vscale x 2 x i64> @sqdmlslbt_i64(<vscale x 2 x i64> %a,
|
||||
<vscale x 4 x i32> %b,
|
||||
<vscale x 4 x i32> %c) {
|
||||
; CHECK-LABEL: sqdmlslbt_i64
|
||||
; CHECK: sqdmlslbt z0.d, z1.s, z2.s
|
||||
; CHECK-NEXT: ret
|
||||
%res = call <vscale x 2 x i64> @llvm.aarch64.sve.sqdmlslbt.nxv2i64(<vscale x 2 x i64> %a,
|
||||
<vscale x 4 x i32> %b,
|
||||
<vscale x 4 x i32> %c)
|
||||
ret <vscale x 2 x i64> %res
|
||||
}
|
||||
|
||||
declare <vscale x 8 x i16> @llvm.aarch64.sve.smlalb.nxv8i16(<vscale x 8 x i16>, <vscale x 16 x i8>, <vscale x 16 x i8>)
|
||||
declare <vscale x 4 x i32> @llvm.aarch64.sve.smlalb.nxv4i32(<vscale x 4 x i32>, <vscale x 8 x i16>, <vscale x 8 x i16>)
|
||||
declare <vscale x 2 x i64> @llvm.aarch64.sve.smlalb.nxv2i64(<vscale x 2 x i64>, <vscale x 4 x i32>, <vscale x 4 x i32>)
|
||||
declare <vscale x 8 x i16> @llvm.aarch64.sve.smlalt.nxv8i16(<vscale x 8 x i16>, <vscale x 16 x i8>, <vscale x 16 x i8>)
|
||||
declare <vscale x 4 x i32> @llvm.aarch64.sve.smlalt.nxv4i32(<vscale x 4 x i32>, <vscale x 8 x i16>, <vscale x 8 x i16>)
|
||||
declare <vscale x 2 x i64> @llvm.aarch64.sve.smlalt.nxv2i64(<vscale x 2 x i64>, <vscale x 4 x i32>, <vscale x 4 x i32>)
|
||||
declare <vscale x 8 x i16> @llvm.aarch64.sve.umlalb.nxv8i16(<vscale x 8 x i16>, <vscale x 16 x i8>, <vscale x 16 x i8>)
|
||||
declare <vscale x 4 x i32> @llvm.aarch64.sve.umlalb.nxv4i32(<vscale x 4 x i32>, <vscale x 8 x i16>, <vscale x 8 x i16>)
|
||||
declare <vscale x 2 x i64> @llvm.aarch64.sve.umlalb.nxv2i64(<vscale x 2 x i64>, <vscale x 4 x i32>, <vscale x 4 x i32>)
|
||||
declare <vscale x 8 x i16> @llvm.aarch64.sve.umlalt.nxv8i16(<vscale x 8 x i16>, <vscale x 16 x i8>, <vscale x 16 x i8>)
|
||||
declare <vscale x 4 x i32> @llvm.aarch64.sve.umlalt.nxv4i32(<vscale x 4 x i32>, <vscale x 8 x i16>, <vscale x 8 x i16>)
|
||||
declare <vscale x 2 x i64> @llvm.aarch64.sve.umlalt.nxv2i64(<vscale x 2 x i64>, <vscale x 4 x i32>, <vscale x 4 x i32>)
|
||||
declare <vscale x 8 x i16> @llvm.aarch64.sve.smlslb.nxv8i16(<vscale x 8 x i16>, <vscale x 16 x i8>, <vscale x 16 x i8>)
|
||||
declare <vscale x 4 x i32> @llvm.aarch64.sve.smlslb.nxv4i32(<vscale x 4 x i32>, <vscale x 8 x i16>, <vscale x 8 x i16>)
|
||||
declare <vscale x 2 x i64> @llvm.aarch64.sve.smlslb.nxv2i64(<vscale x 2 x i64>, <vscale x 4 x i32>, <vscale x 4 x i32>)
|
||||
declare <vscale x 8 x i16> @llvm.aarch64.sve.smlslt.nxv8i16(<vscale x 8 x i16>, <vscale x 16 x i8>, <vscale x 16 x i8>)
|
||||
declare <vscale x 4 x i32> @llvm.aarch64.sve.smlslt.nxv4i32(<vscale x 4 x i32>, <vscale x 8 x i16>, <vscale x 8 x i16>)
|
||||
declare <vscale x 2 x i64> @llvm.aarch64.sve.smlslt.nxv2i64(<vscale x 2 x i64>, <vscale x 4 x i32>, <vscale x 4 x i32>)
|
||||
declare <vscale x 8 x i16> @llvm.aarch64.sve.umlslb.nxv8i16(<vscale x 8 x i16>, <vscale x 16 x i8>, <vscale x 16 x i8>)
|
||||
declare <vscale x 4 x i32> @llvm.aarch64.sve.umlslb.nxv4i32(<vscale x 4 x i32>, <vscale x 8 x i16>, <vscale x 8 x i16>)
|
||||
declare <vscale x 2 x i64> @llvm.aarch64.sve.umlslb.nxv2i64(<vscale x 2 x i64>, <vscale x 4 x i32>, <vscale x 4 x i32>)
|
||||
declare <vscale x 8 x i16> @llvm.aarch64.sve.umlslt.nxv8i16(<vscale x 8 x i16>, <vscale x 16 x i8>, <vscale x 16 x i8>)
|
||||
declare <vscale x 4 x i32> @llvm.aarch64.sve.umlslt.nxv4i32(<vscale x 4 x i32>, <vscale x 8 x i16>, <vscale x 8 x i16>)
|
||||
declare <vscale x 2 x i64> @llvm.aarch64.sve.umlslt.nxv2i64(<vscale x 2 x i64>, <vscale x 4 x i32>, <vscale x 4 x i32>)
|
||||
declare <vscale x 8 x i16> @llvm.aarch64.sve.sqdmlalb.nxv8i16(<vscale x 8 x i16>, <vscale x 16 x i8>, <vscale x 16 x i8>)
|
||||
declare <vscale x 4 x i32> @llvm.aarch64.sve.sqdmlalb.nxv4i32(<vscale x 4 x i32>, <vscale x 8 x i16>, <vscale x 8 x i16>)
|
||||
declare <vscale x 2 x i64> @llvm.aarch64.sve.sqdmlalb.nxv2i64(<vscale x 2 x i64>, <vscale x 4 x i32>, <vscale x 4 x i32>)
|
||||
declare <vscale x 8 x i16> @llvm.aarch64.sve.sqdmlalt.nxv8i16(<vscale x 8 x i16>, <vscale x 16 x i8>, <vscale x 16 x i8>)
|
||||
declare <vscale x 4 x i32> @llvm.aarch64.sve.sqdmlalt.nxv4i32(<vscale x 4 x i32>, <vscale x 8 x i16>, <vscale x 8 x i16>)
|
||||
declare <vscale x 2 x i64> @llvm.aarch64.sve.sqdmlalt.nxv2i64(<vscale x 2 x i64>, <vscale x 4 x i32>, <vscale x 4 x i32>)
|
||||
declare <vscale x 8 x i16> @llvm.aarch64.sve.sqdmlslb.nxv8i16(<vscale x 8 x i16>, <vscale x 16 x i8>, <vscale x 16 x i8>)
|
||||
declare <vscale x 4 x i32> @llvm.aarch64.sve.sqdmlslb.nxv4i32(<vscale x 4 x i32>, <vscale x 8 x i16>, <vscale x 8 x i16>)
|
||||
declare <vscale x 2 x i64> @llvm.aarch64.sve.sqdmlslb.nxv2i64(<vscale x 2 x i64>, <vscale x 4 x i32>, <vscale x 4 x i32>)
|
||||
declare <vscale x 8 x i16> @llvm.aarch64.sve.sqdmlslt.nxv8i16(<vscale x 8 x i16>, <vscale x 16 x i8>, <vscale x 16 x i8>)
|
||||
declare <vscale x 4 x i32> @llvm.aarch64.sve.sqdmlslt.nxv4i32(<vscale x 4 x i32>, <vscale x 8 x i16>, <vscale x 8 x i16>)
|
||||
declare <vscale x 2 x i64> @llvm.aarch64.sve.sqdmlslt.nxv2i64(<vscale x 2 x i64>, <vscale x 4 x i32>, <vscale x 4 x i32>)
|
||||
declare <vscale x 8 x i16> @llvm.aarch64.sve.sqdmlalbt.nxv8i16(<vscale x 8 x i16>, <vscale x 16 x i8>, <vscale x 16 x i8>)
|
||||
declare <vscale x 4 x i32> @llvm.aarch64.sve.sqdmlalbt.nxv4i32(<vscale x 4 x i32>, <vscale x 8 x i16>, <vscale x 8 x i16>)
|
||||
declare <vscale x 2 x i64> @llvm.aarch64.sve.sqdmlalbt.nxv2i64(<vscale x 2 x i64>, <vscale x 4 x i32>, <vscale x 4 x i32>)
|
||||
declare <vscale x 8 x i16> @llvm.aarch64.sve.sqdmlslbt.nxv8i16(<vscale x 8 x i16>, <vscale x 16 x i8>, <vscale x 16 x i8>)
|
||||
declare <vscale x 4 x i32> @llvm.aarch64.sve.sqdmlslbt.nxv4i32(<vscale x 4 x i32>, <vscale x 8 x i16>, <vscale x 8 x i16>)
|
||||
declare <vscale x 2 x i64> @llvm.aarch64.sve.sqdmlslbt.nxv2i64(<vscale x 2 x i64>, <vscale x 4 x i32>, <vscale x 4 x i32>)
|
||||
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Reference in New Issue
Block a user