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Switch the PPC backend over to using FORMAL_ARGUMENTS for formal argument
handling. This makes the lower argument code significantly simpler (we only need to handle legal argument types). Incidentally, this also implements support for vector argument registers, so long as they are not on the stack. llvm-svn: 28331
This commit is contained in:
Chris Lattner
parent
bfb68e47ca
commit
0a12e343e2
@ -727,6 +727,161 @@ static SDOperand LowerVASTART(SDOperand Op, SelectionDAG &DAG,
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Op.getOperand(1), Op.getOperand(2));
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Op.getOperand(1), Op.getOperand(2));
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}
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}
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static SDOperand LowerFORMAL_ARGUMENTS(SDOperand Op, SelectionDAG &DAG,
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int &VarArgsFrameIndex) {
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// TODO: add description of PPC stack frame format, or at least some docs.
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//
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MachineFunction &MF = DAG.getMachineFunction();
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MachineFrameInfo *MFI = MF.getFrameInfo();
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SSARegMap *RegMap = MF.getSSARegMap();
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std::vector<SDOperand> ArgValues;
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SDOperand Root = Op.getOperand(0);
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unsigned ArgOffset = 24;
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unsigned GPR_remaining = 8;
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unsigned FPR_remaining = 13;
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unsigned VR_remaining = 12;
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unsigned GPR_idx = 0, FPR_idx = 0, VR_idx = 0;
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static const unsigned GPR[] = {
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PPC::R3, PPC::R4, PPC::R5, PPC::R6,
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PPC::R7, PPC::R8, PPC::R9, PPC::R10,
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};
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static const unsigned FPR[] = {
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PPC::F1, PPC::F2, PPC::F3, PPC::F4, PPC::F5, PPC::F6, PPC::F7,
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PPC::F8, PPC::F9, PPC::F10, PPC::F11, PPC::F12, PPC::F13
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};
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static const unsigned VR[] = {
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PPC::V2, PPC::V3, PPC::V4, PPC::V5, PPC::V6, PPC::V7, PPC::V8,
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PPC::V9, PPC::V10, PPC::V11, PPC::V12, PPC::V13
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};
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// Add DAG nodes to load the arguments or copy them out of registers. On
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// entry to a function on PPC, the arguments start at offset 24, although the
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// first ones are often in registers.
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for (unsigned ArgNo = 0, e = Op.Val->getNumValues()-1; ArgNo != e; ++ArgNo) {
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SDOperand ArgVal;
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bool needsLoad = false;
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bool ArgLive = !Op.Val->hasNUsesOfValue(0, ArgNo);
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MVT::ValueType ObjectVT = Op.getValue(ArgNo).getValueType();
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unsigned ObjSize = MVT::getSizeInBits(ObjectVT)/8;
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switch (ObjectVT) {
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default: assert(0 && "Unhandled argument type!");
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case MVT::i32:
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if (!ArgLive) break;
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if (GPR_remaining > 0) {
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unsigned VReg = RegMap->createVirtualRegister(&PPC::GPRCRegClass);
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MF.addLiveIn(GPR[GPR_idx], VReg);
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ArgVal = DAG.getCopyFromReg(Root, VReg, MVT::i32);
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} else {
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needsLoad = true;
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}
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break;
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case MVT::f32:
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case MVT::f64:
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if (!ArgLive) {
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if (FPR_remaining > 0) {
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--FPR_remaining;
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++FPR_idx;
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}
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break;
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}
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if (FPR_remaining > 0) {
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unsigned VReg;
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if (ObjectVT == MVT::f32)
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VReg = RegMap->createVirtualRegister(&PPC::F4RCRegClass);
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else
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VReg = RegMap->createVirtualRegister(&PPC::F8RCRegClass);
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MF.addLiveIn(FPR[FPR_idx], VReg);
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ArgVal = DAG.getCopyFromReg(Root, VReg, ObjectVT);
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--FPR_remaining;
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++FPR_idx;
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} else {
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needsLoad = true;
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}
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break;
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case MVT::v4f32:
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case MVT::v4i32:
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case MVT::v8i16:
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case MVT::v16i8:
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if (!ArgLive) {
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if (VR_remaining > 0) {
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--VR_remaining;
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++VR_idx;
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}
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break;
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}
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if (VR_remaining > 0) {
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unsigned VReg = RegMap->createVirtualRegister(&PPC::VRRCRegClass);
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MF.addLiveIn(VR[VR_idx], VReg);
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ArgVal = DAG.getCopyFromReg(Root, VReg, ObjectVT);
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--VR_remaining;
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++VR_idx;
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} else {
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// This should be simple, but requires getting 16-byte aligned stack
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// values.
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assert(0 && "Loading VR argument not implemented yet!");
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needsLoad = true;
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}
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break;
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}
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// We need to load the argument to a virtual register if we determined above
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// that we ran out of physical registers of the appropriate type
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if (needsLoad) {
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int FI = MFI->CreateFixedObject(ObjSize, ArgOffset);
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SDOperand FIN = DAG.getFrameIndex(FI, MVT::i32);
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ArgVal = DAG.getLoad(ObjectVT, Root, FIN,
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DAG.getSrcValue(NULL));
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}
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// Every 4 bytes of argument space consumes one of the GPRs available for
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// argument passing.
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if (GPR_remaining > 0) {
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unsigned delta = (GPR_remaining > 1 && ObjSize == 8) ? 2 : 1;
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GPR_remaining -= delta;
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GPR_idx += delta;
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}
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ArgOffset += ObjSize;
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if (ArgVal.Val == 0)
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ArgVal = DAG.getNode(ISD::UNDEF, ObjectVT);
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ArgValues.push_back(ArgVal);
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}
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// If the function takes variable number of arguments, make a frame index for
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// the start of the first vararg value... for expansion of llvm.va_start.
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bool isVarArg = cast<ConstantSDNode>(Op.getOperand(2))->getValue() != 0;
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if (isVarArg) {
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VarArgsFrameIndex = MFI->CreateFixedObject(4, ArgOffset);
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SDOperand FIN = DAG.getFrameIndex(VarArgsFrameIndex, MVT::i32);
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// If this function is vararg, store any remaining integer argument regs
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// to their spots on the stack so that they may be loaded by deferencing the
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// result of va_next.
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std::vector<SDOperand> MemOps;
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for (; GPR_remaining > 0; --GPR_remaining, ++GPR_idx) {
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unsigned VReg = RegMap->createVirtualRegister(&PPC::GPRCRegClass);
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MF.addLiveIn(GPR[GPR_idx], VReg);
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SDOperand Val = DAG.getCopyFromReg(Root, VReg, MVT::i32);
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SDOperand Store = DAG.getNode(ISD::STORE, MVT::Other, Val.getValue(1),
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Val, FIN, DAG.getSrcValue(NULL));
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MemOps.push_back(Store);
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// Increment the address by four for the next argument to store
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SDOperand PtrOff = DAG.getConstant(4, MVT::i32);
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FIN = DAG.getNode(ISD::ADD, MVT::i32, FIN, PtrOff);
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}
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if (!MemOps.empty())
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Root = DAG.getNode(ISD::TokenFactor, MVT::Other, MemOps);
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}
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ArgValues.push_back(Root);
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// Return the new list of results.
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std::vector<MVT::ValueType> RetVT(Op.Val->value_begin(),
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Op.Val->value_end());
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return DAG.getNode(ISD::MERGE_VALUES, RetVT, ArgValues);
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}
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static SDOperand LowerRET(SDOperand Op, SelectionDAG &DAG) {
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static SDOperand LowerRET(SDOperand Op, SelectionDAG &DAG) {
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SDOperand Copy;
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SDOperand Copy;
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switch(Op.getNumOperands()) {
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switch(Op.getNumOperands()) {
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@ -1690,6 +1845,8 @@ SDOperand PPCTargetLowering::LowerOperation(SDOperand Op, SelectionDAG &DAG) {
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case ISD::JumpTable: return LowerJumpTable(Op, DAG);
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case ISD::JumpTable: return LowerJumpTable(Op, DAG);
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case ISD::SETCC: return LowerSETCC(Op, DAG);
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case ISD::SETCC: return LowerSETCC(Op, DAG);
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case ISD::VASTART: return LowerVASTART(Op, DAG, VarArgsFrameIndex);
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case ISD::VASTART: return LowerVASTART(Op, DAG, VarArgsFrameIndex);
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case ISD::FORMAL_ARGUMENTS: return LowerFORMAL_ARGUMENTS(Op, DAG,
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VarArgsFrameIndex);
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case ISD::RET: return LowerRET(Op, DAG);
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case ISD::RET: return LowerRET(Op, DAG);
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case ISD::SELECT_CC: return LowerSELECT_CC(Op, DAG);
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case ISD::SELECT_CC: return LowerSELECT_CC(Op, DAG);
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@ -1715,174 +1872,6 @@ SDOperand PPCTargetLowering::LowerOperation(SDOperand Op, SelectionDAG &DAG) {
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// Other Lowering Code
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// Other Lowering Code
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//===----------------------------------------------------------------------===//
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//===----------------------------------------------------------------------===//
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std::vector<SDOperand>
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PPCTargetLowering::LowerArguments(Function &F, SelectionDAG &DAG) {
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//
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// add beautiful description of PPC stack frame format, or at least some docs
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//
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MachineFunction &MF = DAG.getMachineFunction();
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MachineFrameInfo *MFI = MF.getFrameInfo();
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SSARegMap *RegMap = MF.getSSARegMap();
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std::vector<SDOperand> ArgValues;
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unsigned ArgOffset = 24;
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unsigned GPR_remaining = 8;
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unsigned FPR_remaining = 13;
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unsigned GPR_idx = 0, FPR_idx = 0;
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static const unsigned GPR[] = {
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PPC::R3, PPC::R4, PPC::R5, PPC::R6,
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PPC::R7, PPC::R8, PPC::R9, PPC::R10,
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};
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static const unsigned FPR[] = {
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PPC::F1, PPC::F2, PPC::F3, PPC::F4, PPC::F5, PPC::F6, PPC::F7,
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PPC::F8, PPC::F9, PPC::F10, PPC::F11, PPC::F12, PPC::F13
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};
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// Add DAG nodes to load the arguments... On entry to a function on PPC,
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// the arguments start at offset 24, although they are likely to be passed
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// in registers.
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for (Function::arg_iterator I = F.arg_begin(), E = F.arg_end(); I != E; ++I) {
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SDOperand newroot, argt;
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unsigned ObjSize;
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bool needsLoad = false;
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bool ArgLive = !I->use_empty();
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MVT::ValueType ObjectVT = getValueType(I->getType());
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switch (ObjectVT) {
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default: assert(0 && "Unhandled argument type!");
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case MVT::i1:
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case MVT::i8:
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case MVT::i16:
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case MVT::i32:
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ObjSize = 4;
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if (!ArgLive) break;
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if (GPR_remaining > 0) {
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unsigned VReg = RegMap->createVirtualRegister(&PPC::GPRCRegClass);
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MF.addLiveIn(GPR[GPR_idx], VReg);
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argt = newroot = DAG.getCopyFromReg(DAG.getRoot(), VReg, MVT::i32);
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if (ObjectVT != MVT::i32) {
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unsigned AssertOp = I->getType()->isSigned() ? ISD::AssertSext
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: ISD::AssertZext;
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argt = DAG.getNode(AssertOp, MVT::i32, argt,
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DAG.getValueType(ObjectVT));
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argt = DAG.getNode(ISD::TRUNCATE, ObjectVT, argt);
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}
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} else {
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needsLoad = true;
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}
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break;
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case MVT::i64:
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ObjSize = 8;
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if (!ArgLive) break;
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if (GPR_remaining > 0) {
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SDOperand argHi, argLo;
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unsigned VReg = RegMap->createVirtualRegister(&PPC::GPRCRegClass);
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MF.addLiveIn(GPR[GPR_idx], VReg);
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argHi = DAG.getCopyFromReg(DAG.getRoot(), VReg, MVT::i32);
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// If we have two or more remaining argument registers, then both halves
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// of the i64 can be sourced from there. Otherwise, the lower half will
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// have to come off the stack. This can happen when an i64 is preceded
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// by 28 bytes of arguments.
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if (GPR_remaining > 1) {
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unsigned VReg = RegMap->createVirtualRegister(&PPC::GPRCRegClass);
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MF.addLiveIn(GPR[GPR_idx+1], VReg);
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argLo = DAG.getCopyFromReg(argHi, VReg, MVT::i32);
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} else {
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int FI = MFI->CreateFixedObject(4, ArgOffset+4);
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SDOperand FIN = DAG.getFrameIndex(FI, MVT::i32);
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argLo = DAG.getLoad(MVT::i32, DAG.getEntryNode(), FIN,
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DAG.getSrcValue(NULL));
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}
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// Build the outgoing arg thingy
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argt = DAG.getNode(ISD::BUILD_PAIR, MVT::i64, argLo, argHi);
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newroot = argLo;
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} else {
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needsLoad = true;
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}
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break;
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case MVT::f32:
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case MVT::f64:
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ObjSize = (ObjectVT == MVT::f64) ? 8 : 4;
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if (!ArgLive) {
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if (FPR_remaining > 0) {
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--FPR_remaining;
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++FPR_idx;
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}
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break;
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}
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if (FPR_remaining > 0) {
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unsigned VReg;
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if (ObjectVT == MVT::f32)
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VReg = RegMap->createVirtualRegister(&PPC::F4RCRegClass);
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else
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VReg = RegMap->createVirtualRegister(&PPC::F8RCRegClass);
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MF.addLiveIn(FPR[FPR_idx], VReg);
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argt = newroot = DAG.getCopyFromReg(DAG.getRoot(), VReg, ObjectVT);
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--FPR_remaining;
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++FPR_idx;
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} else {
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needsLoad = true;
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}
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break;
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}
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// We need to load the argument to a virtual register if we determined above
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// that we ran out of physical registers of the appropriate type
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if (needsLoad) {
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unsigned SubregOffset = 0;
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if (ObjectVT == MVT::i8 || ObjectVT == MVT::i1) SubregOffset = 3;
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if (ObjectVT == MVT::i16) SubregOffset = 2;
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int FI = MFI->CreateFixedObject(ObjSize, ArgOffset);
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SDOperand FIN = DAG.getFrameIndex(FI, MVT::i32);
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FIN = DAG.getNode(ISD::ADD, MVT::i32, FIN,
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DAG.getConstant(SubregOffset, MVT::i32));
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argt = newroot = DAG.getLoad(ObjectVT, DAG.getEntryNode(), FIN,
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DAG.getSrcValue(NULL));
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}
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// Every 4 bytes of argument space consumes one of the GPRs available for
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// argument passing.
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if (GPR_remaining > 0) {
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unsigned delta = (GPR_remaining > 1 && ObjSize == 8) ? 2 : 1;
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GPR_remaining -= delta;
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GPR_idx += delta;
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}
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ArgOffset += ObjSize;
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if (newroot.Val)
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DAG.setRoot(newroot.getValue(1));
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ArgValues.push_back(argt);
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}
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// If the function takes variable number of arguments, make a frame index for
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// the start of the first vararg value... for expansion of llvm.va_start.
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if (F.isVarArg()) {
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VarArgsFrameIndex = MFI->CreateFixedObject(4, ArgOffset);
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SDOperand FIN = DAG.getFrameIndex(VarArgsFrameIndex, MVT::i32);
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// If this function is vararg, store any remaining integer argument regs
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// to their spots on the stack so that they may be loaded by deferencing the
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// result of va_next.
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std::vector<SDOperand> MemOps;
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for (; GPR_remaining > 0; --GPR_remaining, ++GPR_idx) {
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unsigned VReg = RegMap->createVirtualRegister(&PPC::GPRCRegClass);
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MF.addLiveIn(GPR[GPR_idx], VReg);
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SDOperand Val = DAG.getCopyFromReg(DAG.getRoot(), VReg, MVT::i32);
|
|
||||||
SDOperand Store = DAG.getNode(ISD::STORE, MVT::Other, Val.getValue(1),
|
|
||||||
Val, FIN, DAG.getSrcValue(NULL));
|
|
||||||
MemOps.push_back(Store);
|
|
||||||
// Increment the address by four for the next argument to store
|
|
||||||
SDOperand PtrOff = DAG.getConstant(4, getPointerTy());
|
|
||||||
FIN = DAG.getNode(ISD::ADD, MVT::i32, FIN, PtrOff);
|
|
||||||
}
|
|
||||||
if (!MemOps.empty()) {
|
|
||||||
MemOps.push_back(DAG.getRoot());
|
|
||||||
DAG.setRoot(DAG.getNode(ISD::TokenFactor, MVT::Other, MemOps));
|
|
||||||
}
|
|
||||||
}
|
|
||||||
|
|
||||||
return ArgValues;
|
|
||||||
}
|
|
||||||
|
|
||||||
std::pair<SDOperand, SDOperand>
|
std::pair<SDOperand, SDOperand>
|
||||||
PPCTargetLowering::LowerCallTo(SDOperand Chain,
|
PPCTargetLowering::LowerCallTo(SDOperand Chain,
|
||||||
const Type *RetTy, bool isVarArg,
|
const Type *RetTy, bool isVarArg,
|
||||||
|
|||||||
@ -166,10 +166,6 @@ namespace llvm {
|
|||||||
uint64_t &KnownZero,
|
uint64_t &KnownZero,
|
||||||
uint64_t &KnownOne,
|
uint64_t &KnownOne,
|
||||||
unsigned Depth = 0) const;
|
unsigned Depth = 0) const;
|
||||||
/// LowerArguments - This hook must be implemented to indicate how we should
|
|
||||||
/// lower the arguments for the specified function, into the specified DAG.
|
|
||||||
virtual std::vector<SDOperand>
|
|
||||||
LowerArguments(Function &F, SelectionDAG &DAG);
|
|
||||||
|
|
||||||
/// LowerCallTo - This hook lowers an abstract call to a function into an
|
/// LowerCallTo - This hook lowers an abstract call to a function into an
|
||||||
/// actual call.
|
/// actual call.
|
||||||
|
|||||||
Loading…
Reference in New Issue
Block a user