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https://github.com/RPCS3/llvm-mirror.git
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[MIPS GlobalISel] Legalize constants
Legalize s1, s8, s16 and s64 G_CONSTANT for MIPS32. Patch by Petar Avramovic. Differential Revision: https://reviews.llvm.org/D53077 llvm-svn: 344684
This commit is contained in:
Petar Jovanovic
parent
3e73839b39
commit
0a274e2e3b
@ -40,7 +40,9 @@ MipsLegalizerInfo::MipsLegalizerInfo(const MipsSubtarget &ST) {
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.minScalar(0, s32);
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getActionDefinitionsBuilder(G_CONSTANT)
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.legalFor({s32});
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.legalFor({s32})
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.minScalar(0, s32)
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.customFor({s64});
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getActionDefinitionsBuilder(G_GEP)
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.legalFor({{p0, s32}});
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@ -91,6 +93,27 @@ bool MipsLegalizerInfo::legalizeCustom(MachineInstr &MI,
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MI.eraseFromParent();
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break;
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}
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case G_CONSTANT: {
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unsigned Size = MRI.getType(MI.getOperand(0).getReg()).getSizeInBits();
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const LLT sHalf = LLT::scalar(Size / 2);
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const APInt &CImmValue = MI.getOperand(1).getCImm()->getValue();
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unsigned ResLow = MRI.createGenericVirtualRegister(sHalf);
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unsigned ResHigh = MRI.createGenericVirtualRegister(sHalf);
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MIRBuilder.buildConstant(
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ResLow, *ConstantInt::get(MI.getMF()->getFunction().getContext(),
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CImmValue.trunc(Size / 2)));
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MIRBuilder.buildConstant(
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ResHigh, *ConstantInt::get(MI.getMF()->getFunction().getContext(),
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CImmValue.lshr(Size / 2).trunc(Size / 2)));
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MIRBuilder.buildMerge(MI.getOperand(0).getReg(), {ResHigh, ResLow});
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MI.eraseFromParent();
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break;
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}
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default:
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return false;
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}
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164
test/CodeGen/Mips/GlobalISel/legalizer/constants.mir
Normal file
164
test/CodeGen/Mips/GlobalISel/legalizer/constants.mir
Normal file
@ -0,0 +1,164 @@
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# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
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# RUN: llc -O0 -mtriple=mipsel-linux-gnu -run-pass=legalizer -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=MIPS32
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--- |
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define void @any_i64() {entry: ret void}
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define void @any_i32() {entry: ret void}
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define void @signed_i16() {entry: ret void}
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define void @signed_i8() {entry: ret void}
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define void @unsigned_i16() {entry: ret void}
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define void @unsigned_i8() {entry: ret void}
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define void @i1_true() {entry: ret void}
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define void @i1_false() {entry: ret void}
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...
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---
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name: any_i64
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alignment: 2
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tracksRegLiveness: true
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body: |
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bb.1.entry:
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; MIPS32-LABEL: name: any_i64
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; MIPS32: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
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; MIPS32: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 -2147483648
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; MIPS32: $v0 = COPY [[C]](s32)
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; MIPS32: $v1 = COPY [[C1]](s32)
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; MIPS32: RetRA implicit $v0, implicit $v1
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%0:_(s64) = G_CONSTANT i64 -9223372036854775808
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%1:_(s32), %2:_(s32) = G_UNMERGE_VALUES %0(s64)
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$v0 = COPY %2(s32)
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$v1 = COPY %1(s32)
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RetRA implicit $v0, implicit $v1
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...
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---
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name: any_i32
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alignment: 2
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tracksRegLiveness: true
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body: |
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bb.1.entry:
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; MIPS32-LABEL: name: any_i32
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; MIPS32: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 -2147483648
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; MIPS32: $v0 = COPY [[C]](s32)
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; MIPS32: RetRA implicit $v0
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%0:_(s32) = G_CONSTANT i32 -2147483648
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$v0 = COPY %0(s32)
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RetRA implicit $v0
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...
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---
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name: signed_i16
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alignment: 2
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tracksRegLiveness: true
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body: |
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bb.1.entry:
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; MIPS32-LABEL: name: signed_i16
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; MIPS32: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 -32768
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; MIPS32: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
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; MIPS32: [[COPY:%[0-9]+]]:_(s32) = COPY [[C]](s32)
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; MIPS32: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY]], [[C1]]
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; MIPS32: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SHL]], [[C1]]
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; MIPS32: $v0 = COPY [[ASHR]](s32)
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; MIPS32: RetRA implicit $v0
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%0:_(s16) = G_CONSTANT i16 -32768
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%1:_(s32) = G_SEXT %0(s16)
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$v0 = COPY %1(s32)
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RetRA implicit $v0
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...
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---
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name: signed_i8
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alignment: 2
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tracksRegLiveness: true
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body: |
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bb.1.entry:
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; MIPS32-LABEL: name: signed_i8
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; MIPS32: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 -128
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; MIPS32: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 24
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; MIPS32: [[COPY:%[0-9]+]]:_(s32) = COPY [[C]](s32)
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; MIPS32: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY]], [[C1]]
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; MIPS32: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SHL]], [[C1]]
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; MIPS32: $v0 = COPY [[ASHR]](s32)
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; MIPS32: RetRA implicit $v0
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%0:_(s8) = G_CONSTANT i8 -128
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%1:_(s32) = G_SEXT %0(s8)
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$v0 = COPY %1(s32)
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RetRA implicit $v0
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...
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---
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name: unsigned_i16
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alignment: 2
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tracksRegLiveness: true
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body: |
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bb.1.entry:
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; MIPS32-LABEL: name: unsigned_i16
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; MIPS32: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 -32768
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; MIPS32: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
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; MIPS32: [[COPY:%[0-9]+]]:_(s32) = COPY [[C]](s32)
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; MIPS32: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY]], [[C1]]
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; MIPS32: $v0 = COPY [[AND]](s32)
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; MIPS32: RetRA implicit $v0
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%0:_(s16) = G_CONSTANT i16 -32768
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%1:_(s32) = G_ZEXT %0(s16)
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$v0 = COPY %1(s32)
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RetRA implicit $v0
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...
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---
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name: unsigned_i8
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alignment: 2
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tracksRegLiveness: true
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body: |
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bb.1.entry:
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; MIPS32-LABEL: name: unsigned_i8
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; MIPS32: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 -128
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; MIPS32: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
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; MIPS32: [[COPY:%[0-9]+]]:_(s32) = COPY [[C]](s32)
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; MIPS32: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY]], [[C1]]
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; MIPS32: $v0 = COPY [[AND]](s32)
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; MIPS32: RetRA implicit $v0
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%0:_(s8) = G_CONSTANT i8 -128
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%1:_(s32) = G_ZEXT %0(s8)
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$v0 = COPY %1(s32)
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RetRA implicit $v0
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...
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---
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name: i1_true
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alignment: 2
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tracksRegLiveness: true
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body: |
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bb.1.entry:
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; MIPS32-LABEL: name: i1_true
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; MIPS32: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 -1
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; MIPS32: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
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; MIPS32: [[COPY:%[0-9]+]]:_(s32) = COPY [[C]](s32)
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; MIPS32: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY]], [[C1]]
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; MIPS32: $v0 = COPY [[AND]](s32)
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; MIPS32: RetRA implicit $v0
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%0:_(s1) = G_CONSTANT i1 true
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%1:_(s32) = G_ZEXT %0(s1)
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$v0 = COPY %1(s32)
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RetRA implicit $v0
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...
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---
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name: i1_false
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alignment: 2
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tracksRegLiveness: true
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body: |
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bb.1.entry:
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; MIPS32-LABEL: name: i1_false
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; MIPS32: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
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; MIPS32: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
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; MIPS32: [[COPY:%[0-9]+]]:_(s32) = COPY [[C]](s32)
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; MIPS32: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY]], [[C1]]
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; MIPS32: $v0 = COPY [[AND]](s32)
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; MIPS32: RetRA implicit $v0
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%0:_(s1) = G_CONSTANT i1 false
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%1:_(s32) = G_ZEXT %0(s1)
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$v0 = COPY %1(s32)
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RetRA implicit $v0
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...
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108
test/CodeGen/Mips/GlobalISel/llvm-ir/constants.ll
Normal file
108
test/CodeGen/Mips/GlobalISel/llvm-ir/constants.ll
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@ -0,0 +1,108 @@
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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -O0 -mtriple=mipsel-linux-gnu -global-isel -verify-machineinstrs %s -o -| FileCheck %s -check-prefixes=MIPS32
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define i64 @any_i64() {
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; MIPS32-LABEL: any_i64:
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; MIPS32: # %bb.0: # %entry
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; MIPS32-NEXT: lui $1, 0
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; MIPS32-NEXT: ori $2, $1, 0
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; MIPS32-NEXT: lui $1, 32768
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; MIPS32-NEXT: ori $3, $1, 0
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; MIPS32-NEXT: jr $ra
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; MIPS32-NEXT: nop
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entry:
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ret i64 -9223372036854775808
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}
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define i32 @any_i32() {
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; MIPS32-LABEL: any_i32:
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; MIPS32: # %bb.0: # %entry
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; MIPS32-NEXT: lui $1, 32768
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; MIPS32-NEXT: ori $2, $1, 0
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; MIPS32-NEXT: jr $ra
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; MIPS32-NEXT: nop
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entry:
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ret i32 -2147483648
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}
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define signext i16 @signed_i16() {
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; MIPS32-LABEL: signed_i16:
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; MIPS32: # %bb.0: # %entry
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; MIPS32-NEXT: lui $1, 65535
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; MIPS32-NEXT: ori $1, $1, 32768
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; MIPS32-NEXT: sll $1, $1, 16
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; MIPS32-NEXT: sra $2, $1, 16
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; MIPS32-NEXT: jr $ra
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; MIPS32-NEXT: nop
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entry:
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ret i16 -32768
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}
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define signext i8 @signed_i8() {
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; MIPS32-LABEL: signed_i8:
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; MIPS32: # %bb.0: # %entry
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; MIPS32-NEXT: lui $1, 65535
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; MIPS32-NEXT: ori $1, $1, 65408
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; MIPS32-NEXT: sll $1, $1, 24
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; MIPS32-NEXT: sra $2, $1, 24
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; MIPS32-NEXT: jr $ra
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; MIPS32-NEXT: nop
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entry:
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ret i8 -128
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}
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define zeroext i16 @unsigned_i16() {
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; MIPS32-LABEL: unsigned_i16:
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; MIPS32: # %bb.0: # %entry
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; MIPS32-NEXT: lui $1, 65535
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; MIPS32-NEXT: ori $1, $1, 32768
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; MIPS32-NEXT: lui $2, 0
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; MIPS32-NEXT: ori $2, $2, 65535
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; MIPS32-NEXT: and $2, $1, $2
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; MIPS32-NEXT: jr $ra
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; MIPS32-NEXT: nop
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entry:
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ret i16 -32768
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}
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define zeroext i8 @unsigned_i8() {
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; MIPS32-LABEL: unsigned_i8:
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; MIPS32: # %bb.0: # %entry
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; MIPS32-NEXT: lui $1, 65535
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; MIPS32-NEXT: ori $1, $1, 65408
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; MIPS32-NEXT: lui $2, 0
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; MIPS32-NEXT: ori $2, $2, 255
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; MIPS32-NEXT: and $2, $1, $2
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; MIPS32-NEXT: jr $ra
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; MIPS32-NEXT: nop
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entry:
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ret i8 -128
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}
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define zeroext i1 @i1_true() {
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; MIPS32-LABEL: i1_true:
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; MIPS32: # %bb.0: # %entry
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; MIPS32-NEXT: lui $1, 65535
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; MIPS32-NEXT: ori $1, $1, 65535
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; MIPS32-NEXT: lui $2, 0
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; MIPS32-NEXT: ori $2, $2, 1
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; MIPS32-NEXT: and $2, $1, $2
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; MIPS32-NEXT: jr $ra
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; MIPS32-NEXT: nop
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entry:
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ret i1 true
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}
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define zeroext i1 @i1_false() {
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; MIPS32-LABEL: i1_false:
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; MIPS32: # %bb.0: # %entry
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; MIPS32-NEXT: lui $1, 0
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; MIPS32-NEXT: ori $1, $1, 0
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; MIPS32-NEXT: lui $2, 0
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; MIPS32-NEXT: ori $2, $2, 1
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; MIPS32-NEXT: and $2, $1, $2
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; MIPS32-NEXT: jr $ra
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; MIPS32-NEXT: nop
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entry:
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ret i1 false
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}
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