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PR14992 - Tablegen incorrectly converts ARM tLDMIA_UPD pseudo to tLDMIA

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Fixed bug in tablegen conversion when source pseudo instruction has
a different number of arguments than the destination instruction.

llvm-svn: 175066
This commit is contained in:
David Peixotto 2013-02-13 19:21:47 +00:00
parent 5ead8d3901
commit 0a3102166e
2 changed files with 29 additions and 0 deletions
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28
test/CodeGen/ARM/2013-01-21-PR14992.ll Normal file
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@ -0,0 +1,28 @@
;PR14492 - Tablegen incorrectly converts ARM tLDMIA_UPD pseudo to tLDMIA
;RUN: llc -mtriple=thumbv7 < %s | FileCheck -check-prefix=EXPECTED %s
;RUN: llc -mtriple=thumbv7 < %s | FileCheck %s
;EXPECTED: foo:
;CHECK: foo:
define i32 @foo(i32* %a) nounwind optsize {
entry:
%0 = load i32* %a, align 4, !tbaa !0
%arrayidx1 = getelementptr inbounds i32* %a, i32 1
%1 = load i32* %arrayidx1, align 4, !tbaa !0
%arrayidx2 = getelementptr inbounds i32* %a, i32 2
%2 = load i32* %arrayidx2, align 4, !tbaa !0
%add.ptr = getelementptr inbounds i32* %a, i32 3
;Make sure we do not have a duplicated register in the front of the reg list
;EXPECTED: ldm [[BASE:r[0-9]+]]!, {[[REG:r[0-9]+]], {{r[0-9]+}},
;CHECK-NOT: ldm [[BASE:r[0-9]+]]!, {[[REG:r[0-9]+]], [[REG]],
tail call void @bar(i32* %add.ptr) nounwind optsize
%add = add nsw i32 %1, %0
%add3 = add nsw i32 %add, %2
ret i32 %add3
}
declare void @bar(i32*) optsize
!0 = metadata !{metadata !"int", metadata !1}
!1 = metadata !{metadata !"omnipotent char", metadata !2}
!2 = metadata !{metadata !"Simple C/C++ TBAA"}

1
utils/TableGen/PseudoLoweringEmitter.cpp
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@ -252,6 +252,7 @@ void PseudoLoweringEmitter::emitLoweringEmitter(raw_ostream &o) {
MIOpNo += Dest.Operands[OpNo].MINumOperands;
}
if (Dest.Operands.isVariadic) {
MIOpNo = Source.Operands.size() + 1;
o << " // variable_ops\n";
o << " for (unsigned i = " << MIOpNo
<< ", e = MI->getNumOperands(); i != e; ++i)\n"