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[AArch64] Always use the version of computeKnownBits that returns a value. NFCI.
Continues the work started by @bogner in rL340594 to remove uses of the KnownBits output paramater version. llvm-svn: 349908
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@ -2087,8 +2087,7 @@ static bool isBitfieldPositioningOp(SelectionDAG *CurDAG, SDValue Op,
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(void)BitWidth;
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assert(BitWidth == 32 || BitWidth == 64);
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KnownBits Known;
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CurDAG->computeKnownBits(Op, Known);
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KnownBits Known = CurDAG->computeKnownBits(Op);
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// Non-zero in the sense that they're not provably zero, which is the key
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// point if we want to use this value
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@ -2167,8 +2166,7 @@ static bool tryBitfieldInsertOpFromOrAndImm(SDNode *N, SelectionDAG *CurDAG) {
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// Compute the Known Zero for the AND as this allows us to catch more general
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// cases than just looking for AND with imm.
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KnownBits Known;
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CurDAG->computeKnownBits(And, Known);
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KnownBits Known = CurDAG->computeKnownBits(And);
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// Non-zero in the sense that they're not provably zero, which is the key
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// point if we want to use this value.
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@ -2309,8 +2307,7 @@ static bool tryBitfieldInsertOpFromOr(SDNode *N, const APInt &UsefulBits,
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// This allows to catch more general case than just looking for
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// AND with imm. Indeed, simplify-demanded-bits may have removed
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// the AND instruction because it proves it was useless.
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KnownBits Known;
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CurDAG->computeKnownBits(OrOpd1Val, Known);
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KnownBits Known = CurDAG->computeKnownBits(OrOpd1Val);
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// Check if there is enough room for the second operand to appear
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// in the first one
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@ -993,8 +993,8 @@ void AArch64TargetLowering::computeKnownBitsForTargetNode(
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break;
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case AArch64ISD::CSEL: {
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KnownBits Known2;
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DAG.computeKnownBits(Op->getOperand(0), Known, Depth + 1);
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DAG.computeKnownBits(Op->getOperand(1), Known2, Depth + 1);
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Known = DAG.computeKnownBits(Op->getOperand(0), Depth + 1);
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Known2 = DAG.computeKnownBits(Op->getOperand(1), Depth + 1);
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Known.Zero &= Known2.Zero;
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Known.One &= Known2.One;
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break;
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@ -89,8 +89,7 @@ TEST_F(AArch64SelectionDAGTest, computeKnownBits_ZERO_EXTEND_VECTOR_INREG) {
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auto InVec = DAG->getConstant(0, Loc, InVecVT);
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auto Op = DAG->getNode(ISD::ZERO_EXTEND_VECTOR_INREG, Loc, OutVecVT, InVec);
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auto DemandedElts = APInt(2, 3);
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KnownBits Known;
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DAG->computeKnownBits(Op, Known, DemandedElts);
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KnownBits Known = DAG->computeKnownBits(Op, DemandedElts);
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EXPECT_TRUE(Known.isZero());
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}
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@ -105,8 +104,7 @@ TEST_F(AArch64SelectionDAGTest, computeKnownBits_EXTRACT_SUBVECTOR) {
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auto ZeroIdx = DAG->getConstant(0, Loc, IdxVT);
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auto Op = DAG->getNode(ISD::EXTRACT_SUBVECTOR, Loc, VecVT, Vec, ZeroIdx);
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auto DemandedElts = APInt(3, 7);
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KnownBits Known;
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DAG->computeKnownBits(Op, Known, DemandedElts);
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KnownBits Known = DAG->computeKnownBits(Op, DemandedElts);
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EXPECT_TRUE(Known.isZero());
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}
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