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[mips][ias] Further relax operands of certain assembly instructions
This patch adjusts the most relaxed predicate of immediate operands to accept immediate forms such as ~(0xf0000000|0x000f00000). Previously these forms would be accepted by GAS and rejected by IAS. This partially resolves PR/30383. Thanks to Sean Bruno for reporting the issue! Reviewers: slthakur, seanbruno Differential Revision: https://reviews.llvm.org/D29218 llvm-svn: 295965
This commit is contained in:
Simon Dardis
parent
9ca2feaac5
commit
0a7f7f003a
@ -2379,10 +2379,10 @@ MipsAsmParser::tryExpandInstruction(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out,
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return expandUxw(Inst, IDLoc, Out, STI) ? MER_Fail : MER_Success;
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case Mips::NORImm:
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return expandAliasImmediate(Inst, IDLoc, Out, STI) ? MER_Fail : MER_Success;
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case Mips::ADDi:
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case Mips::ADDiu:
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case Mips::SLTi:
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case Mips::SLTiu:
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case Mips::ADDi: case Mips::ADDi_MM:
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case Mips::ADDiu: case Mips::ADDiu_MM:
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case Mips::SLTi: case Mips::SLTi_MM:
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case Mips::SLTiu: case Mips::SLTiu_MM:
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if ((Inst.getNumOperands() == 3) && Inst.getOperand(0).isReg() &&
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Inst.getOperand(1).isReg() && Inst.getOperand(2).isImm()) {
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int64_t ImmValue = Inst.getOperand(2).getImm();
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@ -2392,9 +2392,9 @@ MipsAsmParser::tryExpandInstruction(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out,
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: MER_Success;
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}
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return MER_NotAMacro;
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case Mips::ANDi:
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case Mips::ORi:
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case Mips::XORi:
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case Mips::ANDi: case Mips::ANDi_MM:
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case Mips::ORi: case Mips::ORi_MM:
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case Mips::XORi: case Mips::XORi_MM:
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if ((Inst.getNumOperands() == 3) && Inst.getOperand(0).isReg() &&
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Inst.getOperand(1).isReg() && Inst.getOperand(2).isImm()) {
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int64_t ImmValue = Inst.getOperand(2).getImm();
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@ -3821,30 +3821,51 @@ bool MipsAsmParser::expandAliasImmediate(MCInst &Inst, SMLoc IDLoc,
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switch (FinalOpcode) {
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default:
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llvm_unreachable("unimplemented expansion");
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case (Mips::ADDi):
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case Mips::ADDi:
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FinalOpcode = Mips::ADD;
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break;
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case (Mips::ADDiu):
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case Mips::ADDiu:
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FinalOpcode = Mips::ADDu;
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break;
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case (Mips::ANDi):
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case Mips::ANDi:
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FinalOpcode = Mips::AND;
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break;
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case (Mips::NORImm):
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case Mips::NORImm:
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FinalOpcode = Mips::NOR;
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break;
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case (Mips::ORi):
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case Mips::ORi:
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FinalOpcode = Mips::OR;
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break;
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case (Mips::SLTi):
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case Mips::SLTi:
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FinalOpcode = Mips::SLT;
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break;
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case (Mips::SLTiu):
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case Mips::SLTiu:
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FinalOpcode = Mips::SLTu;
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break;
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case (Mips::XORi):
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case Mips::XORi:
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FinalOpcode = Mips::XOR;
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break;
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case Mips::ADDi_MM:
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FinalOpcode = Mips::ADD_MM;
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break;
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case Mips::ADDiu_MM:
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FinalOpcode = Mips::ADDu_MM;
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break;
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case Mips::ANDi_MM:
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FinalOpcode = Mips::AND_MM;
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break;
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case Mips::ORi_MM:
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FinalOpcode = Mips::OR_MM;
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break;
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case Mips::SLTi_MM:
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FinalOpcode = Mips::SLT_MM;
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break;
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case Mips::SLTiu_MM:
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FinalOpcode = Mips::SLTu_MM;
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break;
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case Mips::XORi_MM:
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FinalOpcode = Mips::XOR_MM;
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break;
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}
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if (FinalDstReg == Mips::NoRegister)
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@ -1136,12 +1136,6 @@ let Predicates = [InMicroMips] in {
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def : MipsInstAlias<
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"sgtu $rs, $rt",
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(SLTu_MM GPR32Opnd:$rs, GPR32Opnd:$rt, GPR32Opnd:$rs), 0>;
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def : MipsInstAlias<"slt $rs, $rt, $imm",
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(SLTi_MM GPR32Opnd:$rs, GPR32Opnd:$rt,
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simm32_relaxed:$imm), 0>;
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def : MipsInstAlias<"sltu $rs, $rt, $imm",
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(SLTiu_MM GPR32Opnd:$rs, GPR32Opnd:$rt,
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simm32_relaxed:$imm), 0>;
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def : MipsInstAlias<"sll $rd, $rt, $rs",
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(SLLV_MM GPR32Opnd:$rd, GPR32Opnd:$rt, GPR32Opnd:$rs), 0>;
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def : MipsInstAlias<"sra $rd, $rt, $rs",
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@ -1163,18 +1157,21 @@ let Predicates = [InMicroMips] in {
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def : MipsInstAlias<"rotr $rt, $imm",
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(ROTR_MM GPR32Opnd:$rt, GPR32Opnd:$rt, uimm5:$imm), 0>;
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def : MipsInstAlias<"syscall", (SYSCALL_MM 0), 1>;
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def : MipsInstAlias<"and $rs, $rt, $imm",
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(ANDi_MM GPR32Opnd:$rs, GPR32Opnd:$rt, simm16:$imm), 0>;
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def : MipsInstAlias<"and $rs, $imm",
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(ANDi_MM GPR32Opnd:$rs, GPR32Opnd:$rs, simm16:$imm), 0>;
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def : MipsInstAlias<"or $rs, $rt, $imm",
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(ORi_MM GPR32Opnd:$rs, GPR32Opnd:$rt, uimm16:$imm), 0>;
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def : MipsInstAlias<"or $rs, $imm",
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(ORi_MM GPR32Opnd:$rs, GPR32Opnd:$rs, uimm16:$imm), 0>;
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def : MipsInstAlias<"xor $rs, $rt, $imm",
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(XORi_MM GPR32Opnd:$rs, GPR32Opnd:$rt, uimm16:$imm), 0>;
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def : MipsInstAlias<"xor $rs, $imm",
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(XORi_MM GPR32Opnd:$rs, GPR32Opnd:$rs, uimm16:$imm), 0>;
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defm : OneOrTwoOperandMacroImmediateAlias<"add", ADDi_MM>;
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defm : OneOrTwoOperandMacroImmediateAlias<"addu", ADDiu_MM>;
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defm : OneOrTwoOperandMacroImmediateAlias<"and", ANDi_MM>;
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defm : OneOrTwoOperandMacroImmediateAlias<"or", ORi_MM>;
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defm : OneOrTwoOperandMacroImmediateAlias<"xor", XORi_MM>;
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defm : OneOrTwoOperandMacroImmediateAlias<"slt", SLTi_MM>;
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defm : OneOrTwoOperandMacroImmediateAlias<"sltu", SLTiu_MM>;
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def : MipsInstAlias<"not $rt, $rs",
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(NOR_MM GPR32Opnd:$rt, GPR32Opnd:$rs, ZERO), 0>;
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def : MipsInstAlias<"not $rt",
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@ -541,7 +541,7 @@ def UImm32CoercedAsmOperandClass : UImmAnyAsmOperandClass<33, []> {
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def SImm32RelaxedAsmOperandClass
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: SImmAsmOperandClass<32, [UImm32CoercedAsmOperandClass]> {
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let Name = "SImm32_Relaxed";
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let PredicateMethod = "isAnyImm<32>";
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let PredicateMethod = "isAnyImm<33>";
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let DiagnosticType = "SImm32_Relaxed";
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}
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def SImm32AsmOperandClass
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@ -2320,6 +2320,19 @@ def MULOUMacro : MipsAsmPseudoInst<(outs), (ins GPR32Opnd:$rd, GPR32Opnd:$rs,
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//===----------------------------------------------------------------------===//
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// Instruction aliases
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//===----------------------------------------------------------------------===//
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multiclass OneOrTwoOperandMacroImmediateAlias<string Memnomic,
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Instruction Opcode> {
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def : MipsInstAlias<!strconcat(Memnomic, " $rs, $rt, $imm"),
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(Opcode GPR32Opnd:$rs,
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GPR32Opnd:$rt,
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simm32_relaxed:$imm), 0>;
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def : MipsInstAlias<!strconcat(Memnomic, " $rs, $imm"),
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(Opcode GPR32Opnd:$rs,
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GPR32Opnd:$rs,
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simm32_relaxed:$imm), 0>;
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}
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def : MipsInstAlias<"move $dst, $src",
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(OR GPR32Opnd:$dst, GPR32Opnd:$src, ZERO), 1>,
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GPR_32 {
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@ -2332,26 +2345,7 @@ def : MipsInstAlias<"move $dst, $src",
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}
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def : MipsInstAlias<"bal $offset", (BGEZAL ZERO, brtarget:$offset), 0>,
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ISA_MIPS1_NOT_32R6_64R6;
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def : MipsInstAlias<
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"addu $rs, $rt, $imm",
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(ADDiu GPR32Opnd:$rs, GPR32Opnd:$rt, simm32_relaxed:$imm), 0>;
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def : MipsInstAlias<
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"addu $rs, $imm",
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(ADDiu GPR32Opnd:$rs, GPR32Opnd:$rs, simm32_relaxed:$imm), 0>;
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def : MipsInstAlias<
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"add $rs, $rt, $imm",
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(ADDi GPR32Opnd:$rs, GPR32Opnd:$rt, simm32_relaxed:$imm), 0>,
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ISA_MIPS1_NOT_32R6_64R6;
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def : MipsInstAlias<
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"add $rs, $imm",
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(ADDi GPR32Opnd:$rs, GPR32Opnd:$rs, simm32_relaxed:$imm), 0>,
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ISA_MIPS1_NOT_32R6_64R6;
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def : MipsInstAlias<
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"and $rs, $rt, $imm",
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(ANDi GPR32Opnd:$rs, GPR32Opnd:$rt, simm32_relaxed:$imm), 0>;
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def : MipsInstAlias<
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"and $rs, $imm",
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(ANDi GPR32Opnd:$rs, GPR32Opnd:$rs, simm32_relaxed:$imm), 0>;
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def : MipsInstAlias<"j $rs", (JR GPR32Opnd:$rs), 0>;
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let Predicates = [NotInMicroMips] in {
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def : MipsInstAlias<"jalr $rs", (JALR RA, GPR32Opnd:$rs), 0>;
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@ -2378,30 +2372,6 @@ let AdditionalPredicates = [NotInMicroMips] in {
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def : MipsInstAlias<
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"sgtu $$rs, $rt",
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(SLTu GPR32Opnd:$rs, GPR32Opnd:$rt, GPR32Opnd:$rs), 0>;
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def : MipsInstAlias<
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"slt $rs, $rt, $imm",
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(SLTi GPR32Opnd:$rs, GPR32Opnd:$rt, simm32_relaxed:$imm), 0>;
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def : MipsInstAlias<
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"sltu $rt, $rs, $imm",
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(SLTiu GPR32Opnd:$rt, GPR32Opnd:$rs, simm32_relaxed:$imm), 0>;
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def : MipsInstAlias<
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"and $rs, $rt, $imm",
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(ANDi GPR32Opnd:$rs, GPR32Opnd:$rt, simm32_relaxed:$imm), 0>;
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def : MipsInstAlias<
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"and $rs, $imm",
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(ANDi GPR32Opnd:$rs, GPR32Opnd:$rs, simm32_relaxed:$imm), 0>;
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def : MipsInstAlias<
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"xor $rs, $rt, $imm",
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(XORi GPR32Opnd:$rs, GPR32Opnd:$rt, simm32_relaxed:$imm), 0>;
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def : MipsInstAlias<
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"xor $rs, $imm",
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(XORi GPR32Opnd:$rs, GPR32Opnd:$rs, simm32_relaxed:$imm), 0>;
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def : MipsInstAlias<
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"or $rs, $rt, $imm",
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(ORi GPR32Opnd:$rs, GPR32Opnd:$rt, simm32_relaxed:$imm), 0>;
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def : MipsInstAlias<
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"or $rs, $imm",
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(ORi GPR32Opnd:$rs, GPR32Opnd:$rs, simm32_relaxed:$imm), 0>;
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def : MipsInstAlias<
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"not $rt, $rs",
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(NOR GPR32Opnd:$rt, GPR32Opnd:$rs, ZERO), 0>;
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@ -2409,6 +2379,20 @@ let AdditionalPredicates = [NotInMicroMips] in {
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"not $rt",
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(NOR GPR32Opnd:$rt, GPR32Opnd:$rt, ZERO), 0>;
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def : MipsInstAlias<"nop", (SLL ZERO, ZERO, 0), 1>;
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defm : OneOrTwoOperandMacroImmediateAlias<"add", ADDi>, ISA_MIPS1_NOT_32R6_64R6;
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defm : OneOrTwoOperandMacroImmediateAlias<"addu", ADDiu>;
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defm : OneOrTwoOperandMacroImmediateAlias<"and", ANDi>;
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defm : OneOrTwoOperandMacroImmediateAlias<"or", ORi>;
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defm : OneOrTwoOperandMacroImmediateAlias<"xor", XORi>;
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defm : OneOrTwoOperandMacroImmediateAlias<"slt", SLTi>;
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defm : OneOrTwoOperandMacroImmediateAlias<"sltu", SLTiu>;
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}
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def : MipsInstAlias<"mfc0 $rt, $rd", (MFC0 GPR32Opnd:$rt, COP0Opnd:$rd, 0), 0>;
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def : MipsInstAlias<"mtc0 $rt, $rd", (MTC0 COP0Opnd:$rd, GPR32Opnd:$rt, 0), 0>;
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@ -2517,8 +2501,10 @@ def JalOneReg : MipsAsmPseudoInst<(outs), (ins GPR32Opnd:$rs),
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"jal\t$rs"> ;
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def NORImm : MipsAsmPseudoInst<
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(outs), (ins GPR32Opnd:$rs, GPR32Opnd:$rt, simm32:$imm),
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"nor\t$rs, $rt, $imm"> ;
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(outs), (ins GPR32Opnd:$rs, GPR32Opnd:$rt, simm32_relaxed:$imm),
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"nor\t$rs, $rt, $imm">;
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def : MipsInstAlias<"nor\t$rs, $imm", (NORImm GPR32Opnd:$rs, GPR32Opnd:$rs,
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simm32_relaxed:$imm)>;
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let hasDelaySlot = 1, isCTI = 1 in {
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def BneImm : MipsAsmPseudoInst<(outs GPR32Opnd:$rt),
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@ -23,6 +23,10 @@ text_label:
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# CHECK: add $4, $4, $1 # encoding: [0x20,0x20,0x81,0x00]
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add $4, 0xFFFFFFFF
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# CHECK: addi $4, $4, -1 # encoding: [0xff,0xff,0x84,0x20]
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add $5, ~(0xf0000000|0x0f000000|0x000000f0)
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# CHECK: lui $1, 255 # encoding: [0xff,0x00,0x01,0x3c]
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# CHECK: ori $1, $1, 65295 # encoding: [0x0f,0xff,0x21,0x34]
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# CHECK: add $5, $5, $1 # encoding: [0x20,0x28,0xa1,0x00]
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add $4, $5, -0x80000000
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# CHECK: lui $4, 32768 # encoding: [0x00,0x80,0x04,0x3c]
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@ -43,6 +47,10 @@ text_label:
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# CHECK: add $4, $4, $5 # encoding: [0x20,0x20,0x85,0x00]
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add $4, $5, 0xFFFFFFFF
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# CHECK: addi $4, $5, -1 # encoding: [0xff,0xff,0xa4,0x20]
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add $4, $5, ~(0xf0000000|0x0f000000|0x000000f0)
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# CHECK: lui $4, 255 # encoding: [0xff,0x00,0x04,0x3c]
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# CHECK: ori $4, $4, 65295 # encoding: [0x0f,0xff,0x84,0x34]
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# CHECK: add $4, $4, $5 # encoding: [0x20,0x20,0x85,0x00]
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addu $4, -0x80000000
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# CHECK: lui $1, 32768 # encoding: [0x00,0x80,0x01,0x3c]
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@ -63,6 +71,10 @@ text_label:
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# CHECK: addu $4, $4, $1 # encoding: [0x21,0x20,0x81,0x00]
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addu $4, 0xFFFFFFFF
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# CHECK: addiu $4, $4, -1 # encoding: [0xff,0xff,0x84,0x24]
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addu $5, ~(0xf0000000|0x0f000000|0x000000f0)
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# CHECK: lui $1, 255 # encoding: [0xff,0x00,0x01,0x3c]
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# CHECK: ori $1, $1, 65295 # encoding: [0x0f,0xff,0x21,0x34]
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# CHECK: addu $5, $5, $1 # encoding: [0x21,0x28,0xa1,0x00]
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addu $4, $5, -0x80000000
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# CHECK: lui $4, 32768 # encoding: [0x00,0x80,0x04,0x3c]
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@ -83,6 +95,10 @@ text_label:
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# CHECK: addu $4, $4, $5 # encoding: [0x21,0x20,0x85,0x00]
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addu $4, $5, 0xFFFFFFFF
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# CHECK: addiu $4, $5, -1 # encoding: [0xff,0xff,0xa4,0x24]
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addu $4, $5, ~(0xf0000000|0x0f000000|0x000000f0)
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# CHECK: lui $4, 255 # encoding: [0xff,0x00,0x04,0x3c]
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# CHECK: ori $4, $4, 65295 # encoding: [0x0f,0xff,0x84,0x34]
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# CHECK: addu $4, $4, $5 # encoding: [0x21,0x20,0x85,0x00]
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and $4, -0x80000000
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# CHECK: lui $1, 32768 # encoding: [0x00,0x80,0x01,0x3c]
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@ -103,6 +119,10 @@ text_label:
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and $4, 0xFFFFFFFF
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# CHECK: addiu $1, $zero, -1 # encoding: [0xff,0xff,0x01,0x24]
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# CHECK: and $4, $4, $1 # encoding: [0x24,0x20,0x81,0x00]
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and $5, ~(0xf0000000|0x0f000000|0x000000f0)
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# CHECK: lui $1, 255 # encoding: [0xff,0x00,0x01,0x3c]
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# CHECK: ori $1, $1, 65295 # encoding: [0x0f,0xff,0x21,0x34]
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# CHECK: and $5, $5, $1 # encoding: [0x24,0x28,0xa1,0x00]
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and $4, $5, -0x80000000
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# CHECK: lui $4, 32768 # encoding: [0x00,0x80,0x04,0x3c]
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@ -123,6 +143,10 @@ text_label:
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# CHECK: and $4, $4, $5 # encoding: [0x24,0x20,0x85,0x00]
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and $4, $5, 0xFFFFFFFF
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# CHECK: addiu $4, $zero, -1 # encoding: [0xff,0xff,0x04,0x24]
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# CHECK: and $4, $4, $5 # encoding: [0x24,0x20,0x85,0x00]
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and $4, $5, ~(0xf0000000|0x0f000000|0x000000f0)
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# CHECK: lui $4, 255 # encoding: [0xff,0x00,0x04,0x3c]
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# CHECK: ori $4, $4, 65295 # encoding: [0x0f,0xff,0x84,0x34]
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# CHECK: and $4, $4, $5 # encoding: [0x24,0x20,0x85,0x00]
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nor $4, $5, 0
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@ -144,6 +168,34 @@ text_label:
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# CHECK: lui $4, 1 # encoding: [0x01,0x00,0x04,0x3c]
|
||||
# CHECK: ori $4, $4, 42405 # encoding: [0xa5,0xa5,0x84,0x34]
|
||||
# CHECK: nor $4, $4, $5 # encoding: [0x27,0x20,0x85,0x00]
|
||||
nor $4, ~(0xf0000000|0x0f000000|0x000000f0)
|
||||
# CHECK: lui $1, 255 # encoding: [0xff,0x00,0x01,0x3c]
|
||||
# CHECK: ori $1, $1, 65295 # encoding: [0x0f,0xff,0x21,0x34]
|
||||
# CHECK: nor $4, $4, $1 # encoding: [0x27,0x20,0x81,0x00]
|
||||
|
||||
nor $4, 0
|
||||
# CHECK: addiu $1, $zero, 0 # encoding: [0x00,0x00,0x01,0x24]
|
||||
# CHECK: nor $4, $4, $1 # encoding: [0x27,0x20,0x81,0x00]
|
||||
nor $4, 1
|
||||
# CHECK: addiu $1, $zero, 1 # encoding: [0x01,0x00,0x01,0x24]
|
||||
# CHECK: nor $4, $4, $1 # encoding: [0x27,0x20,0x81,0x00]
|
||||
nor $4, 0x8000
|
||||
# CHECK: ori $1, $zero, 32768 # encoding: [0x00,0x80,0x01,0x34]
|
||||
# CHECK: nor $4, $4, $1 # encoding: [0x27,0x20,0x81,0x00]
|
||||
nor $4, -0x8000
|
||||
# CHECK: addiu $1, $zero, -32768 # encoding: [0x00,0x80,0x01,0x24]
|
||||
# CHECK: nor $4, $4, $1 # encoding: [0x27,0x20,0x81,0x00]
|
||||
nor $4, 0x10000
|
||||
# CHECK: lui $1, 1 # encoding: [0x01,0x00,0x01,0x3c]
|
||||
# CHECK: nor $4, $4, $1 # encoding: [0x27,0x20,0x81,0x00]
|
||||
nor $4, 0x1a5a5
|
||||
# CHECK: lui $1, 1 # encoding: [0x01,0x00,0x01,0x3c]
|
||||
# CHECK: ori $1, $1, 42405 # encoding: [0xa5,0xa5,0x21,0x34]
|
||||
# CHECK: nor $4, $4, $1 # encoding: [0x27,0x20,0x81,0x00]
|
||||
nor $4, ~(0xf0000000|0x0f000000|0x000000f0)
|
||||
# CHECK: lui $1, 255 # encoding: [0xff,0x00,0x01,0x3c]
|
||||
# CHECK: ori $1, $1, 65295 # encoding: [0x0f,0xff,0x21,0x34]
|
||||
# CHECK: nor $4, $4, $1 # encoding: [0x27,0x20,0x81,0x00]
|
||||
|
||||
or $4, -0x80000000
|
||||
# CHECK: lui $1, 32768 # encoding: [0x00,0x80,0x01,0x3c]
|
||||
@ -165,6 +217,10 @@ text_label:
|
||||
or $4, 0xFFFFFFFF
|
||||
# CHECK: addiu $1, $zero, -1 # encoding: [0xff,0xff,0x01,0x24]
|
||||
# CHECK: or $4, $4, $1 # encoding: [0x25,0x20,0x81,0x00]
|
||||
or $5, ~(0xf0000000|0x0f000000|0x000000f0)
|
||||
# CHECK: lui $1, 255 # encoding: [0xff,0x00,0x01,0x3c]
|
||||
# CHECK: ori $1, $1, 65295 # encoding: [0x0f,0xff,0x21,0x34]
|
||||
# CHECK: or $5, $5, $1 # encoding: [0x25,0x28,0xa1,0x00]
|
||||
|
||||
or $4, $5, -0x80000000
|
||||
# CHECK: lui $4, 32768 # encoding: [0x00,0x80,0x04,0x3c]
|
||||
@ -185,6 +241,10 @@ text_label:
|
||||
# CHECK: or $4, $4, $5 # encoding: [0x25,0x20,0x85,0x00]
|
||||
or $4, $5, 0xFFFFFFFF
|
||||
# CHECK: addiu $4, $zero, -1 # encoding: [0xff,0xff,0x04,0x24]
|
||||
# CHECK: or $4, $4, $5 # encoding: [0x25,0x20,0x85,0x00]
|
||||
or $4, $5, ~(0xF0000000|0x0F000000|0x000000F0)
|
||||
# CHECK: lui $4, 255 # encoding: [0xff,0x00,0x04,0x3c]
|
||||
# CHECK: ori $4, $4, 65295 # encoding: [0x0f,0xff,0x84,0x34]
|
||||
# CHECK: or $4, $4, $5 # encoding: [0x25,0x20,0x85,0x00]
|
||||
|
||||
slt $4, $5, -0x80000000
|
||||
@ -205,6 +265,10 @@ text_label:
|
||||
# CHECK: slt $4, $4, $5 # encoding: [0x2a,0x20,0x85,0x00]
|
||||
slt $4, $5, 0xFFFFFFFF
|
||||
# CHECK: slti $4, $5, -1 # encoding: [0xff,0xff,0xa4,0x28]
|
||||
slt $4, $5, ~(0xf0000000|0x0f000000|0x000000f0)
|
||||
# CHECK: lui $4, 255 # encoding: [0xff,0x00,0x04,0x3c]
|
||||
# CHECK: ori $4, $4, 65295 # encoding: [0x0f,0xff,0x84,0x34]
|
||||
# CHECK: slt $4, $4, $5 # encoding: [0x2a,0x20,0x85,0x00]
|
||||
|
||||
sltu $4, $5, -0x80000000
|
||||
# CHECK: lui $4, 32768 # encoding: [0x00,0x80,0x04,0x3c]
|
||||
@ -224,6 +288,10 @@ text_label:
|
||||
# CHECK: sltu $4, $4, $5 # encoding: [0x2b,0x20,0x85,0x00]
|
||||
sltu $4, $5, 0xFFFFFFFF
|
||||
# CHECK: sltiu $4, $5, -1 # encoding: [0xff,0xff,0xa4,0x2c]
|
||||
sltu $4, $5, ~(0xf0000000|0x0f000000|0x000000f0)
|
||||
# CHECK: lui $4, 255 # encoding: [0xff,0x00,0x04,0x3c]
|
||||
# CHECK: ori $4, $4, 65295 # encoding: [0x0f,0xff,0x84,0x34]
|
||||
# CHECK: sltu $4, $4, $5 # encoding: [0x2b,0x20,0x85,0x00]
|
||||
|
||||
xor $4, -0x80000000
|
||||
# CHECK: lui $1, 32768 # encoding: [0x00,0x80,0x01,0x3c]
|
||||
@ -243,6 +311,10 @@ text_label:
|
||||
# CHECK: xor $4, $4, $1 # encoding: [0x26,0x20,0x81,0x00]
|
||||
xor $4, 0xFFFFFFFF
|
||||
# CHECK: addiu $1, $zero, -1 # encoding: [0xff,0xff,0x01,0x24]
|
||||
# CHECK: xor $4, $4, $1 # encoding: [0x26,0x20,0x81,0x00]
|
||||
xor $4, ~(0xf0000000|0x0f000000|0x000000f0)
|
||||
# CHECK: lui $1, 255 # encoding: [0xff,0x00,0x01,0x3c]
|
||||
# CHECK: ori $1, $1, 65295 # encoding: [0x0f,0xff,0x21,0x34]
|
||||
# CHECK: xor $4, $4, $1 # encoding: [0x26,0x20,0x81,0x00]
|
||||
|
||||
xor $4, $5, -0x80000000
|
||||
@ -254,7 +326,7 @@ text_label:
|
||||
# CHECK: xor $4, $4, $5 # encoding: [0x26,0x20,0x85,0x00]
|
||||
xor $4, $5, -0x8000
|
||||
# CHECK: addiu $4, $zero, -32768 # encoding: [0x00,0x80,0x04,0x24]
|
||||
# CHECK: xor $4, $4, $5 # encoding: [0x26,0x20,0x85,0x00]
|
||||
# CHECK: xor $4, $4, $5 # encoding: [0x26,0x20,0x85,0x00]
|
||||
xor $4, $5, 0
|
||||
# CHECK: xori $4, $5, 0 # encoding: [0x00,0x00,0xa4,0x38]
|
||||
xor $4, $5, 0xFFFF
|
||||
@ -264,4 +336,8 @@ text_label:
|
||||
# CHECK: xor $4, $4, $5 # encoding: [0x26,0x20,0x85,0x00]
|
||||
xor $4, $5, 0xFFFFFFFF
|
||||
# CHECK: addiu $4, $zero, -1 # encoding: [0xff,0xff,0x04,0x24]
|
||||
# CHECK: xor $4, $4, $5 # encoding: [0x26,0x20,0x85,0x00]
|
||||
xor $4, $5, ~(0xf0000000|0x0f000000|0x000000f0)
|
||||
# CHECK: lui $4, 255 # encoding: [0xff,0x00,0x04,0x3c]
|
||||
# CHECK: ori $4, $4, 65295 # encoding: [0x0f,0xff,0x84,0x34]
|
||||
# CHECK: xor $4, $4, $5 # encoding: [0x26,0x20,0x85,0x00]
|
||||
|
||||
Loading…
x
Reference in New Issue
Block a user