mirror of
https://github.com/RPCS3/llvm-mirror.git
synced 2024-10-20 03:23:01 +02:00
misched: Allow flags to disable hasInstrSchedModel/hasInstrItineraries for external users of TargetSchedule.
llvm-svn: 165564
This commit is contained in:
parent
54d088900c
commit
0a8af76cb4
@ -45,11 +45,11 @@ public:
|
|||||||
/// Return true if this machine model includes an instruction-level scheduling
|
/// Return true if this machine model includes an instruction-level scheduling
|
||||||
/// model. This is more detailed than the course grain IssueWidth and default
|
/// model. This is more detailed than the course grain IssueWidth and default
|
||||||
/// latency properties, but separate from the per-cycle itinerary data.
|
/// latency properties, but separate from the per-cycle itinerary data.
|
||||||
bool hasInstrSchedModel() const { return SchedModel.hasInstrSchedModel(); }
|
bool hasInstrSchedModel() const;
|
||||||
|
|
||||||
/// Return true if this machine model includes cycle-to-cycle itinerary
|
/// Return true if this machine model includes cycle-to-cycle itinerary
|
||||||
/// data. This models scheduling at each stage in the processor pipeline.
|
/// data. This models scheduling at each stage in the processor pipeline.
|
||||||
bool hasInstrItineraries() const { return !InstrItins.isEmpty(); }
|
bool hasInstrItineraries() const;
|
||||||
|
|
||||||
/// computeOperandLatency - Compute and return the latency of the given data
|
/// computeOperandLatency - Compute and return the latency of the given data
|
||||||
/// dependent def and use when the operand indices are already known. UseMI
|
/// dependent def and use when the operand indices are already known. UseMI
|
||||||
|
@ -27,6 +27,14 @@ static cl::opt<bool> EnableSchedModel("schedmodel", cl::Hidden, cl::init(true),
|
|||||||
static cl::opt<bool> EnableSchedItins("scheditins", cl::Hidden, cl::init(true),
|
static cl::opt<bool> EnableSchedItins("scheditins", cl::Hidden, cl::init(true),
|
||||||
cl::desc("Use InstrItineraryData for latency lookup"));
|
cl::desc("Use InstrItineraryData for latency lookup"));
|
||||||
|
|
||||||
|
bool TargetSchedModel::hasInstrSchedModel() const {
|
||||||
|
return EnableSchedModel && SchedModel.hasInstrSchedModel();
|
||||||
|
}
|
||||||
|
|
||||||
|
bool TargetSchedModel::hasInstrItineraries() const {
|
||||||
|
return EnableSchedItins && !InstrItins.isEmpty();
|
||||||
|
}
|
||||||
|
|
||||||
void TargetSchedModel::init(const MCSchedModel &sm,
|
void TargetSchedModel::init(const MCSchedModel &sm,
|
||||||
const TargetSubtargetInfo *sti,
|
const TargetSubtargetInfo *sti,
|
||||||
const TargetInstrInfo *tii) {
|
const TargetInstrInfo *tii) {
|
||||||
@ -47,14 +55,12 @@ int TargetSchedModel::getDefLatency(const MachineInstr *DefMI,
|
|||||||
if (FindMin) {
|
if (FindMin) {
|
||||||
// If MinLatency is invalid, then use the itinerary for MinLatency. If no
|
// If MinLatency is invalid, then use the itinerary for MinLatency. If no
|
||||||
// itinerary exists either, then use single cycle latency.
|
// itinerary exists either, then use single cycle latency.
|
||||||
if (SchedModel.MinLatency < 0
|
if (SchedModel.MinLatency < 0 && !hasInstrItineraries()) {
|
||||||
&& !(EnableSchedItins && hasInstrItineraries())) {
|
|
||||||
return 1;
|
return 1;
|
||||||
}
|
}
|
||||||
return SchedModel.MinLatency;
|
return SchedModel.MinLatency;
|
||||||
}
|
}
|
||||||
else if (!(EnableSchedModel && hasInstrSchedModel())
|
else if (!hasInstrSchedModel() && !hasInstrItineraries()) {
|
||||||
&& !(EnableSchedItins && hasInstrItineraries())) {
|
|
||||||
return TII->defaultDefLatency(&SchedModel, DefMI);
|
return TII->defaultDefLatency(&SchedModel, DefMI);
|
||||||
}
|
}
|
||||||
// ...operand lookup required
|
// ...operand lookup required
|
||||||
@ -123,7 +129,7 @@ unsigned TargetSchedModel::computeOperandLatency(
|
|||||||
if (DefLatency >= 0)
|
if (DefLatency >= 0)
|
||||||
return DefLatency;
|
return DefLatency;
|
||||||
|
|
||||||
if (EnableSchedItins && hasInstrItineraries()) {
|
if (hasInstrItineraries()) {
|
||||||
int OperLatency = 0;
|
int OperLatency = 0;
|
||||||
if (UseMI) {
|
if (UseMI) {
|
||||||
OperLatency =
|
OperLatency =
|
||||||
@ -145,7 +151,7 @@ unsigned TargetSchedModel::computeOperandLatency(
|
|||||||
TII->defaultDefLatency(&SchedModel, DefMI));
|
TII->defaultDefLatency(&SchedModel, DefMI));
|
||||||
return InstrLatency;
|
return InstrLatency;
|
||||||
}
|
}
|
||||||
assert(!FindMin && EnableSchedModel && hasInstrSchedModel() &&
|
assert(!FindMin && hasInstrSchedModel() &&
|
||||||
"Expected a SchedModel for this cpu");
|
"Expected a SchedModel for this cpu");
|
||||||
const MCSchedClassDesc *SCDesc = resolveSchedClass(DefMI);
|
const MCSchedClassDesc *SCDesc = resolveSchedClass(DefMI);
|
||||||
unsigned DefIdx = findDefIdx(DefMI, DefOperIdx);
|
unsigned DefIdx = findDefIdx(DefMI, DefOperIdx);
|
||||||
|
Loading…
Reference in New Issue
Block a user