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AArch64: Implement conditional compare sequence matching.
This is a new iteration of the reverted r238793 / http://reviews.llvm.org/D8232 which wrongly assumed that any and/or trees can be represented by conditional compare sequences, however there are some restrictions to that. This version fixes this and adds comments that explain exactly what types of and/or trees can actually be implemented as conditional compare sequences. Related to http://llvm.org/PR20927, rdar://18326194 Differential Revision: http://reviews.llvm.org/D10579 llvm-svn: 242436
This commit is contained in:
Matthias Braun
parent
d96b39afde
commit
0a9f87ba79
@ -76,6 +76,9 @@ cl::opt<bool> EnableAArch64ELFLocalDynamicTLSGeneration(
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cl::desc("Allow AArch64 Local Dynamic TLS code generation"),
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cl::init(false));
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/// Value type used for condition codes.
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static const MVT MVT_CC = MVT::i32;
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AArch64TargetLowering::AArch64TargetLowering(const TargetMachine &TM,
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const AArch64Subtarget &STI)
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: TargetLowering(TM), Subtarget(&STI) {
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@ -809,6 +812,9 @@ const char *AArch64TargetLowering::getTargetNodeName(unsigned Opcode) const {
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case AArch64ISD::ADCS: return "AArch64ISD::ADCS";
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case AArch64ISD::SBCS: return "AArch64ISD::SBCS";
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case AArch64ISD::ANDS: return "AArch64ISD::ANDS";
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case AArch64ISD::CCMP: return "AArch64ISD::CCMP";
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case AArch64ISD::CCMN: return "AArch64ISD::CCMN";
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case AArch64ISD::FCCMP: return "AArch64ISD::FCCMP";
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case AArch64ISD::FCMP: return "AArch64ISD::FCMP";
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case AArch64ISD::FMIN: return "AArch64ISD::FMIN";
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case AArch64ISD::FMAX: return "AArch64ISD::FMAX";
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@ -1167,14 +1173,224 @@ static SDValue emitComparison(SDValue LHS, SDValue RHS, ISD::CondCode CC,
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LHS = LHS.getOperand(0);
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}
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return DAG.getNode(Opcode, dl, DAG.getVTList(VT, MVT::i32), LHS, RHS)
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return DAG.getNode(Opcode, dl, DAG.getVTList(VT, MVT_CC), LHS, RHS)
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.getValue(1);
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}
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/// \defgroup AArch64CCMP CMP;CCMP matching
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///
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/// These functions deal with the formation of CMP;CCMP;... sequences.
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/// The CCMP/CCMN/FCCMP/FCCMPE instructions allow the conditional execution of
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/// a comparison. They set the NZCV flags to a predefined value if their
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/// predicate is false. This allows to express arbitrary conjunctions, for
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/// example "cmp 0 (and (setCA (cmp A)) (setCB (cmp B))))"
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/// expressed as:
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/// cmp A
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/// ccmp B, inv(CB), CA
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/// check for CB flags
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///
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/// In general we can create code for arbitrary "... (and (and A B) C)"
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/// sequences. We can also implement some "or" expressions, because "(or A B)"
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/// is equivalent to "not (and (not A) (not B))" and we can implement some
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/// negation operations:
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/// We can negate the results of a single comparison by inverting the flags
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/// used when the predicate fails and inverting the flags tested in the next
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/// instruction; We can also negate the results of the whole previous
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/// conditional compare sequence by inverting the flags tested in the next
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/// instruction. However there is no way to negate the result of a partial
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/// sequence.
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///
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/// Therefore on encountering an "or" expression we can negate the subtree on
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/// one side and have to be able to push the negate to the leafs of the subtree
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/// on the other side (see also the comments in code). As complete example:
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/// "or (or (setCA (cmp A)) (setCB (cmp B)))
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/// (and (setCC (cmp C)) (setCD (cmp D)))"
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/// is transformed to
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/// "not (and (not (and (setCC (cmp C)) (setCC (cmp D))))
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/// (and (not (setCA (cmp A)) (not (setCB (cmp B))))))"
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/// and implemented as:
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/// cmp C
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/// ccmp D, inv(CD), CC
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/// ccmp A, CA, inv(CD)
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/// ccmp B, CB, inv(CA)
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/// check for CB flags
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/// A counterexample is "or (and A B) (and C D)" which cannot be implemented
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/// by conditional compare sequences.
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/// @{
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/// Create a conditional comparison; Use CCMP, CCMN or FCCMP as apropriate.
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static SDValue emitConditionalComparison(SDValue LHS, SDValue RHS,
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ISD::CondCode CC, SDValue CCOp,
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SDValue Condition, unsigned NZCV,
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SDLoc DL, SelectionDAG &DAG) {
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unsigned Opcode = 0;
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if (LHS.getValueType().isFloatingPoint())
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Opcode = AArch64ISD::FCCMP;
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else if (RHS.getOpcode() == ISD::SUB) {
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SDValue SubOp0 = RHS.getOperand(0);
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if (const ConstantSDNode *SubOp0C = dyn_cast<ConstantSDNode>(SubOp0))
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if (SubOp0C->isNullValue() && (CC == ISD::SETEQ || CC == ISD::SETNE)) {
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// See emitComparison() on why we can only do this for SETEQ and SETNE.
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Opcode = AArch64ISD::CCMN;
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RHS = RHS.getOperand(1);
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}
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}
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if (Opcode == 0)
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Opcode = AArch64ISD::CCMP;
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SDValue NZCVOp = DAG.getConstant(NZCV, DL, MVT::i32);
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return DAG.getNode(Opcode, DL, MVT_CC, LHS, RHS, NZCVOp, Condition, CCOp);
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}
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/// Returns true if @p Val is a tree of AND/OR/SETCC operations.
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/// CanPushNegate is set to true if we can push a negate operation through
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/// the tree in a was that we are left with AND operations and negate operations
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/// at the leafs only. i.e. "not (or (or x y) z)" can be changed to
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/// "and (and (not x) (not y)) (not z)"; "not (or (and x y) z)" cannot be
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/// brought into such a form.
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static bool isConjunctionDisjunctionTree(const SDValue Val, bool &CanPushNegate,
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unsigned Depth = 0) {
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if (!Val.hasOneUse())
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return false;
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unsigned Opcode = Val->getOpcode();
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if (Opcode == ISD::SETCC) {
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CanPushNegate = true;
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return true;
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}
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// Protect against stack overflow.
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if (Depth > 15)
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return false;
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if (Opcode == ISD::AND || Opcode == ISD::OR) {
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SDValue O0 = Val->getOperand(0);
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SDValue O1 = Val->getOperand(1);
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bool CanPushNegateL;
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if (!isConjunctionDisjunctionTree(O0, CanPushNegateL, Depth+1))
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return false;
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bool CanPushNegateR;
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if (!isConjunctionDisjunctionTree(O1, CanPushNegateR, Depth+1))
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return false;
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// We cannot push a negate through an AND operation (it would become an OR),
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// we can however change a (not (or x y)) to (and (not x) (not y)) if we can
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// push the negate through the x/y subtrees.
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CanPushNegate = (Opcode == ISD::OR) && CanPushNegateL && CanPushNegateR;
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return true;
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}
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return false;
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}
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/// Emit conjunction or disjunction tree with the CMP/FCMP followed by a chain
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/// of CCMP/CFCMP ops. See @ref AArch64CCMP.
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/// Tries to transform the given i1 producing node @p Val to a series compare
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/// and conditional compare operations. @returns an NZCV flags producing node
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/// and sets @p OutCC to the flags that should be tested or returns SDValue() if
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/// transformation was not possible.
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/// On recursive invocations @p PushNegate may be set to true to have negation
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/// effects pushed to the tree leafs; @p Predicate is an NZCV flag predicate
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/// for the comparisons in the current subtree; @p Depth limits the search
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/// depth to avoid stack overflow.
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static SDValue emitConjunctionDisjunctionTree(SelectionDAG &DAG, SDValue Val,
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AArch64CC::CondCode &OutCC, bool PushNegate = false,
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SDValue CCOp = SDValue(), AArch64CC::CondCode Predicate = AArch64CC::AL,
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unsigned Depth = 0) {
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// We're at a tree leaf, produce a conditional comparison operation.
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unsigned Opcode = Val->getOpcode();
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if (Opcode == ISD::SETCC) {
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SDValue LHS = Val->getOperand(0);
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SDValue RHS = Val->getOperand(1);
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ISD::CondCode CC = cast<CondCodeSDNode>(Val->getOperand(2))->get();
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bool isInteger = LHS.getValueType().isInteger();
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if (PushNegate)
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CC = getSetCCInverse(CC, isInteger);
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SDLoc DL(Val);
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// Determine OutCC and handle FP special case.
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if (isInteger) {
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OutCC = changeIntCCToAArch64CC(CC);
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} else {
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assert(LHS.getValueType().isFloatingPoint());
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AArch64CC::CondCode ExtraCC;
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changeFPCCToAArch64CC(CC, OutCC, ExtraCC);
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// Surpisingly some floating point conditions can't be tested with a
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// single condition code. Construct an additional comparison in this case.
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// See comment below on how we deal with OR conditions.
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if (ExtraCC != AArch64CC::AL) {
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SDValue ExtraCmp;
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if (!CCOp.getNode())
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ExtraCmp = emitComparison(LHS, RHS, CC, DL, DAG);
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else {
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SDValue ConditionOp = DAG.getConstant(Predicate, DL, MVT_CC);
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// Note that we want the inverse of ExtraCC, so NZCV is not inversed.
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unsigned NZCV = AArch64CC::getNZCVToSatisfyCondCode(ExtraCC);
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ExtraCmp = emitConditionalComparison(LHS, RHS, CC, CCOp, ConditionOp,
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NZCV, DL, DAG);
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}
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CCOp = ExtraCmp;
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Predicate = AArch64CC::getInvertedCondCode(ExtraCC);
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OutCC = AArch64CC::getInvertedCondCode(OutCC);
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}
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}
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// Produce a normal comparison if we are first in the chain
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if (!CCOp.getNode())
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return emitComparison(LHS, RHS, CC, DL, DAG);
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// Otherwise produce a ccmp.
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SDValue ConditionOp = DAG.getConstant(Predicate, DL, MVT_CC);
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AArch64CC::CondCode InvOutCC = AArch64CC::getInvertedCondCode(OutCC);
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unsigned NZCV = AArch64CC::getNZCVToSatisfyCondCode(InvOutCC);
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return emitConditionalComparison(LHS, RHS, CC, CCOp, ConditionOp, NZCV, DL,
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DAG);
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} else if (Opcode != ISD::AND && Opcode != ISD::OR)
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return SDValue();
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assert((Opcode == ISD::OR || !PushNegate)
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&& "Can only push negate through OR operation");
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// Check if both sides can be transformed.
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SDValue LHS = Val->getOperand(0);
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SDValue RHS = Val->getOperand(1);
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bool CanPushNegateL;
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if (!isConjunctionDisjunctionTree(LHS, CanPushNegateL, Depth+1))
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return SDValue();
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bool CanPushNegateR;
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if (!isConjunctionDisjunctionTree(RHS, CanPushNegateR, Depth+1))
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return SDValue();
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// Do we need to negate our operands?
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bool NegateOperands = Opcode == ISD::OR;
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// We can negate the results of all previous operations by inverting the
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// predicate flags giving us a free negation for one side. For the other side
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// we need to be able to push the negation to the leafs of the tree.
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if (NegateOperands) {
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if (!CanPushNegateL && !CanPushNegateR)
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return SDValue();
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// Order the side where we can push the negate through to LHS.
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if (!CanPushNegateL && CanPushNegateR) {
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std::swap(LHS, RHS);
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CanPushNegateL = true;
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}
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}
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// Emit RHS. If we want to negate the tree we only need to push a negate
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// through if we are already in a PushNegate case, otherwise we can negate
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// the "flags to test" afterwards.
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AArch64CC::CondCode RHSCC;
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SDValue CmpR = emitConjunctionDisjunctionTree(DAG, RHS, RHSCC, PushNegate,
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CCOp, Predicate, Depth+1);
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if (NegateOperands && !PushNegate)
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RHSCC = AArch64CC::getInvertedCondCode(RHSCC);
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// Emit LHS. We must push the negate through if we need to negate it.
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SDValue CmpL = emitConjunctionDisjunctionTree(DAG, LHS, OutCC, NegateOperands,
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CmpR, RHSCC, Depth+1);
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// If we transformed an OR to and AND then we have to negate the result
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// (or absorb a PushNegate resulting in a double negation).
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if (Opcode == ISD::OR && !PushNegate)
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OutCC = AArch64CC::getInvertedCondCode(OutCC);
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return CmpL;
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}
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/// @}
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static SDValue getAArch64Cmp(SDValue LHS, SDValue RHS, ISD::CondCode CC,
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SDValue &AArch64cc, SelectionDAG &DAG, SDLoc dl) {
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SDValue Cmp;
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AArch64CC::CondCode AArch64CC;
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if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(RHS.getNode())) {
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EVT VT = RHS.getValueType();
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uint64_t C = RHSC->getZExtValue();
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@ -1229,47 +1445,56 @@ static SDValue getAArch64Cmp(SDValue LHS, SDValue RHS, ISD::CondCode CC,
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}
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}
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}
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// The imm operand of ADDS is an unsigned immediate, in the range 0 to 4095.
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// For the i8 operand, the largest immediate is 255, so this can be easily
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// encoded in the compare instruction. For the i16 operand, however, the
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// largest immediate cannot be encoded in the compare.
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// Therefore, use a sign extending load and cmn to avoid materializing the -1
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// constant. For example,
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// movz w1, #65535
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// ldrh w0, [x0, #0]
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// cmp w0, w1
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// >
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// ldrsh w0, [x0, #0]
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// cmn w0, #1
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// Fundamental, we're relying on the property that (zext LHS) == (zext RHS)
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// if and only if (sext LHS) == (sext RHS). The checks are in place to ensure
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// both the LHS and RHS are truely zero extended and to make sure the
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// transformation is profitable.
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SDValue Cmp;
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AArch64CC::CondCode AArch64CC;
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if ((CC == ISD::SETEQ || CC == ISD::SETNE) && isa<ConstantSDNode>(RHS)) {
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if ((cast<ConstantSDNode>(RHS)->getZExtValue() >> 16 == 0) &&
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isa<LoadSDNode>(LHS)) {
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if (cast<LoadSDNode>(LHS)->getExtensionType() == ISD::ZEXTLOAD &&
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cast<LoadSDNode>(LHS)->getMemoryVT() == MVT::i16 &&
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LHS.getNode()->hasNUsesOfValue(1, 0)) {
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int16_t ValueofRHS = cast<ConstantSDNode>(RHS)->getZExtValue();
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if (ValueofRHS < 0 && isLegalArithImmed(-ValueofRHS)) {
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SDValue SExt =
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DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, LHS.getValueType(), LHS,
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DAG.getValueType(MVT::i16));
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Cmp = emitComparison(SExt,
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DAG.getConstant(ValueofRHS, dl,
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RHS.getValueType()),
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CC, dl, DAG);
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AArch64CC = changeIntCCToAArch64CC(CC);
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AArch64cc = DAG.getConstant(AArch64CC, dl, MVT::i32);
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return Cmp;
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}
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const ConstantSDNode *RHSC = cast<ConstantSDNode>(RHS);
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// The imm operand of ADDS is an unsigned immediate, in the range 0 to 4095.
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// For the i8 operand, the largest immediate is 255, so this can be easily
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// encoded in the compare instruction. For the i16 operand, however, the
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// largest immediate cannot be encoded in the compare.
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// Therefore, use a sign extending load and cmn to avoid materializing the
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// -1 constant. For example,
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// movz w1, #65535
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// ldrh w0, [x0, #0]
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// cmp w0, w1
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// >
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// ldrsh w0, [x0, #0]
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// cmn w0, #1
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// Fundamental, we're relying on the property that (zext LHS) == (zext RHS)
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// if and only if (sext LHS) == (sext RHS). The checks are in place to
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// ensure both the LHS and RHS are truely zero extended and to make sure the
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// transformation is profitable.
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if ((RHSC->getZExtValue() >> 16 == 0) && isa<LoadSDNode>(LHS) &&
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cast<LoadSDNode>(LHS)->getExtensionType() == ISD::ZEXTLOAD &&
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cast<LoadSDNode>(LHS)->getMemoryVT() == MVT::i16 &&
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LHS.getNode()->hasNUsesOfValue(1, 0)) {
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int16_t ValueofRHS = cast<ConstantSDNode>(RHS)->getZExtValue();
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if (ValueofRHS < 0 && isLegalArithImmed(-ValueofRHS)) {
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SDValue SExt =
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DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, LHS.getValueType(), LHS,
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DAG.getValueType(MVT::i16));
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Cmp = emitComparison(SExt, DAG.getConstant(ValueofRHS, dl,
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RHS.getValueType()),
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CC, dl, DAG);
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AArch64CC = changeIntCCToAArch64CC(CC);
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}
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}
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if (!Cmp && (RHSC->isNullValue() || RHSC->isOne())) {
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if ((Cmp = emitConjunctionDisjunctionTree(DAG, LHS, AArch64CC))) {
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if ((CC == ISD::SETNE) ^ RHSC->isNullValue())
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AArch64CC = AArch64CC::getInvertedCondCode(AArch64CC);
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}
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}
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}
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Cmp = emitComparison(LHS, RHS, CC, dl, DAG);
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AArch64CC = changeIntCCToAArch64CC(CC);
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AArch64cc = DAG.getConstant(AArch64CC, dl, MVT::i32);
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if (!Cmp) {
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Cmp = emitComparison(LHS, RHS, CC, dl, DAG);
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AArch64CC = changeIntCCToAArch64CC(CC);
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}
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AArch64cc = DAG.getConstant(AArch64CC, dl, MVT_CC);
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return Cmp;
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}
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@ -9294,3 +9519,8 @@ bool AArch64TargetLowering::functionArgumentNeedsConsecutiveRegisters(
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Type *Ty, CallingConv::ID CallConv, bool isVarArg) const {
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return Ty->isArrayTy();
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}
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bool AArch64TargetLowering::shouldNormalizeToSelectSequence(LLVMContext &,
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EVT) const {
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return false;
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}
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@ -58,6 +58,11 @@ enum NodeType : unsigned {
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SBCS,
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ANDS,
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// Conditional compares. Operands: left,right,falsecc,cc,flags
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CCMP,
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CCMN,
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FCCMP,
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// Floating point comparison
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FCMP,
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@ -516,6 +521,8 @@ private:
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bool functionArgumentNeedsConsecutiveRegisters(Type *Ty,
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CallingConv::ID CallConv,
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bool isVarArg) const override;
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bool shouldNormalizeToSelectSequence(LLVMContext &, EVT) const override;
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};
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namespace AArch64 {
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||||
|
||||
@ -525,6 +525,13 @@ def imm0_31 : Operand<i64>, ImmLeaf<i64, [{
|
||||
let ParserMatchClass = Imm0_31Operand;
|
||||
}
|
||||
|
||||
// True if the 32-bit immediate is in the range [0,31]
|
||||
def imm32_0_31 : Operand<i32>, ImmLeaf<i32, [{
|
||||
return ((uint64_t)Imm) < 32;
|
||||
}]> {
|
||||
let ParserMatchClass = Imm0_31Operand;
|
||||
}
|
||||
|
||||
// imm0_15 predicate - True if the immediate is in the range [0,15]
|
||||
def imm0_15 : Operand<i64>, ImmLeaf<i64, [{
|
||||
return ((uint64_t)Imm) < 16;
|
||||
@ -542,7 +549,9 @@ def imm0_7 : Operand<i64>, ImmLeaf<i64, [{
|
||||
// imm32_0_15 predicate - True if the 32-bit immediate is in the range [0,15]
|
||||
def imm32_0_15 : Operand<i32>, ImmLeaf<i32, [{
|
||||
return ((uint32_t)Imm) < 16;
|
||||
}]>;
|
||||
}]> {
|
||||
let ParserMatchClass = Imm0_15Operand;
|
||||
}
|
||||
|
||||
// An arithmetic shifter operand:
|
||||
// {7-6} - shift type: 00 = lsl, 01 = lsr, 10 = asr
|
||||
@ -2108,9 +2117,12 @@ multiclass LogicalRegS<bits<2> opc, bit N, string mnemonic,
|
||||
//---
|
||||
|
||||
let mayLoad = 0, mayStore = 0, hasSideEffects = 0 in
|
||||
class BaseCondSetFlagsImm<bit op, RegisterClass regtype, string asm>
|
||||
: I<(outs), (ins regtype:$Rn, imm0_31:$imm, imm0_15:$nzcv, ccode:$cond),
|
||||
asm, "\t$Rn, $imm, $nzcv, $cond", "", []>,
|
||||
class BaseCondComparisonImm<bit op, RegisterClass regtype, ImmLeaf immtype,
|
||||
string mnemonic, SDNode OpNode>
|
||||
: I<(outs), (ins regtype:$Rn, immtype:$imm, imm32_0_15:$nzcv, ccode:$cond),
|
||||
mnemonic, "\t$Rn, $imm, $nzcv, $cond", "",
|
||||
[(set NZCV, (OpNode regtype:$Rn, immtype:$imm, (i32 imm:$nzcv),
|
||||
(i32 imm:$cond), NZCV))]>,
|
||||
Sched<[WriteI, ReadI]> {
|
||||
let Uses = [NZCV];
|
||||
let Defs = [NZCV];
|
||||
@ -2130,19 +2142,13 @@ class BaseCondSetFlagsImm<bit op, RegisterClass regtype, string asm>
|
||||
let Inst{3-0} = nzcv;
|
||||
}
|
||||
|
||||
multiclass CondSetFlagsImm<bit op, string asm> {
|
||||
def Wi : BaseCondSetFlagsImm<op, GPR32, asm> {
|
||||
let Inst{31} = 0;
|
||||
}
|
||||
def Xi : BaseCondSetFlagsImm<op, GPR64, asm> {
|
||||
let Inst{31} = 1;
|
||||
}
|
||||
}
|
||||
|
||||
let mayLoad = 0, mayStore = 0, hasSideEffects = 0 in
|
||||
class BaseCondSetFlagsReg<bit op, RegisterClass regtype, string asm>
|
||||
: I<(outs), (ins regtype:$Rn, regtype:$Rm, imm0_15:$nzcv, ccode:$cond),
|
||||
asm, "\t$Rn, $Rm, $nzcv, $cond", "", []>,
|
||||
class BaseCondComparisonReg<bit op, RegisterClass regtype, string mnemonic,
|
||||
SDNode OpNode>
|
||||
: I<(outs), (ins regtype:$Rn, regtype:$Rm, imm32_0_15:$nzcv, ccode:$cond),
|
||||
mnemonic, "\t$Rn, $Rm, $nzcv, $cond", "",
|
||||
[(set NZCV, (OpNode regtype:$Rn, regtype:$Rm, (i32 imm:$nzcv),
|
||||
(i32 imm:$cond), NZCV))]>,
|
||||
Sched<[WriteI, ReadI, ReadI]> {
|
||||
let Uses = [NZCV];
|
||||
let Defs = [NZCV];
|
||||
@ -2162,11 +2168,19 @@ class BaseCondSetFlagsReg<bit op, RegisterClass regtype, string asm>
|
||||
let Inst{3-0} = nzcv;
|
||||
}
|
||||
|
||||
multiclass CondSetFlagsReg<bit op, string asm> {
|
||||
def Wr : BaseCondSetFlagsReg<op, GPR32, asm> {
|
||||
multiclass CondComparison<bit op, string mnemonic, SDNode OpNode> {
|
||||
// immediate operand variants
|
||||
def Wi : BaseCondComparisonImm<op, GPR32, imm32_0_31, mnemonic, OpNode> {
|
||||
let Inst{31} = 0;
|
||||
}
|
||||
def Xr : BaseCondSetFlagsReg<op, GPR64, asm> {
|
||||
def Xi : BaseCondComparisonImm<op, GPR64, imm0_31, mnemonic, OpNode> {
|
||||
let Inst{31} = 1;
|
||||
}
|
||||
// register operand variants
|
||||
def Wr : BaseCondComparisonReg<op, GPR32, mnemonic, OpNode> {
|
||||
let Inst{31} = 0;
|
||||
}
|
||||
def Xr : BaseCondComparisonReg<op, GPR64, mnemonic, OpNode> {
|
||||
let Inst{31} = 1;
|
||||
}
|
||||
}
|
||||
@ -3974,11 +3988,14 @@ multiclass FPComparison<bit signalAllNans, string asm,
|
||||
//---
|
||||
|
||||
let mayLoad = 0, mayStore = 0, hasSideEffects = 0 in
|
||||
class BaseFPCondComparison<bit signalAllNans,
|
||||
RegisterClass regtype, string asm>
|
||||
: I<(outs), (ins regtype:$Rn, regtype:$Rm, imm0_15:$nzcv, ccode:$cond),
|
||||
asm, "\t$Rn, $Rm, $nzcv, $cond", "", []>,
|
||||
class BaseFPCondComparison<bit signalAllNans, RegisterClass regtype,
|
||||
string mnemonic, list<dag> pat>
|
||||
: I<(outs), (ins regtype:$Rn, regtype:$Rm, imm32_0_15:$nzcv, ccode:$cond),
|
||||
mnemonic, "\t$Rn, $Rm, $nzcv, $cond", "", pat>,
|
||||
Sched<[WriteFCmp]> {
|
||||
let Uses = [NZCV];
|
||||
let Defs = [NZCV];
|
||||
|
||||
bits<5> Rn;
|
||||
bits<5> Rm;
|
||||
bits<4> nzcv;
|
||||
@ -3994,16 +4011,18 @@ class BaseFPCondComparison<bit signalAllNans,
|
||||
let Inst{3-0} = nzcv;
|
||||
}
|
||||
|
||||
multiclass FPCondComparison<bit signalAllNans, string asm> {
|
||||
let Defs = [NZCV], Uses = [NZCV] in {
|
||||
def Srr : BaseFPCondComparison<signalAllNans, FPR32, asm> {
|
||||
multiclass FPCondComparison<bit signalAllNans, string mnemonic,
|
||||
SDPatternOperator OpNode = null_frag> {
|
||||
def Srr : BaseFPCondComparison<signalAllNans, FPR32, mnemonic,
|
||||
[(set NZCV, (OpNode (f32 FPR32:$Rn), (f32 FPR32:$Rm), (i32 imm:$nzcv),
|
||||
(i32 imm:$cond), NZCV))]> {
|
||||
let Inst{22} = 0;
|
||||
}
|
||||
|
||||
def Drr : BaseFPCondComparison<signalAllNans, FPR64, asm> {
|
||||
def Drr : BaseFPCondComparison<signalAllNans, FPR64, mnemonic,
|
||||
[(set NZCV, (OpNode (f64 FPR64:$Rn), (f64 FPR64:$Rm), (i32 imm:$nzcv),
|
||||
(i32 imm:$cond), NZCV))]> {
|
||||
let Inst{22} = 1;
|
||||
}
|
||||
} // Defs = [NZCV], Uses = [NZCV]
|
||||
}
|
||||
|
||||
//---
|
||||
|
||||
@ -66,6 +66,20 @@ def SDT_AArch64CSel : SDTypeProfile<1, 4,
|
||||
SDTCisSameAs<0, 2>,
|
||||
SDTCisInt<3>,
|
||||
SDTCisVT<4, i32>]>;
|
||||
def SDT_AArch64CCMP : SDTypeProfile<1, 5,
|
||||
[SDTCisVT<0, i32>,
|
||||
SDTCisInt<1>,
|
||||
SDTCisSameAs<1, 2>,
|
||||
SDTCisInt<3>,
|
||||
SDTCisInt<4>,
|
||||
SDTCisVT<5, i32>]>;
|
||||
def SDT_AArch64FCCMP : SDTypeProfile<1, 5,
|
||||
[SDTCisVT<0, i32>,
|
||||
SDTCisFP<1>,
|
||||
SDTCisSameAs<1, 2>,
|
||||
SDTCisInt<3>,
|
||||
SDTCisInt<4>,
|
||||
SDTCisVT<5, i32>]>;
|
||||
def SDT_AArch64FCmp : SDTypeProfile<0, 2,
|
||||
[SDTCisFP<0>,
|
||||
SDTCisSameAs<0, 1>]>;
|
||||
@ -160,6 +174,10 @@ def AArch64and_flag : SDNode<"AArch64ISD::ANDS", SDTBinaryArithWithFlagsOut,
|
||||
def AArch64adc_flag : SDNode<"AArch64ISD::ADCS", SDTBinaryArithWithFlagsInOut>;
|
||||
def AArch64sbc_flag : SDNode<"AArch64ISD::SBCS", SDTBinaryArithWithFlagsInOut>;
|
||||
|
||||
def AArch64ccmp : SDNode<"AArch64ISD::CCMP", SDT_AArch64CCMP>;
|
||||
def AArch64ccmn : SDNode<"AArch64ISD::CCMN", SDT_AArch64CCMP>;
|
||||
def AArch64fccmp : SDNode<"AArch64ISD::FCCMP", SDT_AArch64FCCMP>;
|
||||
|
||||
def AArch64threadpointer : SDNode<"AArch64ISD::THREAD_POINTER", SDTPtrLeaf>;
|
||||
|
||||
def AArch64fcmp : SDNode<"AArch64ISD::FCMP", SDT_AArch64FCmp>;
|
||||
@ -1020,13 +1038,10 @@ def : InstAlias<"uxth $dst, $src", (UBFMXri GPR64:$dst, GPR64:$src, 0, 15)>;
|
||||
def : InstAlias<"uxtw $dst, $src", (UBFMXri GPR64:$dst, GPR64:$src, 0, 31)>;
|
||||
|
||||
//===----------------------------------------------------------------------===//
|
||||
// Conditionally set flags instructions.
|
||||
// Conditional comparison instructions.
|
||||
//===----------------------------------------------------------------------===//
|
||||
defm CCMN : CondSetFlagsImm<0, "ccmn">;
|
||||
defm CCMP : CondSetFlagsImm<1, "ccmp">;
|
||||
|
||||
defm CCMN : CondSetFlagsReg<0, "ccmn">;
|
||||
defm CCMP : CondSetFlagsReg<1, "ccmp">;
|
||||
defm CCMN : CondComparison<0, "ccmn", AArch64ccmn>;
|
||||
defm CCMP : CondComparison<1, "ccmp", AArch64ccmp>;
|
||||
|
||||
//===----------------------------------------------------------------------===//
|
||||
// Conditional select instructions.
|
||||
@ -2556,7 +2571,7 @@ defm FCMP : FPComparison<0, "fcmp", AArch64fcmp>;
|
||||
//===----------------------------------------------------------------------===//
|
||||
|
||||
defm FCCMPE : FPCondComparison<1, "fccmpe">;
|
||||
defm FCCMP : FPCondComparison<0, "fccmp">;
|
||||
defm FCCMP : FPCondComparison<0, "fccmp", AArch64fccmp>;
|
||||
|
||||
//===----------------------------------------------------------------------===//
|
||||
// Floating point conditional select instruction.
|
||||
|
||||
@ -287,3 +287,99 @@ sw.bb.i.i:
|
||||
%code1.i.i.phi.trans.insert = getelementptr inbounds %str1, %str1* %0, i64 0, i32 0, i32 0, i64 16
|
||||
br label %sw.bb.i.i
|
||||
}
|
||||
|
||||
; CHECK-LABEL: select_and
|
||||
define i64 @select_and(i32 %w0, i32 %w1, i64 %x2, i64 %x3) {
|
||||
; CHECK: cmp w1, #5
|
||||
; CHECK-NEXT: ccmp w0, w1, #0, ne
|
||||
; CHECK-NEXT: csel x0, x2, x3, lt
|
||||
; CHECK-NEXT: ret
|
||||
%1 = icmp slt i32 %w0, %w1
|
||||
%2 = icmp ne i32 5, %w1
|
||||
%3 = and i1 %1, %2
|
||||
%sel = select i1 %3, i64 %x2, i64 %x3
|
||||
ret i64 %sel
|
||||
}
|
||||
|
||||
; CHECK-LABEL: select_or
|
||||
define i64 @select_or(i32 %w0, i32 %w1, i64 %x2, i64 %x3) {
|
||||
; CHECK: cmp w1, #5
|
||||
; CHECK-NEXT: ccmp w0, w1, #8, eq
|
||||
; CHECK-NEXT: csel x0, x2, x3, lt
|
||||
; CHECK-NEXT: ret
|
||||
%1 = icmp slt i32 %w0, %w1
|
||||
%2 = icmp ne i32 5, %w1
|
||||
%3 = or i1 %1, %2
|
||||
%sel = select i1 %3, i64 %x2, i64 %x3
|
||||
ret i64 %sel
|
||||
}
|
||||
|
||||
; CHECK-LABEL: select_complicated
|
||||
define i16 @select_complicated(double %v1, double %v2, i16 %a, i16 %b) {
|
||||
; CHECK: ldr [[REG:d[0-9]+]],
|
||||
; CHECK: fcmp d0, d2
|
||||
; CHECK-NEXT: fmov d2, #13.00000000
|
||||
; CHECK-NEXT: fccmp d1, d2, #4, ne
|
||||
; CHECK-NEXT: fccmp d0, d1, #1, ne
|
||||
; CHECK-NEXT: fccmp d0, d1, #4, vc
|
||||
; CEHCK-NEXT: csel w0, w0, w1, eq
|
||||
%1 = fcmp one double %v1, %v2
|
||||
%2 = fcmp oeq double %v2, 13.0
|
||||
%3 = fcmp oeq double %v1, 42.0
|
||||
%or0 = or i1 %2, %3
|
||||
%or1 = or i1 %1, %or0
|
||||
%sel = select i1 %or1, i16 %a, i16 %b
|
||||
ret i16 %sel
|
||||
}
|
||||
|
||||
; CHECK-LABEL: gccbug
|
||||
define i64 @gccbug(i64 %x0, i64 %x1) {
|
||||
; CHECK: cmp x1, #0
|
||||
; CHECK-NEXT: ccmp x0, #2, #0, eq
|
||||
; CHECK-NEXT: ccmp x0, #4, #4, ne
|
||||
; CHECK-NEXT: orr w[[REGNUM:[0-9]+]], wzr, #0x1
|
||||
; CHECK-NEXT: cinc x0, x[[REGNUM]], eq
|
||||
; CHECK-NEXT: ret
|
||||
%cmp0 = icmp eq i64 %x1, 0
|
||||
%cmp1 = icmp eq i64 %x0, 2
|
||||
%cmp2 = icmp eq i64 %x0, 4
|
||||
|
||||
%or = or i1 %cmp2, %cmp1
|
||||
%and = and i1 %or, %cmp0
|
||||
|
||||
%sel = select i1 %and, i64 2, i64 1
|
||||
ret i64 %sel
|
||||
}
|
||||
|
||||
; CHECK-LABEL: select_ororand
|
||||
define i32 @select_ororand(i32 %w0, i32 %w1, i32 %w2, i32 %w3) {
|
||||
; CHECK: cmp w3, #4
|
||||
; CHECK-NEXT: ccmp w2, #2, #0, gt
|
||||
; CHECK-NEXT: ccmp w1, #13, #2, ge
|
||||
; CHECK-NEXT: ccmp w0, #0, #4, ls
|
||||
; CHECK-NEXT: csel w0, w3, wzr, eq
|
||||
; CHECK-NEXT: ret
|
||||
%c0 = icmp eq i32 %w0, 0
|
||||
%c1 = icmp ugt i32 %w1, 13
|
||||
%c2 = icmp slt i32 %w2, 2
|
||||
%c4 = icmp sgt i32 %w3, 4
|
||||
%or = or i1 %c0, %c1
|
||||
%and = and i1 %c2, %c4
|
||||
%or1 = or i1 %or, %and
|
||||
%sel = select i1 %or1, i32 %w3, i32 0
|
||||
ret i32 %sel
|
||||
}
|
||||
|
||||
; CHECK-LABEL: select_noccmp
|
||||
define i64 @select_noccmp(i64 %v1, i64 %v2, i64 %v3, i64 %r) {
|
||||
; CHECK-NOT: CCMP
|
||||
%c0 = icmp slt i64 %v1, 0
|
||||
%c1 = icmp sgt i64 %v1, 13
|
||||
%c2 = icmp slt i64 %v3, 2
|
||||
%c4 = icmp sgt i64 %v3, 4
|
||||
%and0 = and i1 %c0, %c1
|
||||
%and1 = and i1 %c2, %c4
|
||||
%or = or i1 %and0, %and1
|
||||
%sel = select i1 %or, i64 0, i64 %r
|
||||
ret i64 %sel
|
||||
}
|
||||
|
||||
Loading…
Reference in New Issue
Block a user