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Remove IIC_DEFAULT from X86Schedule.td
All the instructions tagged with IIC_DEFAULT had nothing in common, and we already have a NoItineraries class to represent untagged instructions. llvm-svn: 177937
This commit is contained in:
Jakob Stoklund Olesen
parent
19c4788c8a
commit
0ac9ff5688
@ -209,47 +209,47 @@ class PseudoI<dag oops, dag iops, list<dag> pattern>
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}
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class I<bits<8> o, Format f, dag outs, dag ins, string asm,
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list<dag> pattern, InstrItinClass itin = IIC_DEFAULT,
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list<dag> pattern, InstrItinClass itin = NoItinerary,
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Domain d = GenericDomain>
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: X86Inst<o, f, NoImm, outs, ins, asm, itin, d> {
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let Pattern = pattern;
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let CodeSize = 3;
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}
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class Ii8 <bits<8> o, Format f, dag outs, dag ins, string asm,
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list<dag> pattern, InstrItinClass itin = IIC_DEFAULT,
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list<dag> pattern, InstrItinClass itin = NoItinerary,
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Domain d = GenericDomain>
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: X86Inst<o, f, Imm8, outs, ins, asm, itin, d> {
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let Pattern = pattern;
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let CodeSize = 3;
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}
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class Ii8PCRel<bits<8> o, Format f, dag outs, dag ins, string asm,
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list<dag> pattern, InstrItinClass itin = IIC_DEFAULT>
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list<dag> pattern, InstrItinClass itin = NoItinerary>
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: X86Inst<o, f, Imm8PCRel, outs, ins, asm, itin> {
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let Pattern = pattern;
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let CodeSize = 3;
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}
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class Ii16<bits<8> o, Format f, dag outs, dag ins, string asm,
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list<dag> pattern, InstrItinClass itin = IIC_DEFAULT>
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list<dag> pattern, InstrItinClass itin = NoItinerary>
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: X86Inst<o, f, Imm16, outs, ins, asm, itin> {
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let Pattern = pattern;
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let CodeSize = 3;
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}
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class Ii32<bits<8> o, Format f, dag outs, dag ins, string asm,
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list<dag> pattern, InstrItinClass itin = IIC_DEFAULT>
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list<dag> pattern, InstrItinClass itin = NoItinerary>
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: X86Inst<o, f, Imm32, outs, ins, asm, itin> {
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let Pattern = pattern;
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let CodeSize = 3;
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}
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class Ii16PCRel<bits<8> o, Format f, dag outs, dag ins, string asm,
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list<dag> pattern, InstrItinClass itin = IIC_DEFAULT>
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list<dag> pattern, InstrItinClass itin = NoItinerary>
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: X86Inst<o, f, Imm16PCRel, outs, ins, asm, itin> {
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let Pattern = pattern;
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let CodeSize = 3;
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}
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class Ii32PCRel<bits<8> o, Format f, dag outs, dag ins, string asm,
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list<dag> pattern, InstrItinClass itin = IIC_DEFAULT>
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list<dag> pattern, InstrItinClass itin = NoItinerary>
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: X86Inst<o, f, Imm32PCRel, outs, ins, asm, itin> {
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let Pattern = pattern;
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let CodeSize = 3;
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@ -258,12 +258,12 @@ class Ii32PCRel<bits<8> o, Format f, dag outs, dag ins, string asm,
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// FPStack Instruction Templates:
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// FPI - Floating Point Instruction template.
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class FPI<bits<8> o, Format F, dag outs, dag ins, string asm,
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InstrItinClass itin = IIC_DEFAULT>
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InstrItinClass itin = NoItinerary>
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: I<o, F, outs, ins, asm, [], itin> {}
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// FpI_ - Floating Point Pseudo Instruction template. Not Predicated.
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class FpI_<dag outs, dag ins, FPFormat fp, list<dag> pattern,
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InstrItinClass itin = IIC_DEFAULT>
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InstrItinClass itin = NoItinerary>
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: X86Inst<0, Pseudo, NoImm, outs, ins, "", itin> {
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let FPForm = fp;
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let Pattern = pattern;
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@ -276,14 +276,14 @@ class FpI_<dag outs, dag ins, FPFormat fp, list<dag> pattern,
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// Iseg32 - 16-bit segment selector, 32-bit offset
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class Iseg16 <bits<8> o, Format f, dag outs, dag ins, string asm,
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list<dag> pattern, InstrItinClass itin = IIC_DEFAULT>
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list<dag> pattern, InstrItinClass itin = NoItinerary>
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: X86Inst<o, f, Imm16, outs, ins, asm, itin> {
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let Pattern = pattern;
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let CodeSize = 3;
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}
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class Iseg32 <bits<8> o, Format f, dag outs, dag ins, string asm,
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list<dag> pattern, InstrItinClass itin = IIC_DEFAULT>
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list<dag> pattern, InstrItinClass itin = NoItinerary>
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: X86Inst<o, f, Imm32, outs, ins, asm, itin> {
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let Pattern = pattern;
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let CodeSize = 3;
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@ -293,7 +293,7 @@ def __xs : XS;
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// SI - SSE 1 & 2 scalar instructions
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class SI<bits<8> o, Format F, dag outs, dag ins, string asm,
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list<dag> pattern, InstrItinClass itin = IIC_DEFAULT>
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list<dag> pattern, InstrItinClass itin = NoItinerary>
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: I<o, F, outs, ins, asm, pattern, itin> {
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let Predicates = !if(hasVEXPrefix /* VEX */, [HasAVX],
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!if(!eq(Prefix, __xs.Prefix), [UseSSE1], [UseSSE2]));
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@ -304,7 +304,7 @@ class SI<bits<8> o, Format F, dag outs, dag ins, string asm,
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// SIi8 - SSE 1 & 2 scalar instructions
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class SIi8<bits<8> o, Format F, dag outs, dag ins, string asm,
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list<dag> pattern, InstrItinClass itin = IIC_DEFAULT>
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list<dag> pattern, InstrItinClass itin = NoItinerary>
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: Ii8<o, F, outs, ins, asm, pattern, itin> {
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let Predicates = !if(hasVEXPrefix /* VEX */, [HasAVX],
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!if(!eq(Prefix, __xs.Prefix), [UseSSE1], [UseSSE2]));
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@ -351,25 +351,25 @@ class PIi8<bits<8> o, Format F, dag outs, dag ins, string asm,
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// VPSI - SSE1 instructions with TB prefix in AVX form.
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class SSI<bits<8> o, Format F, dag outs, dag ins, string asm,
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list<dag> pattern, InstrItinClass itin = IIC_DEFAULT>
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list<dag> pattern, InstrItinClass itin = NoItinerary>
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: I<o, F, outs, ins, asm, pattern, itin>, XS, Requires<[UseSSE1]>;
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class SSIi8<bits<8> o, Format F, dag outs, dag ins, string asm,
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list<dag> pattern, InstrItinClass itin = IIC_DEFAULT>
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list<dag> pattern, InstrItinClass itin = NoItinerary>
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: Ii8<o, F, outs, ins, asm, pattern, itin>, XS, Requires<[UseSSE1]>;
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class PSI<bits<8> o, Format F, dag outs, dag ins, string asm,
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list<dag> pattern, InstrItinClass itin = IIC_DEFAULT>
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list<dag> pattern, InstrItinClass itin = NoItinerary>
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: I<o, F, outs, ins, asm, pattern, itin, SSEPackedSingle>, TB,
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Requires<[UseSSE1]>;
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class PSIi8<bits<8> o, Format F, dag outs, dag ins, string asm,
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list<dag> pattern, InstrItinClass itin = IIC_DEFAULT>
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list<dag> pattern, InstrItinClass itin = NoItinerary>
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: Ii8<o, F, outs, ins, asm, pattern, itin, SSEPackedSingle>, TB,
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Requires<[UseSSE1]>;
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class VSSI<bits<8> o, Format F, dag outs, dag ins, string asm,
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list<dag> pattern, InstrItinClass itin = IIC_DEFAULT>
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list<dag> pattern, InstrItinClass itin = NoItinerary>
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: I<o, F, outs, ins, !strconcat("v", asm), pattern, itin>, XS,
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Requires<[HasAVX]>;
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class VPSI<bits<8> o, Format F, dag outs, dag ins, string asm,
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list<dag> pattern, InstrItinClass itin = IIC_DEFAULT>
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list<dag> pattern, InstrItinClass itin = NoItinerary>
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: I<o, F, outs, ins, !strconcat("v", asm), pattern, itin, SSEPackedSingle>, TB,
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Requires<[HasAVX]>;
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@ -389,42 +389,42 @@ class VPSI<bits<8> o, Format F, dag outs, dag ins, string asm,
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// MMX operands.
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class SDI<bits<8> o, Format F, dag outs, dag ins, string asm,
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list<dag> pattern, InstrItinClass itin = IIC_DEFAULT>
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list<dag> pattern, InstrItinClass itin = NoItinerary>
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: I<o, F, outs, ins, asm, pattern, itin>, XD, Requires<[UseSSE2]>;
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class SDIi8<bits<8> o, Format F, dag outs, dag ins, string asm,
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list<dag> pattern, InstrItinClass itin = IIC_DEFAULT>
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list<dag> pattern, InstrItinClass itin = NoItinerary>
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: Ii8<o, F, outs, ins, asm, pattern, itin>, XD, Requires<[UseSSE2]>;
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class S2SI<bits<8> o, Format F, dag outs, dag ins, string asm,
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list<dag> pattern, InstrItinClass itin = IIC_DEFAULT>
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list<dag> pattern, InstrItinClass itin = NoItinerary>
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: I<o, F, outs, ins, asm, pattern, itin>, XS, Requires<[UseSSE2]>;
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class S2SIi8<bits<8> o, Format F, dag outs, dag ins, string asm,
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list<dag> pattern, InstrItinClass itin = IIC_DEFAULT>
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list<dag> pattern, InstrItinClass itin = NoItinerary>
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: Ii8<o, F, outs, ins, asm, pattern>, XS, Requires<[UseSSE2]>;
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class PDI<bits<8> o, Format F, dag outs, dag ins, string asm,
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list<dag> pattern, InstrItinClass itin = IIC_DEFAULT>
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list<dag> pattern, InstrItinClass itin = NoItinerary>
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: I<o, F, outs, ins, asm, pattern, itin, SSEPackedDouble>, TB, OpSize,
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Requires<[UseSSE2]>;
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class PDIi8<bits<8> o, Format F, dag outs, dag ins, string asm,
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list<dag> pattern, InstrItinClass itin = IIC_DEFAULT>
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list<dag> pattern, InstrItinClass itin = NoItinerary>
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: Ii8<o, F, outs, ins, asm, pattern, itin, SSEPackedDouble>, TB, OpSize,
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Requires<[UseSSE2]>;
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class VSDI<bits<8> o, Format F, dag outs, dag ins, string asm,
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list<dag> pattern, InstrItinClass itin = IIC_DEFAULT>
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list<dag> pattern, InstrItinClass itin = NoItinerary>
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: I<o, F, outs, ins, !strconcat("v", asm), pattern, itin>, XD,
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Requires<[HasAVX]>;
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class VS2SI<bits<8> o, Format F, dag outs, dag ins, string asm,
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list<dag> pattern, InstrItinClass itin = IIC_DEFAULT>
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list<dag> pattern, InstrItinClass itin = NoItinerary>
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: I<o, F, outs, ins, !strconcat("v", asm), pattern, itin>, XS,
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Requires<[HasAVX]>;
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class VPDI<bits<8> o, Format F, dag outs, dag ins, string asm,
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list<dag> pattern, InstrItinClass itin = IIC_DEFAULT>
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list<dag> pattern, InstrItinClass itin = NoItinerary>
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: I<o, F, outs, ins, !strconcat("v", asm), pattern, itin, SSEPackedDouble>, TB,
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OpSize, Requires<[HasAVX]>;
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class MMXSDIi8<bits<8> o, Format F, dag outs, dag ins, string asm,
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list<dag> pattern, InstrItinClass itin = IIC_DEFAULT>
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list<dag> pattern, InstrItinClass itin = NoItinerary>
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: Ii8<o, F, outs, ins, asm, pattern, itin>, XD, Requires<[HasSSE2]>;
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class MMXS2SIi8<bits<8> o, Format F, dag outs, dag ins, string asm,
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list<dag> pattern, InstrItinClass itin = IIC_DEFAULT>
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list<dag> pattern, InstrItinClass itin = NoItinerary>
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: Ii8<o, F, outs, ins, asm, pattern>, XS, Requires<[HasSSE2]>;
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// SSE3 Instruction Templates:
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@ -434,15 +434,15 @@ class MMXS2SIi8<bits<8> o, Format F, dag outs, dag ins, string asm,
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// S3DI - SSE3 instructions with XD prefix.
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class S3SI<bits<8> o, Format F, dag outs, dag ins, string asm,
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list<dag> pattern, InstrItinClass itin = IIC_DEFAULT>
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list<dag> pattern, InstrItinClass itin = NoItinerary>
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: I<o, F, outs, ins, asm, pattern, itin, SSEPackedSingle>, XS,
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Requires<[UseSSE3]>;
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class S3DI<bits<8> o, Format F, dag outs, dag ins, string asm,
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list<dag> pattern, InstrItinClass itin = IIC_DEFAULT>
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list<dag> pattern, InstrItinClass itin = NoItinerary>
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: I<o, F, outs, ins, asm, pattern, itin, SSEPackedDouble>, XD,
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Requires<[UseSSE3]>;
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class S3I<bits<8> o, Format F, dag outs, dag ins, string asm,
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list<dag> pattern, InstrItinClass itin = IIC_DEFAULT>
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list<dag> pattern, InstrItinClass itin = NoItinerary>
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: I<o, F, outs, ins, asm, pattern, itin, SSEPackedDouble>, TB, OpSize,
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Requires<[UseSSE3]>;
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@ -459,19 +459,19 @@ class S3I<bits<8> o, Format F, dag outs, dag ins, string asm,
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// classes. They need to be enabled even if AVX is enabled.
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class SS38I<bits<8> o, Format F, dag outs, dag ins, string asm,
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list<dag> pattern, InstrItinClass itin = IIC_DEFAULT>
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list<dag> pattern, InstrItinClass itin = NoItinerary>
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: I<o, F, outs, ins, asm, pattern, itin, SSEPackedInt>, T8,
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Requires<[UseSSSE3]>;
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class SS3AI<bits<8> o, Format F, dag outs, dag ins, string asm,
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list<dag> pattern, InstrItinClass itin = IIC_DEFAULT>
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list<dag> pattern, InstrItinClass itin = NoItinerary>
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: Ii8<o, F, outs, ins, asm, pattern, itin, SSEPackedInt>, TA,
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Requires<[UseSSSE3]>;
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class MMXSS38I<bits<8> o, Format F, dag outs, dag ins, string asm,
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list<dag> pattern, InstrItinClass itin = IIC_DEFAULT>
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list<dag> pattern, InstrItinClass itin = NoItinerary>
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: I<o, F, outs, ins, asm, pattern, itin, SSEPackedInt>, T8,
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Requires<[HasSSSE3]>;
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class MMXSS3AI<bits<8> o, Format F, dag outs, dag ins, string asm,
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list<dag> pattern, InstrItinClass itin = IIC_DEFAULT>
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list<dag> pattern, InstrItinClass itin = NoItinerary>
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: Ii8<o, F, outs, ins, asm, pattern, itin, SSEPackedInt>, TA,
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Requires<[HasSSSE3]>;
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@ -481,11 +481,11 @@ class MMXSS3AI<bits<8> o, Format F, dag outs, dag ins, string asm,
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// SS41AIi8 - SSE 4.1 instructions with TA prefix and ImmT == Imm8.
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//
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class SS48I<bits<8> o, Format F, dag outs, dag ins, string asm,
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list<dag> pattern, InstrItinClass itin = IIC_DEFAULT>
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list<dag> pattern, InstrItinClass itin = NoItinerary>
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: I<o, F, outs, ins, asm, pattern, itin, SSEPackedInt>, T8,
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Requires<[UseSSE41]>;
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class SS4AIi8<bits<8> o, Format F, dag outs, dag ins, string asm,
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list<dag> pattern, InstrItinClass itin = IIC_DEFAULT>
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list<dag> pattern, InstrItinClass itin = NoItinerary>
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: Ii8<o, F, outs, ins, asm, pattern, itin, SSEPackedInt>, TA,
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Requires<[UseSSE41]>;
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@ -493,19 +493,19 @@ class SS4AIi8<bits<8> o, Format F, dag outs, dag ins, string asm,
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//
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// SS428I - SSE 4.2 instructions with T8 prefix.
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class SS428I<bits<8> o, Format F, dag outs, dag ins, string asm,
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list<dag> pattern, InstrItinClass itin = IIC_DEFAULT>
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list<dag> pattern, InstrItinClass itin = NoItinerary>
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: I<o, F, outs, ins, asm, pattern, itin, SSEPackedInt>, T8,
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Requires<[UseSSE42]>;
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// SS42FI - SSE 4.2 instructions with T8XD prefix.
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// NOTE: 'HasSSE42' is used as SS42FI is only used for CRC32 insns.
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class SS42FI<bits<8> o, Format F, dag outs, dag ins, string asm,
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list<dag> pattern, InstrItinClass itin = IIC_DEFAULT>
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list<dag> pattern, InstrItinClass itin = NoItinerary>
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: I<o, F, outs, ins, asm, pattern, itin>, T8XD, Requires<[HasSSE42]>;
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// SS42AI = SSE 4.2 instructions with TA prefix
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class SS42AI<bits<8> o, Format F, dag outs, dag ins, string asm,
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list<dag> pattern, InstrItinClass itin = IIC_DEFAULT>
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list<dag> pattern, InstrItinClass itin = NoItinerary>
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: Ii8<o, F, outs, ins, asm, pattern, itin, SSEPackedInt>, TA,
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Requires<[UseSSE42]>;
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@ -515,11 +515,11 @@ class SS42AI<bits<8> o, Format F, dag outs, dag ins, string asm,
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// AVX8I - AVX instructions with T8 and OpSize prefix.
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// AVXAIi8 - AVX instructions with TA, OpSize prefix and ImmT = Imm8.
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class AVX8I<bits<8> o, Format F, dag outs, dag ins, string asm,
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list<dag> pattern, InstrItinClass itin = IIC_DEFAULT>
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list<dag> pattern, InstrItinClass itin = NoItinerary>
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: I<o, F, outs, ins, asm, pattern, itin, SSEPackedInt>, T8, OpSize,
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Requires<[HasAVX]>;
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class AVXAIi8<bits<8> o, Format F, dag outs, dag ins, string asm,
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list<dag> pattern, InstrItinClass itin = IIC_DEFAULT>
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list<dag> pattern, InstrItinClass itin = NoItinerary>
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: Ii8<o, F, outs, ins, asm, pattern, itin, SSEPackedInt>, TA, OpSize,
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Requires<[HasAVX]>;
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@ -529,11 +529,11 @@ class AVXAIi8<bits<8> o, Format F, dag outs, dag ins, string asm,
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// AVX28I - AVX2 instructions with T8 and OpSize prefix.
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// AVX2AIi8 - AVX2 instructions with TA, OpSize prefix and ImmT = Imm8.
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class AVX28I<bits<8> o, Format F, dag outs, dag ins, string asm,
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list<dag> pattern, InstrItinClass itin = IIC_DEFAULT>
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list<dag> pattern, InstrItinClass itin = NoItinerary>
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: I<o, F, outs, ins, asm, pattern, itin, SSEPackedInt>, T8, OpSize,
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Requires<[HasAVX2]>;
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class AVX2AIi8<bits<8> o, Format F, dag outs, dag ins, string asm,
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list<dag> pattern, InstrItinClass itin = IIC_DEFAULT>
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list<dag> pattern, InstrItinClass itin = NoItinerary>
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: Ii8<o, F, outs, ins, asm, pattern, itin, SSEPackedInt>, TA, OpSize,
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Requires<[HasAVX2]>;
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@ -542,53 +542,53 @@ class AVX2AIi8<bits<8> o, Format F, dag outs, dag ins, string asm,
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// AES8I
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// These use the same encoding as the SSE4.2 T8 and TA encodings.
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class AES8I<bits<8> o, Format F, dag outs, dag ins, string asm,
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list<dag>pattern, InstrItinClass itin = IIC_DEFAULT>
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list<dag>pattern, InstrItinClass itin = NoItinerary>
|
||||
: I<o, F, outs, ins, asm, pattern, itin, SSEPackedInt>, T8,
|
||||
Requires<[HasAES]>;
|
||||
|
||||
class AESAI<bits<8> o, Format F, dag outs, dag ins, string asm,
|
||||
list<dag> pattern, InstrItinClass itin = IIC_DEFAULT>
|
||||
list<dag> pattern, InstrItinClass itin = NoItinerary>
|
||||
: Ii8<o, F, outs, ins, asm, pattern, itin, SSEPackedInt>, TA,
|
||||
Requires<[HasAES]>;
|
||||
|
||||
// PCLMUL Instruction Templates
|
||||
class PCLMULIi8<bits<8> o, Format F, dag outs, dag ins, string asm,
|
||||
list<dag>pattern, InstrItinClass itin = IIC_DEFAULT>
|
||||
list<dag>pattern, InstrItinClass itin = NoItinerary>
|
||||
: Ii8<o, F, outs, ins, asm, pattern, itin, SSEPackedInt>, TA,
|
||||
OpSize, Requires<[HasPCLMUL]>;
|
||||
|
||||
class AVXPCLMULIi8<bits<8> o, Format F, dag outs, dag ins, string asm,
|
||||
list<dag>pattern, InstrItinClass itin = IIC_DEFAULT>
|
||||
list<dag>pattern, InstrItinClass itin = NoItinerary>
|
||||
: Ii8<o, F, outs, ins, asm, pattern, itin, SSEPackedInt>, TA,
|
||||
OpSize, VEX_4V, Requires<[HasAVX, HasPCLMUL]>;
|
||||
|
||||
// FMA3 Instruction Templates
|
||||
class FMA3<bits<8> o, Format F, dag outs, dag ins, string asm,
|
||||
list<dag>pattern, InstrItinClass itin = IIC_DEFAULT>
|
||||
list<dag>pattern, InstrItinClass itin = NoItinerary>
|
||||
: I<o, F, outs, ins, asm, pattern, itin>, T8,
|
||||
OpSize, VEX_4V, Requires<[HasFMA]>;
|
||||
|
||||
// FMA4 Instruction Templates
|
||||
class FMA4<bits<8> o, Format F, dag outs, dag ins, string asm,
|
||||
list<dag>pattern, InstrItinClass itin = IIC_DEFAULT>
|
||||
list<dag>pattern, InstrItinClass itin = NoItinerary>
|
||||
: Ii8<o, F, outs, ins, asm, pattern, itin>, TA,
|
||||
OpSize, VEX_4V, VEX_I8IMM, Requires<[HasFMA4]>;
|
||||
|
||||
// XOP 2, 3 and 4 Operand Instruction Template
|
||||
class IXOP<bits<8> o, Format F, dag outs, dag ins, string asm,
|
||||
list<dag> pattern, InstrItinClass itin = IIC_DEFAULT>
|
||||
list<dag> pattern, InstrItinClass itin = NoItinerary>
|
||||
: I<o, F, outs, ins, asm, pattern, itin, SSEPackedDouble>,
|
||||
XOP, XOP9, Requires<[HasXOP]>;
|
||||
|
||||
// XOP 2, 3 and 4 Operand Instruction Templates with imm byte
|
||||
class IXOPi8<bits<8> o, Format F, dag outs, dag ins, string asm,
|
||||
list<dag> pattern, InstrItinClass itin = IIC_DEFAULT>
|
||||
list<dag> pattern, InstrItinClass itin = NoItinerary>
|
||||
: Ii8<o, F, outs, ins, asm, pattern, itin, SSEPackedDouble>,
|
||||
XOP, XOP8, Requires<[HasXOP]>;
|
||||
|
||||
// XOP 5 operand instruction (VEX encoding!)
|
||||
class IXOP5<bits<8> o, Format F, dag outs, dag ins, string asm,
|
||||
list<dag>pattern, InstrItinClass itin = IIC_DEFAULT>
|
||||
list<dag>pattern, InstrItinClass itin = NoItinerary>
|
||||
: Ii8<o, F, outs, ins, asm, pattern, itin, SSEPackedInt>, TA,
|
||||
OpSize, VEX_4V, VEX_I8IMM, Requires<[HasXOP]>;
|
||||
|
||||
@ -596,33 +596,33 @@ class IXOP5<bits<8> o, Format F, dag outs, dag ins, string asm,
|
||||
//
|
||||
|
||||
class RI<bits<8> o, Format F, dag outs, dag ins, string asm,
|
||||
list<dag> pattern, InstrItinClass itin = IIC_DEFAULT>
|
||||
list<dag> pattern, InstrItinClass itin = NoItinerary>
|
||||
: I<o, F, outs, ins, asm, pattern, itin>, REX_W;
|
||||
class RIi8 <bits<8> o, Format F, dag outs, dag ins, string asm,
|
||||
list<dag> pattern, InstrItinClass itin = IIC_DEFAULT>
|
||||
list<dag> pattern, InstrItinClass itin = NoItinerary>
|
||||
: Ii8<o, F, outs, ins, asm, pattern, itin>, REX_W;
|
||||
class RIi32 <bits<8> o, Format F, dag outs, dag ins, string asm,
|
||||
list<dag> pattern, InstrItinClass itin = IIC_DEFAULT>
|
||||
list<dag> pattern, InstrItinClass itin = NoItinerary>
|
||||
: Ii32<o, F, outs, ins, asm, pattern, itin>, REX_W;
|
||||
|
||||
class RIi64<bits<8> o, Format f, dag outs, dag ins, string asm,
|
||||
list<dag> pattern, InstrItinClass itin = IIC_DEFAULT>
|
||||
list<dag> pattern, InstrItinClass itin = NoItinerary>
|
||||
: X86Inst<o, f, Imm64, outs, ins, asm, itin>, REX_W {
|
||||
let Pattern = pattern;
|
||||
let CodeSize = 3;
|
||||
}
|
||||
|
||||
class RSSI<bits<8> o, Format F, dag outs, dag ins, string asm,
|
||||
list<dag> pattern, InstrItinClass itin = IIC_DEFAULT>
|
||||
list<dag> pattern, InstrItinClass itin = NoItinerary>
|
||||
: SSI<o, F, outs, ins, asm, pattern, itin>, REX_W;
|
||||
class RSDI<bits<8> o, Format F, dag outs, dag ins, string asm,
|
||||
list<dag> pattern, InstrItinClass itin = IIC_DEFAULT>
|
||||
list<dag> pattern, InstrItinClass itin = NoItinerary>
|
||||
: SDI<o, F, outs, ins, asm, pattern, itin>, REX_W;
|
||||
class RPDI<bits<8> o, Format F, dag outs, dag ins, string asm,
|
||||
list<dag> pattern, InstrItinClass itin = IIC_DEFAULT>
|
||||
list<dag> pattern, InstrItinClass itin = NoItinerary>
|
||||
: PDI<o, F, outs, ins, asm, pattern, itin>, REX_W;
|
||||
class VRPDI<bits<8> o, Format F, dag outs, dag ins, string asm,
|
||||
list<dag> pattern, InstrItinClass itin = IIC_DEFAULT>
|
||||
list<dag> pattern, InstrItinClass itin = NoItinerary>
|
||||
: VPDI<o, F, outs, ins, asm, pattern, itin>, VEX_W;
|
||||
|
||||
// MMX Instruction templates
|
||||
@ -636,23 +636,23 @@ class VRPDI<bits<8> o, Format F, dag outs, dag ins, string asm,
|
||||
// MMXID - MMX instructions with XD prefix.
|
||||
// MMXIS - MMX instructions with XS prefix.
|
||||
class MMXI<bits<8> o, Format F, dag outs, dag ins, string asm,
|
||||
list<dag> pattern, InstrItinClass itin = IIC_DEFAULT>
|
||||
list<dag> pattern, InstrItinClass itin = NoItinerary>
|
||||
: I<o, F, outs, ins, asm, pattern, itin>, TB, Requires<[HasMMX]>;
|
||||
class MMXI64<bits<8> o, Format F, dag outs, dag ins, string asm,
|
||||
list<dag> pattern, InstrItinClass itin = IIC_DEFAULT>
|
||||
list<dag> pattern, InstrItinClass itin = NoItinerary>
|
||||
: I<o, F, outs, ins, asm, pattern, itin>, TB, Requires<[HasMMX,In64BitMode]>;
|
||||
class MMXRI<bits<8> o, Format F, dag outs, dag ins, string asm,
|
||||
list<dag> pattern, InstrItinClass itin = IIC_DEFAULT>
|
||||
list<dag> pattern, InstrItinClass itin = NoItinerary>
|
||||
: I<o, F, outs, ins, asm, pattern, itin>, TB, REX_W, Requires<[HasMMX]>;
|
||||
class MMX2I<bits<8> o, Format F, dag outs, dag ins, string asm,
|
||||
list<dag> pattern, InstrItinClass itin = IIC_DEFAULT>
|
||||
list<dag> pattern, InstrItinClass itin = NoItinerary>
|
||||
: I<o, F, outs, ins, asm, pattern, itin>, TB, OpSize, Requires<[HasMMX]>;
|
||||
class MMXIi8<bits<8> o, Format F, dag outs, dag ins, string asm,
|
||||
list<dag> pattern, InstrItinClass itin = IIC_DEFAULT>
|
||||
list<dag> pattern, InstrItinClass itin = NoItinerary>
|
||||
: Ii8<o, F, outs, ins, asm, pattern, itin>, TB, Requires<[HasMMX]>;
|
||||
class MMXID<bits<8> o, Format F, dag outs, dag ins, string asm,
|
||||
list<dag> pattern, InstrItinClass itin = IIC_DEFAULT>
|
||||
list<dag> pattern, InstrItinClass itin = NoItinerary>
|
||||
: Ii8<o, F, outs, ins, asm, pattern, itin>, XD, Requires<[HasMMX]>;
|
||||
class MMXIS<bits<8> o, Format F, dag outs, dag ins, string asm,
|
||||
list<dag> pattern, InstrItinClass itin = IIC_DEFAULT>
|
||||
list<dag> pattern, InstrItinClass itin = NoItinerary>
|
||||
: Ii8<o, F, outs, ins, asm, pattern, itin>, XS, Requires<[HasMMX]>;
|
||||
|
||||
@ -174,11 +174,11 @@ multiclass sse12_cvt_pint_3addr<bits<8> opc, RegisterClass SrcRC,
|
||||
PatFrag ld_frag, string asm, Domain d> {
|
||||
def irr : PI<opc, MRMSrcReg, (outs DstRC:$dst),(ins DstRC:$src1, SrcRC:$src2),
|
||||
asm, [(set DstRC:$dst, (Int DstRC:$src1, SrcRC:$src2))],
|
||||
IIC_DEFAULT, d>;
|
||||
NoItinerary, d>;
|
||||
def irm : PI<opc, MRMSrcMem, (outs DstRC:$dst),
|
||||
(ins DstRC:$src1, x86memop:$src2), asm,
|
||||
[(set DstRC:$dst, (Int DstRC:$src1, (ld_frag addr:$src2)))],
|
||||
IIC_DEFAULT, d>;
|
||||
NoItinerary, d>;
|
||||
}
|
||||
|
||||
//===----------------------------------------------------------------------===//
|
||||
|
||||
@ -232,13 +232,13 @@ multiclass sse12_fp_packed_logical_rm<bits<8> opc, RegisterClass RC, Domain d,
|
||||
!if(Is2Addr,
|
||||
!strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
|
||||
!strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
|
||||
pat_rr, IIC_DEFAULT, d>,
|
||||
pat_rr, NoItinerary, d>,
|
||||
Sched<[WriteVecLogic]>;
|
||||
def rm : PI<opc, MRMSrcMem, (outs RC:$dst), (ins RC:$src1, x86memop:$src2),
|
||||
!if(Is2Addr,
|
||||
!strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
|
||||
!strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
|
||||
pat_rm, IIC_DEFAULT, d>,
|
||||
pat_rm, NoItinerary, d>,
|
||||
Sched<[WriteVecLogicLd, ReadAfterLd]>;
|
||||
}
|
||||
|
||||
@ -6839,7 +6839,7 @@ multiclass SS41I_quaternary_int_avx<bits<8> opc, string OpcodeStr,
|
||||
!strconcat(OpcodeStr,
|
||||
"\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
|
||||
[(set RC:$dst, (IntId RC:$src1, RC:$src2, RC:$src3))],
|
||||
IIC_DEFAULT, SSEPackedInt>, OpSize, TA, VEX_4V, VEX_I8IMM;
|
||||
NoItinerary, SSEPackedInt>, OpSize, TA, VEX_4V, VEX_I8IMM;
|
||||
|
||||
def rm : Ii8<opc, MRMSrcMem, (outs RC:$dst),
|
||||
(ins RC:$src1, x86memop:$src2, RC:$src3),
|
||||
@ -6848,7 +6848,7 @@ multiclass SS41I_quaternary_int_avx<bits<8> opc, string OpcodeStr,
|
||||
[(set RC:$dst,
|
||||
(IntId RC:$src1, (bitconvert (mem_frag addr:$src2)),
|
||||
RC:$src3))],
|
||||
IIC_DEFAULT, SSEPackedInt>, OpSize, TA, VEX_4V, VEX_I8IMM;
|
||||
NoItinerary, SSEPackedInt>, OpSize, TA, VEX_4V, VEX_I8IMM;
|
||||
}
|
||||
|
||||
let Predicates = [HasAVX] in {
|
||||
|
||||
@ -91,7 +91,6 @@ def WriteMicrocoded : SchedWrite;
|
||||
|
||||
//===----------------------------------------------------------------------===//
|
||||
// Instruction Itinerary classes used for X86
|
||||
def IIC_DEFAULT : InstrItinClass;
|
||||
def IIC_ALU_MEM : InstrItinClass;
|
||||
def IIC_ALU_NONMEM : InstrItinClass;
|
||||
def IIC_LEA : InstrItinClass;
|
||||
|
||||
@ -33,7 +33,6 @@ def AtomItineraries : ProcessorItineraries<
|
||||
// InstrItinData<class, [InstrStage<N, [P0], 0>, InstrStage<N, [P1]>] >,
|
||||
//
|
||||
// Default is 1 cycle, port0 or port1
|
||||
InstrItinData<IIC_DEFAULT, [InstrStage<1, [Port0, Port1]>] >,
|
||||
InstrItinData<IIC_ALU_MEM, [InstrStage<1, [Port0]>] >,
|
||||
InstrItinData<IIC_ALU_NONMEM, [InstrStage<1, [Port0, Port1]>] >,
|
||||
InstrItinData<IIC_LEA, [InstrStage<1, [Port1]>] >,
|
||||
|
||||
Loading…
x
Reference in New Issue
Block a user