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[InstCombine] don't form select from bitcasted logic ops if bitcasts have >1 use
This isn't a sure thing (are 2 extra bitcasts less expensive than a logic op?), but we'll try to err on the conservative side by going with the case that has less IR instructions. Note: This question came up in http://reviews.llvm.org/D22114 , but this part is independent of that patch proposal, so I'm making this small change ahead of that one. See also: http://reviews.llvm.org/rL274926 llvm-svn: 274932
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@ -1619,8 +1619,8 @@ static Value *matchSelectFromAndOr(Value *A, Value *C, Value *B, Value *D,
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// through its bitcast and the corresponding bitcast of the 'not' condition.
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Type *OrigType = A->getType();
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Value *SrcA, *SrcB;
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if (match(A, m_BitCast(m_Value(SrcA))) &&
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match(B, m_BitCast(m_Value(SrcB)))) {
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if (match(A, m_OneUse(m_BitCast(m_Value(SrcA)))) &&
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match(B, m_OneUse(m_BitCast(m_Value(SrcB))))) {
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A = SrcA;
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B = SrcB;
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}
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@ -265,15 +265,14 @@ define <2 x i64> @bitcast_select_swap7(<4 x i1> %cmp, <2 x double> %a, <2 x doub
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define <2 x i64> @bitcast_select_multi_uses(<4 x i1> %cmp, <2 x i64> %a, <2 x i64> %b) {
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; CHECK-LABEL: @bitcast_select_multi_uses(
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; CHECK-NEXT: [[SEXT:%.*]] = sext <4 x i1> %cmp to <4 x i32>
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; CHECK-NEXT: [[BC1:%.*]] = bitcast <4 x i32> [[SEXT]] to <2 x i64>
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; CHECK-NEXT: [[AND1:%.*]] = and <2 x i64> [[BC1]], %a
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; CHECK-NEXT: [[NEG:%.*]] = xor <4 x i32> [[SEXT]], <i32 -1, i32 -1, i32 -1, i32 -1>
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; CHECK-NEXT: [[BC2:%.*]] = bitcast <4 x i32> [[NEG]] to <2 x i64>
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; CHECK-NEXT: [[AND2:%.*]] = and <2 x i64> [[BC2]], %b
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; CHECK-NEXT: [[TMP1:%.*]] = bitcast <2 x i64> %a to <4 x i32>
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; CHECK-NEXT: [[TMP2:%.*]] = bitcast <2 x i64> %b to <4 x i32>
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; CHECK-NEXT: [[TMP3:%.*]] = select <4 x i1> %cmp, <4 x i32> [[TMP1]], <4 x i32> [[TMP2]]
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; CHECK-NEXT: [[TMP4:%.*]] = bitcast <4 x i32> [[TMP3]] to <2 x i64>
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; CHECK-NEXT: [[OR:%.*]] = or <2 x i64> [[AND2]], [[AND1]]
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; CHECK-NEXT: [[ADD:%.*]] = add <2 x i64> [[AND2]], [[BC2]]
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; CHECK-NEXT: [[SUB:%.*]] = sub <2 x i64> [[TMP4]], [[ADD]]
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; CHECK-NEXT: [[SUB:%.*]] = sub <2 x i64> [[OR]], [[ADD]]
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; CHECK-NEXT: ret <2 x i64> [[SUB]]
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;
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%sext = sext <4 x i1> %cmp to <4 x i32>
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