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[X86] Rename the rb form of scalar ADD/SUB/MUL/DIV to include _Int since they can only be selected by intrinsics.

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llvm-svn: 320283
This commit is contained in:
Craig Topper 2017-12-10 04:07:28 +00:00
parent 919288edf2
commit 0b0595cce7
3 changed files with 20 additions and 20 deletions
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4
lib/Target/X86/X86InstrAVX512.td
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@ -4778,7 +4778,7 @@ multiclass avx512_fp_scalar<bits<8> opc, string OpcodeStr,X86VectorVTInfo _,
multiclass avx512_fp_scalar_round<bits<8> opc, string OpcodeStr,X86VectorVTInfo _, multiclass avx512_fp_scalar_round<bits<8> opc, string OpcodeStr,X86VectorVTInfo _,
SDNode VecNode, OpndItins itins, bit IsCommutable = 0> { SDNode VecNode, OpndItins itins, bit IsCommutable = 0> {
let ExeDomain = _.ExeDomain in let ExeDomain = _.ExeDomain in
defm rrb : AVX512_maskable_scalar<opc, MRMSrcReg, _, (outs _.RC:$dst), defm rrb_Int : AVX512_maskable_scalar<opc, MRMSrcReg, _, (outs _.RC:$dst),
(ins _.RC:$src1, _.RC:$src2, AVX512RC:$rc), OpcodeStr, (ins _.RC:$src1, _.RC:$src2, AVX512RC:$rc), OpcodeStr,
"$rc, $src2, $src1", "$src1, $src2, $rc", "$rc, $src2, $src1", "$src1, $src2, $rc",
(VecNode (_.VT _.RC:$src1), (_.VT _.RC:$src2), (VecNode (_.VT _.RC:$src1), (_.VT _.RC:$src2),
@ -4818,7 +4818,7 @@ multiclass avx512_fp_scalar_sae<bits<8> opc, string OpcodeStr,X86VectorVTInfo _,
Sched<[itins.Sched.Folded, ReadAfterLd]>; Sched<[itins.Sched.Folded, ReadAfterLd]>;
} }
defm rrb : AVX512_maskable_scalar<opc, MRMSrcReg, _, (outs _.RC:$dst), defm rrb_Int : AVX512_maskable_scalar<opc, MRMSrcReg, _, (outs _.RC:$dst),
(ins _.RC:$src1, _.RC:$src2), OpcodeStr, (ins _.RC:$src1, _.RC:$src2), OpcodeStr,
"{sae}, $src2, $src1", "$src1, $src2, {sae}", "{sae}, $src2, $src1", "$src1, $src2, {sae}",
(SaeNode (_.VT _.RC:$src1), (_.VT _.RC:$src2), (SaeNode (_.VT _.RC:$src1), (_.VT _.RC:$src2),

12
lib/Target/X86/X86InstrInfo.cpp
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@ -10109,9 +10109,9 @@ bool X86InstrInfo::isHighLatencyDef(int opc) const {
case X86::VDIVSDZrr_Int: case X86::VDIVSDZrr_Int:
case X86::VDIVSDZrr_Intk: case X86::VDIVSDZrr_Intk:
case X86::VDIVSDZrr_Intkz: case X86::VDIVSDZrr_Intkz:
case X86::VDIVSDZrrb: case X86::VDIVSDZrrb_Int:
case X86::VDIVSDZrrbk: case X86::VDIVSDZrrb_Intk:
case X86::VDIVSDZrrbkz: case X86::VDIVSDZrrb_Intkz:
case X86::VDIVSSZrm: case X86::VDIVSSZrm:
case X86::VDIVSSZrr: case X86::VDIVSSZrr:
case X86::VDIVSSZrm_Int: case X86::VDIVSSZrm_Int:
@ -10120,9 +10120,9 @@ bool X86InstrInfo::isHighLatencyDef(int opc) const {
case X86::VDIVSSZrr_Int: case X86::VDIVSSZrr_Int:
case X86::VDIVSSZrr_Intk: case X86::VDIVSSZrr_Intk:
case X86::VDIVSSZrr_Intkz: case X86::VDIVSSZrr_Intkz:
case X86::VDIVSSZrrb: case X86::VDIVSSZrrb_Int:
case X86::VDIVSSZrrbk: case X86::VDIVSSZrrb_Intk:
case X86::VDIVSSZrrbkz: case X86::VDIVSSZrrb_Intkz:
case X86::VSQRTPDZ128m: case X86::VSQRTPDZ128m:
case X86::VSQRTPDZ128mb: case X86::VSQRTPDZ128mb:
case X86::VSQRTPDZ128mbk: case X86::VSQRTPDZ128mbk:

24
lib/Target/X86/X86SchedSkylakeServer.td
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@ -2444,9 +2444,9 @@ def: InstRW<[SKXWriteResGroup50], (instregex "VADDPSZ128rr(b?)(k?)(z?)")>;
def: InstRW<[SKXWriteResGroup50], (instregex "VADDPSZ256rr(b?)(k?)(z?)")>; def: InstRW<[SKXWriteResGroup50], (instregex "VADDPSZ256rr(b?)(k?)(z?)")>;
def: InstRW<[SKXWriteResGroup50], (instregex "VADDPSZrr(b?)(k?)(z?)")>; def: InstRW<[SKXWriteResGroup50], (instregex "VADDPSZrr(b?)(k?)(z?)")>;
def: InstRW<[SKXWriteResGroup50], (instregex "VADDPSrr")>; def: InstRW<[SKXWriteResGroup50], (instregex "VADDPSrr")>;
def: InstRW<[SKXWriteResGroup50], (instregex "VADDSDZrr(_Int)?(b?)(k?)(z?)")>; def: InstRW<[SKXWriteResGroup50], (instregex "VADDSDZrr(b?)(_Int)?(k?)(z?)")>;
def: InstRW<[SKXWriteResGroup50], (instregex "VADDSDrr")>; def: InstRW<[SKXWriteResGroup50], (instregex "VADDSDrr")>;
def: InstRW<[SKXWriteResGroup50], (instregex "VADDSSZrr(_Int)?(b?)(k?)(z?)")>; def: InstRW<[SKXWriteResGroup50], (instregex "VADDSSZrr(b?)(_Int)?(k?)(z?)")>;
def: InstRW<[SKXWriteResGroup50], (instregex "VADDSSrr")>; def: InstRW<[SKXWriteResGroup50], (instregex "VADDSSrr")>;
def: InstRW<[SKXWriteResGroup50], (instregex "VADDSUBPDYrr")>; def: InstRW<[SKXWriteResGroup50], (instregex "VADDSUBPDYrr")>;
def: InstRW<[SKXWriteResGroup50], (instregex "VADDSUBPDrr")>; def: InstRW<[SKXWriteResGroup50], (instregex "VADDSUBPDrr")>;
@ -2762,9 +2762,9 @@ def: InstRW<[SKXWriteResGroup50], (instregex "VMAX(C?)PSZ128rr(b?)(k?)(z?)")>;
def: InstRW<[SKXWriteResGroup50], (instregex "VMAX(C?)PSZ256rr(b?)(k?)(z?)")>; def: InstRW<[SKXWriteResGroup50], (instregex "VMAX(C?)PSZ256rr(b?)(k?)(z?)")>;
def: InstRW<[SKXWriteResGroup50], (instregex "VMAX(C?)PSZrr(b?)(k?)(z?)")>; def: InstRW<[SKXWriteResGroup50], (instregex "VMAX(C?)PSZrr(b?)(k?)(z?)")>;
def: InstRW<[SKXWriteResGroup50], (instregex "VMAX(C?)PSrr")>; def: InstRW<[SKXWriteResGroup50], (instregex "VMAX(C?)PSrr")>;
def: InstRW<[SKXWriteResGroup50], (instregex "VMAX(C?)SDZrr(_Int)?(b?)(k?)(z?)")>; def: InstRW<[SKXWriteResGroup50], (instregex "VMAX(C?)SDZrr(b?)(_Int)?(k?)(z?)")>;
def: InstRW<[SKXWriteResGroup50], (instregex "VMAX(C?)SDrr")>; def: InstRW<[SKXWriteResGroup50], (instregex "VMAX(C?)SDrr")>;
def: InstRW<[SKXWriteResGroup50], (instregex "VMAX(C?)SSZrr(_Int)?(b?)(k?)(z?)")>; def: InstRW<[SKXWriteResGroup50], (instregex "VMAX(C?)SSZrr(b?)(_Int)?(k?)(z?)")>;
def: InstRW<[SKXWriteResGroup50], (instregex "VMAX(C?)SSrr")>; def: InstRW<[SKXWriteResGroup50], (instregex "VMAX(C?)SSrr")>;
def: InstRW<[SKXWriteResGroup50], (instregex "VMIN(C?)PDYrr")>; def: InstRW<[SKXWriteResGroup50], (instregex "VMIN(C?)PDYrr")>;
def: InstRW<[SKXWriteResGroup50], (instregex "VMIN(C?)PDZ128rr(b?)(k?)(z?)")>; def: InstRW<[SKXWriteResGroup50], (instregex "VMIN(C?)PDZ128rr(b?)(k?)(z?)")>;
@ -2776,9 +2776,9 @@ def: InstRW<[SKXWriteResGroup50], (instregex "VMIN(C?)PSZ128rr(b?)(k?)(z?)")>;
def: InstRW<[SKXWriteResGroup50], (instregex "VMIN(C?)PSZ256rr(b?)(k?)(z?)")>; def: InstRW<[SKXWriteResGroup50], (instregex "VMIN(C?)PSZ256rr(b?)(k?)(z?)")>;
def: InstRW<[SKXWriteResGroup50], (instregex "VMIN(C?)PSZrr(b?)(k?)(z?)")>; def: InstRW<[SKXWriteResGroup50], (instregex "VMIN(C?)PSZrr(b?)(k?)(z?)")>;
def: InstRW<[SKXWriteResGroup50], (instregex "VMIN(C?)PSrr")>; def: InstRW<[SKXWriteResGroup50], (instregex "VMIN(C?)PSrr")>;
def: InstRW<[SKXWriteResGroup50], (instregex "VMIN(C?)SDZrr(_Int)?(b?)(k?)(z?)")>; def: InstRW<[SKXWriteResGroup50], (instregex "VMIN(C?)SDZrr(b?)(_Int)?(k?)(z?)")>;
def: InstRW<[SKXWriteResGroup50], (instregex "VMIN(C?)SDrr")>; def: InstRW<[SKXWriteResGroup50], (instregex "VMIN(C?)SDrr")>;
def: InstRW<[SKXWriteResGroup50], (instregex "VMIN(C?)SSZrr(_Int)?(b?)(k?)(z?)")>; def: InstRW<[SKXWriteResGroup50], (instregex "VMIN(C?)SSZrr(b?)(_Int)?(k?)(z?)")>;
def: InstRW<[SKXWriteResGroup50], (instregex "VMIN(C?)SSrr")>; def: InstRW<[SKXWriteResGroup50], (instregex "VMIN(C?)SSrr")>;
def: InstRW<[SKXWriteResGroup50], (instregex "VMULPDYrr")>; def: InstRW<[SKXWriteResGroup50], (instregex "VMULPDYrr")>;
def: InstRW<[SKXWriteResGroup50], (instregex "VMULPDZ128rr(b?)(k?)(z?)")>; def: InstRW<[SKXWriteResGroup50], (instregex "VMULPDZ128rr(b?)(k?)(z?)")>;
@ -2790,9 +2790,9 @@ def: InstRW<[SKXWriteResGroup50], (instregex "VMULPSZ128rr(b?)(k?)(z?)")>;
def: InstRW<[SKXWriteResGroup50], (instregex "VMULPSZ256rr(b?)(k?)(z?)")>; def: InstRW<[SKXWriteResGroup50], (instregex "VMULPSZ256rr(b?)(k?)(z?)")>;
def: InstRW<[SKXWriteResGroup50], (instregex "VMULPSZrr(b?)(k?)(z?)")>; def: InstRW<[SKXWriteResGroup50], (instregex "VMULPSZrr(b?)(k?)(z?)")>;
def: InstRW<[SKXWriteResGroup50], (instregex "VMULPSrr")>; def: InstRW<[SKXWriteResGroup50], (instregex "VMULPSrr")>;
def: InstRW<[SKXWriteResGroup50], (instregex "VMULSDZrr(_Int)?(b?)(k?)(z?)")>; def: InstRW<[SKXWriteResGroup50], (instregex "VMULSDZrr(b?)(_Int)?(k?)(z?)")>;
def: InstRW<[SKXWriteResGroup50], (instregex "VMULSDrr")>; def: InstRW<[SKXWriteResGroup50], (instregex "VMULSDrr")>;
def: InstRW<[SKXWriteResGroup50], (instregex "VMULSSZrr(_Int)?(b?)(k?)(z?)")>; def: InstRW<[SKXWriteResGroup50], (instregex "VMULSSZrr(b?)(_Int)?(k?)(z?)")>;
def: InstRW<[SKXWriteResGroup50], (instregex "VMULSSrr")>; def: InstRW<[SKXWriteResGroup50], (instregex "VMULSSrr")>;
def: InstRW<[SKXWriteResGroup50], (instregex "VPHMINPOSUWrr128")>; def: InstRW<[SKXWriteResGroup50], (instregex "VPHMINPOSUWrr128")>;
def: InstRW<[SKXWriteResGroup50], (instregex "VPLZCNTDZ128rr(b?)(k?)(z?)")>; def: InstRW<[SKXWriteResGroup50], (instregex "VPLZCNTDZ128rr(b?)(k?)(z?)")>;
@ -2874,9 +2874,9 @@ def: InstRW<[SKXWriteResGroup50], (instregex "VSUBPSZ128rr(b?)(k?)(z?)")>;
def: InstRW<[SKXWriteResGroup50], (instregex "VSUBPSZ256rr(b?)(k?)(z?)")>; def: InstRW<[SKXWriteResGroup50], (instregex "VSUBPSZ256rr(b?)(k?)(z?)")>;
def: InstRW<[SKXWriteResGroup50], (instregex "VSUBPSZrr(b?)(k?)(z?)")>; def: InstRW<[SKXWriteResGroup50], (instregex "VSUBPSZrr(b?)(k?)(z?)")>;
def: InstRW<[SKXWriteResGroup50], (instregex "VSUBPSrr")>; def: InstRW<[SKXWriteResGroup50], (instregex "VSUBPSrr")>;
def: InstRW<[SKXWriteResGroup50], (instregex "VSUBSDZrr(_Int)?(b?)(k?)(z?)")>; def: InstRW<[SKXWriteResGroup50], (instregex "VSUBSDZrr(b?)(_Int)?(k?)(z?)")>;
def: InstRW<[SKXWriteResGroup50], (instregex "VSUBSDrr")>; def: InstRW<[SKXWriteResGroup50], (instregex "VSUBSDrr")>;
def: InstRW<[SKXWriteResGroup50], (instregex "VSUBSSZrr(_Int)?(b?)(k?)(z?)")>; def: InstRW<[SKXWriteResGroup50], (instregex "VSUBSSZrr(b?)(_Int)?(k?)(z?)")>;
def: InstRW<[SKXWriteResGroup50], (instregex "VSUBSSrr")>; def: InstRW<[SKXWriteResGroup50], (instregex "VSUBSSrr")>;
def SKXWriteResGroup51 : SchedWriteRes<[SKXPort5]> { def SKXWriteResGroup51 : SchedWriteRes<[SKXPort5]> {
@ -5701,7 +5701,7 @@ def: InstRW<[SKXWriteResGroup159], (instregex "VDIVPSYrr")>;
def: InstRW<[SKXWriteResGroup159], (instregex "VDIVPSZ128rr(b?)(k?)(z?)")>; def: InstRW<[SKXWriteResGroup159], (instregex "VDIVPSZ128rr(b?)(k?)(z?)")>;
def: InstRW<[SKXWriteResGroup159], (instregex "VDIVPSZ256rr(b?)(k?)(z?)")>; def: InstRW<[SKXWriteResGroup159], (instregex "VDIVPSZ256rr(b?)(k?)(z?)")>;
def: InstRW<[SKXWriteResGroup159], (instregex "VDIVPSrr")>; def: InstRW<[SKXWriteResGroup159], (instregex "VDIVPSrr")>;
def: InstRW<[SKXWriteResGroup159], (instregex "VDIVSSZrr(_Int)?(b?)(k?)(z?)")>; def: InstRW<[SKXWriteResGroup159], (instregex "VDIVSSZrr(b?)(_Int)?(k?)(z?)")>;
def: InstRW<[SKXWriteResGroup159], (instregex "VDIVSSrr")>; def: InstRW<[SKXWriteResGroup159], (instregex "VDIVSSrr")>;
def SKXWriteResGroup160 : SchedWriteRes<[SKXPort0,SKXPort23]> { def SKXWriteResGroup160 : SchedWriteRes<[SKXPort0,SKXPort23]> {
@ -6205,7 +6205,7 @@ def: InstRW<[SKXWriteResGroup184], (instregex "VDIVPDYrr")>;
def: InstRW<[SKXWriteResGroup184], (instregex "VDIVPDZ128rr(b?)(k?)(z?)")>; def: InstRW<[SKXWriteResGroup184], (instregex "VDIVPDZ128rr(b?)(k?)(z?)")>;
def: InstRW<[SKXWriteResGroup184], (instregex "VDIVPDZ256rr(b?)(k?)(z?)")>; def: InstRW<[SKXWriteResGroup184], (instregex "VDIVPDZ256rr(b?)(k?)(z?)")>;
def: InstRW<[SKXWriteResGroup184], (instregex "VDIVPDrr")>; def: InstRW<[SKXWriteResGroup184], (instregex "VDIVPDrr")>;
def: InstRW<[SKXWriteResGroup184], (instregex "VDIVSDZrr(_Int)?(b?)(k?)(z?)")>; def: InstRW<[SKXWriteResGroup184], (instregex "VDIVSDZrr(b?)(_Int)?(k?)(z?)")>;
def: InstRW<[SKXWriteResGroup184], (instregex "VDIVSDrr")>; def: InstRW<[SKXWriteResGroup184], (instregex "VDIVSDrr")>;
def SKXWriteResGroup185 : SchedWriteRes<[SKXPort0,SKXPort23]> { def SKXWriteResGroup185 : SchedWriteRes<[SKXPort0,SKXPort23]> {