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[Hexagon] Add new InstrItinClass to support timing classes.
This patch doesn't introduce any functionality change. Test cases will be added later when v5 support is added. llvm-svn: 208349
This commit is contained in:
Jyotsna Verma
parent
ccc1932aa6
commit
0b0b5038bf
@ -200,8 +200,6 @@ class Proc<string Name, SchedMachineModel Model,
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list<SubtargetFeature> Features>
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: ProcessorModel<Name, Model, Features>;
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def : Proc<"hexagonv2", HexagonModel, [ArchV2]>;
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def : Proc<"hexagonv3", HexagonModel, [ArchV2, ArchV3]>;
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def : Proc<"hexagonv4", HexagonModelV4, [ArchV2, ArchV3, ArchV4]>;
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def : Proc<"hexagonv5", HexagonModelV4, [ArchV2, ArchV3, ArchV4, ArchV5]>;
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@ -197,8 +197,8 @@ class InstHexagon<dag outs, dag ins, string asmstr, list<dag> pattern,
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// LD Instruction Class in V2/V3/V4.
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// Definition of the instruction class NOT CHANGED.
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class LDInst<dag outs, dag ins, string asmstr, list<dag> pattern = [],
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string cstr = "">
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: InstHexagon<outs, ins, asmstr, pattern, cstr, LD, TypeLD>;
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string cstr = "", InstrItinClass itin = LD_tc_ld_SLOT01>
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: InstHexagon<outs, ins, asmstr, pattern, cstr, itin, TypeLD>;
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let mayLoad = 1 in
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class LDInst2<dag outs, dag ins, string asmstr, list<dag> pattern = [],
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@ -217,16 +217,16 @@ class LDInstPost<dag outs, dag ins, string asmstr, list<dag> pattern = [],
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let mayLoad = 1 in
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class LD0Inst<dag outs, dag ins, string asmstr, list<dag> pattern = [],
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string cstr = "">
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: LDInst<outs, ins, asmstr, pattern, cstr>;
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string cstr = "", InstrItinClass itin=LD_tc_ld_SLOT0>
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: InstHexagon<outs, ins, asmstr, pattern, cstr, itin, TypeLD>;
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// ST Instruction Class in V2/V3 can take SLOT0 only.
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// ST Instruction Class in V4 can take SLOT0 & SLOT1.
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// Definition of the instruction class CHANGED from V2/V3 to V4.
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let mayStore = 1 in
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class STInst<dag outs, dag ins, string asmstr, list<dag> pattern = [],
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string cstr = "">
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: InstHexagon<outs, ins, asmstr, pattern, cstr, ST, TypeST>;
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string cstr = "", InstrItinClass itin = ST_tc_st_SLOT01>
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: InstHexagon<outs, ins, asmstr, pattern, cstr, itin, TypeST>;
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class STInst2<dag outs, dag ins, string asmstr, list<dag> pattern = [],
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string cstr = "">
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@ -234,39 +234,39 @@ class STInst2<dag outs, dag ins, string asmstr, list<dag> pattern = [],
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let mayStore = 1 in
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class ST0Inst<dag outs, dag ins, string asmstr, list<dag> pattern = [],
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string cstr = "">
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: InstHexagon<outs, ins, asmstr, pattern, cstr, ST0, TypeST>;
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string cstr = "", InstrItinClass itin = ST_tc_ld_SLOT0>
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: InstHexagon<outs, ins, asmstr, pattern, cstr, itin, TypeST>;
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// ST Instruction Class in V2/V3 can take SLOT0 only.
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// ST Instruction Class in V4 can take SLOT0 & SLOT1.
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// Definition of the instruction class CHANGED from V2/V3 to V4.
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class STInstPost<dag outs, dag ins, string asmstr, list<dag> pattern = [],
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string cstr = "">
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: STInst<outs, ins, asmstr, pattern, cstr>;
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string cstr = "", InstrItinClass itin = ST_tc_st_SLOT01>
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: STInst<outs, ins, asmstr, pattern, cstr, itin>;
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// SYSTEM Instruction Class in V4 can take SLOT0 only
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// In V2/V3 we used ST for this but in v4 ST can take SLOT0 or SLOT1.
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class SYSInst<dag outs, dag ins, string asmstr, list<dag> pattern = [],
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string cstr = "">
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: InstHexagon<outs, ins, asmstr, pattern, cstr, SYS, TypeSYSTEM>;
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string cstr = "", InstrItinClass itin = ST_tc_3stall_SLOT0>
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: InstHexagon<outs, ins, asmstr, pattern, cstr, itin, TypeSYSTEM>;
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// ALU32 Instruction Class in V2/V3/V4.
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// Definition of the instruction class NOT CHANGED.
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class ALU32Inst<dag outs, dag ins, string asmstr, list<dag> pattern = [],
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string cstr = "">
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: InstHexagon<outs, ins, asmstr, pattern, cstr, ALU32, TypeALU32>;
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string cstr = "", InstrItinClass itin = ALU32_2op_tc_1_SLOT0123>
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: InstHexagon<outs, ins, asmstr, pattern, cstr, itin, TypeALU32>;
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// ALU64 Instruction Class in V2/V3.
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// XTYPE Instruction Class in V4.
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// Definition of the instruction class NOT CHANGED.
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// Name of the Instruction Class changed from ALU64 to XTYPE from V2/V3 to V4.
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class ALU64Inst<dag outs, dag ins, string asmstr, list<dag> pattern = [],
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string cstr = "">
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: InstHexagon<outs, ins, asmstr, pattern, cstr, ALU64, TypeXTYPE>;
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string cstr = "", InstrItinClass itin = ALU64_tc_2_SLOT23>
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: InstHexagon<outs, ins, asmstr, pattern, cstr, itin, TypeXTYPE>;
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class ALU64_acc<dag outs, dag ins, string asmstr, list<dag> pattern = [],
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string cstr = "">
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: ALU64Inst<outs, ins, asmstr, pattern, cstr>;
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string cstr = "", InstrItinClass itin = ALU64_tc_2_SLOT23>
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: ALU64Inst<outs, ins, asmstr, pattern, cstr, itin>;
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// M Instruction Class in V2/V3.
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@ -274,55 +274,55 @@ class ALU64_acc<dag outs, dag ins, string asmstr, list<dag> pattern = [],
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// Definition of the instruction class NOT CHANGED.
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// Name of the Instruction Class changed from M to XTYPE from V2/V3 to V4.
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class MInst<dag outs, dag ins, string asmstr, list<dag> pattern = [],
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string cstr = "">
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: InstHexagon<outs, ins, asmstr, pattern, cstr, M, TypeXTYPE>;
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string cstr = "", InstrItinClass itin = M_tc_3x_SLOT23>
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: InstHexagon<outs, ins, asmstr, pattern, cstr, itin, TypeXTYPE>;
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// M Instruction Class in V2/V3.
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// XTYPE Instruction Class in V4.
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// Definition of the instruction class NOT CHANGED.
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// Name of the Instruction Class changed from M to XTYPE from V2/V3 to V4.
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class MInst_acc<dag outs, dag ins, string asmstr, list<dag> pattern = [],
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string cstr = "">
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: MInst<outs, ins, asmstr, pattern, cstr>;
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string cstr = "", InstrItinClass itin = M_tc_2_SLOT23>
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: MInst<outs, ins, asmstr, pattern, cstr, itin>;
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// S Instruction Class in V2/V3.
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// XTYPE Instruction Class in V4.
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// Definition of the instruction class NOT CHANGED.
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// Name of the Instruction Class changed from S to XTYPE from V2/V3 to V4.
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class SInst<dag outs, dag ins, string asmstr, list<dag> pattern = [],
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string cstr = "">
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: InstHexagon<outs, ins, asmstr, pattern, cstr, S, TypeXTYPE>;
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string cstr = "", InstrItinClass itin = S_2op_tc_1_SLOT23>
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: InstHexagon<outs, ins, asmstr, pattern, cstr, itin, TypeXTYPE>;
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// S Instruction Class in V2/V3.
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// XTYPE Instruction Class in V4.
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// Definition of the instruction class NOT CHANGED.
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// Name of the Instruction Class changed from S to XTYPE from V2/V3 to V4.
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class SInst_acc<dag outs, dag ins, string asmstr, list<dag> pattern = [],
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string cstr = "">
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: SInst<outs, ins, asmstr, pattern, cstr>;
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string cstr = "", InstrItinClass itin = S_3op_tc_1_SLOT23>
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: SInst<outs, ins, asmstr, pattern, cstr, itin>;
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// J Instruction Class in V2/V3/V4.
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// Definition of the instruction class NOT CHANGED.
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class JInst<dag outs, dag ins, string asmstr, list<dag> pattern = [],
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string cstr = "">
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: InstHexagon<outs, ins, asmstr, pattern, cstr, J, TypeJ>;
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string cstr = "", InstrItinClass itin = J_tc_2early_SLOT23>
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: InstHexagon<outs, ins, asmstr, pattern, cstr, itin, TypeJ>;
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// JR Instruction Class in V2/V3/V4.
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// Definition of the instruction class NOT CHANGED.
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class JRInst<dag outs, dag ins, string asmstr, list<dag> pattern = [],
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string cstr = "">
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: InstHexagon<outs, ins, asmstr, pattern, cstr, JR, TypeJR>;
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string cstr = "", InstrItinClass itin = J_tc_2early_SLOT2>
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: InstHexagon<outs, ins, asmstr, pattern, cstr, itin, TypeJR>;
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// CR Instruction Class in V2/V3/V4.
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// Definition of the instruction class NOT CHANGED.
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class CRInst<dag outs, dag ins, string asmstr, list<dag> pattern = [],
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string cstr = "">
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: InstHexagon<outs, ins, asmstr, pattern, cstr, CR, TypeCR>;
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string cstr = "", InstrItinClass itin = CR_tc_2early_SLOT3>
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: InstHexagon<outs, ins, asmstr, pattern, cstr, itin, TypeCR>;
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let isCodeGenOnly = 1, isPseudo = 1 in
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class Endloop<dag outs, dag ins, string asmstr, list<dag> pattern = [],
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string cstr = "">
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: InstHexagon<outs, ins, asmstr, pattern, cstr, ENDLOOP, TypeENDLOOP>;
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string cstr = "", InstrItinClass itin = J_tc_2early_SLOT0123>
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: InstHexagon<outs, ins, asmstr, pattern, cstr, itin, TypeENDLOOP>;
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let isCodeGenOnly = 1, isPseudo = 1 in
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class Pseudo<dag outs, dag ins, string asmstr, list<dag> pattern = [],
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@ -342,32 +342,33 @@ class PseudoM<dag outs, dag ins, string asmstr, list<dag> pattern = [],
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//
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// ALU32 patterns
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//.
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class ALU32_rr<dag outs, dag ins, string asmstr, list<dag> pattern,
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string cstr = "">
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: ALU32Inst<outs, ins, asmstr, pattern, cstr>;
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class ALU32_rr<dag outs, dag ins, string asmstr, list<dag> pattern = [],
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string cstr = "", InstrItinClass itin = ALU32_2op_tc_1_SLOT0123>
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: ALU32Inst<outs, ins, asmstr, pattern, cstr, itin>;
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class ALU32_ir<dag outs, dag ins, string asmstr, list<dag> pattern,
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string cstr = "">
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: ALU32Inst<outs, ins, asmstr, pattern, cstr>;
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class ALU32_ir<dag outs, dag ins, string asmstr, list<dag> pattern = [],
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string cstr = "", InstrItinClass itin = ALU32_2op_tc_1_SLOT0123>
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: ALU32Inst<outs, ins, asmstr, pattern, cstr, itin>;
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class ALU32_ri<dag outs, dag ins, string asmstr, list<dag> pattern,
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string cstr = "">
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: ALU32Inst<outs, ins, asmstr, pattern, cstr>;
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class ALU32_ri<dag outs, dag ins, string asmstr, list<dag> pattern = [],
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string cstr = "", InstrItinClass itin = ALU32_2op_tc_1_SLOT0123>
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: ALU32Inst<outs, ins, asmstr, pattern, cstr, itin>;
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class ALU32_ii<dag outs, dag ins, string asmstr, list<dag> pattern = [],
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string cstr = "", InstrItinClass itin = ALU32_2op_tc_1_SLOT0123>
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: ALU32Inst<outs, ins, asmstr, pattern, cstr, itin>;
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class ALU32_ii<dag outs, dag ins, string asmstr, list<dag> pattern,
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string cstr = "">
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: ALU32Inst<outs, ins, asmstr, pattern, cstr>;
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//
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// ALU64 patterns.
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//
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class ALU64_rr<dag outs, dag ins, string asmstr, list<dag> pattern,
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string cstr = "">
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: ALU64Inst<outs, ins, asmstr, pattern, cstr>;
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class ALU64_rr<dag outs, dag ins, string asmstr, list<dag> pattern = [],
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string cstr = "", InstrItinClass itin = ALU64_tc_1_SLOT23>
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: ALU64Inst<outs, ins, asmstr, pattern, cstr, itin>;
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class ALU64_ri<dag outs, dag ins, string asmstr, list<dag> pattern,
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string cstr = "">
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: ALU64Inst<outs, ins, asmstr, pattern, cstr>;
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class ALU64_ri<dag outs, dag ins, string asmstr, list<dag> pattern = [],
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string cstr = "", InstrItinClass itin = ALU64_tc_1_SLOT23>
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: ALU64Inst<outs, ins, asmstr, pattern, cstr, itin>;
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// Post increment ST Instruction.
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class STInstPI<dag outs, dag ins, string asmstr, list<dag> pattern = [],
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@ -12,7 +12,7 @@
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//===----------------------------------------------------------------------===//
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//----------------------------------------------------------------------------//
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// Hexagon Intruction Flags +
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// Hexagon Instruction Flags
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//
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// *** Must match BaseInfo.h ***
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//----------------------------------------------------------------------------//
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@ -22,30 +22,30 @@ def TypeNV : IType<10>;
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def TypePREFIX : IType<30>;
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//----------------------------------------------------------------------------//
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// Intruction Classes Definitions +
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// Instruction Classes Definitions
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//----------------------------------------------------------------------------//
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//
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// NV type instructions.
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//
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class NVInst<dag outs, dag ins, string asmstr, list<dag> pattern = [],
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string cstr = "">
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: InstHexagon<outs, ins, asmstr, pattern, cstr, NV_V4, TypeNV>;
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string cstr = "", InstrItinClass itin = NCJ_tc_3or4stall_SLOT0>
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: InstHexagon<outs, ins, asmstr, pattern, cstr, itin, TypeNV>;
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class NVInst_V4<dag outs, dag ins, string asmstr, list<dag> pattern = [],
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string cstr = "">
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: NVInst<outs, ins, asmstr, pattern, cstr>;
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string cstr = "", InstrItinClass itin = NCJ_tc_3or4stall_SLOT0>
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: NVInst<outs, ins, asmstr, pattern, cstr, itin>;
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// Definition of Post increment new value store.
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class NVInstPost_V4<dag outs, dag ins, string asmstr, list<dag> pattern = [],
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string cstr = "">
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: NVInst<outs, ins, asmstr, pattern, cstr>;
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string cstr = "", InstrItinClass itin = ST_tc_st_SLOT0>
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: NVInst<outs, ins, asmstr, pattern, cstr, itin>;
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// Post increment ST Instruction.
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let mayStore = 1 in
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class NVInstPI_V4<dag outs, dag ins, string asmstr, list<dag> pattern = [],
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string cstr = "">
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: NVInst<outs, ins, asmstr, pattern, cstr>;
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string cstr = "", InstrItinClass itin = ST_tc_st_SLOT0>
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: NVInst<outs, ins, asmstr, pattern, cstr, itin>;
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// New-value conditional branch.
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class NCJInst<dag outs, dag ins, string asmstr, list<dag> pattern = [],
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@ -54,13 +54,14 @@ class NCJInst<dag outs, dag ins, string asmstr, list<dag> pattern = [],
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let mayLoad = 1, mayStore = 1 in
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class MEMInst<dag outs, dag ins, string asmstr, list<dag> pattern = [],
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string cstr = "">
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: InstHexagon<outs, ins, asmstr, pattern, cstr, MEM_V4, TypeMEMOP>;
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string cstr = "", InstrItinClass itin = V4LDST_tc_st_SLOT0>
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: InstHexagon<outs, ins, asmstr, pattern, cstr, itin, TypeMEMOP>;
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class MEMInst_V4<dag outs, dag ins, string asmstr, list<dag> pattern = [],
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string cstr = "">
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: MEMInst<outs, ins, asmstr, pattern, cstr>;
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string cstr = "", InstrItinClass itin = V4LDST_tc_st_SLOT0>
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: MEMInst<outs, ins, asmstr, pattern, cstr, itin>;
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let isCodeGenOnly = 1 in
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class EXTENDERInst<dag outs, dag ins, string asmstr, list<dag> pattern = []>
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: InstHexagon<outs, ins, asmstr, pattern, "", PREFIX, TypePREFIX>;
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: InstHexagon<outs, ins, asmstr, pattern, "", EXTENDER_tc_1_SLOT0123,
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TypePREFIX>;
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@ -7,57 +7,6 @@
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//
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//===----------------------------------------------------------------------===//
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// Functional Units
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def LSUNIT : FuncUnit; // SLOT0
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def LUNIT : FuncUnit; // SLOT1
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def MUNIT : FuncUnit; // SLOT2
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def SUNIT : FuncUnit; // SLOT3
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def LOOPUNIT : FuncUnit;
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// Itinerary classes
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def ALU32 : InstrItinClass;
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def ALU64 : InstrItinClass;
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def CR : InstrItinClass;
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def J : InstrItinClass;
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def JR : InstrItinClass;
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def LD : InstrItinClass;
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def LD0 : InstrItinClass;
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def M : InstrItinClass;
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def ST : InstrItinClass;
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def ST0 : InstrItinClass;
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def S : InstrItinClass;
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def SYS : InstrItinClass;
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def ENDLOOP : InstrItinClass;
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def PSEUDO : InstrItinClass;
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def PSEUDOM : InstrItinClass;
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def HexagonItineraries :
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ProcessorItineraries<[LSUNIT, LUNIT, MUNIT, SUNIT, LOOPUNIT], [], [
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InstrItinData<ALU32 , [InstrStage<1, [LUNIT, LSUNIT, MUNIT, SUNIT]>]>,
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InstrItinData<ALU64 , [InstrStage<1, [MUNIT, SUNIT]>]>,
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InstrItinData<CR , [InstrStage<1, [SUNIT]>]>,
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InstrItinData<J , [InstrStage<1, [SUNIT, MUNIT]>]>,
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InstrItinData<JR , [InstrStage<1, [MUNIT]>]>,
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InstrItinData<LD , [InstrStage<1, [LUNIT, LSUNIT]>]>,
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InstrItinData<LD0 , [InstrStage<1, [LSUNIT]>]>,
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InstrItinData<M , [InstrStage<1, [MUNIT, SUNIT]>]>,
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InstrItinData<ST , [InstrStage<1, [LSUNIT]>]>,
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InstrItinData<ST0 , [InstrStage<1, [LSUNIT]>]>,
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InstrItinData<S , [InstrStage<1, [SUNIT, MUNIT]>]>,
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InstrItinData<SYS , [InstrStage<1, [LSUNIT]>]>,
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InstrItinData<ENDLOOP, [InstrStage<1, [LOOPUNIT]>]>,
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InstrItinData<PSEUDO , [InstrStage<1, [LUNIT, LSUNIT, MUNIT, SUNIT]>]>,
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InstrItinData<PSEUDOM, [InstrStage<1, [MUNIT, SUNIT], 0>,
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InstrStage<1, [MUNIT, SUNIT]>]>
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]>;
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def HexagonModel : SchedMachineModel {
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// Max issue per cycle == bundle width.
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let IssueWidth = 4;
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let Itineraries = HexagonItineraries;
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let LoadLatency = 1;
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}
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//===----------------------------------------------------------------------===//
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// V4 Machine Info +
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//===----------------------------------------------------------------------===//
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@ -34,29 +34,158 @@ def SLOT3 : FuncUnit;
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def SLOT_ENDLOOP: FuncUnit;
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// Itinerary classes.
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def NV_V4 : InstrItinClass;
|
||||
def MEM_V4 : InstrItinClass;
|
||||
def PSEUDO : InstrItinClass;
|
||||
def PSEUDOM : InstrItinClass;
|
||||
// ALU64/M/S Instruction classes of V2 are collectively knownn as XTYPE in V4.
|
||||
def DUPLEX : InstrItinClass;
|
||||
def PREFIX : InstrItinClass;
|
||||
def COMPOUND : InstrItinClass;
|
||||
|
||||
def ALU32_2op_tc_1_SLOT0123 : InstrItinClass;
|
||||
def ALU32_2op_tc_2early_SLOT0123 : InstrItinClass;
|
||||
def ALU32_3op_tc_2early_SLOT0123 : InstrItinClass;
|
||||
def ALU32_3op_tc_1_SLOT0123 : InstrItinClass;
|
||||
def ALU32_3op_tc_2_SLOT0123 : InstrItinClass;
|
||||
def ALU32_ADDI_tc_1_SLOT0123 : InstrItinClass;
|
||||
def ALU64_tc_1_SLOT23 : InstrItinClass;
|
||||
def ALU64_tc_1or2_SLOT23 : InstrItinClass;
|
||||
def ALU64_tc_2_SLOT23 : InstrItinClass;
|
||||
def ALU64_tc_2early_SLOT23 : InstrItinClass;
|
||||
def ALU64_tc_3x_SLOT23 : InstrItinClass;
|
||||
def CR_tc_2_SLOT3 : InstrItinClass;
|
||||
def CR_tc_2early_SLOT23 : InstrItinClass;
|
||||
def CR_tc_2early_SLOT3 : InstrItinClass;
|
||||
def CR_tc_3x_SLOT23 : InstrItinClass;
|
||||
def CR_tc_3x_SLOT3 : InstrItinClass;
|
||||
def J_tc_2early_SLOT23 : InstrItinClass;
|
||||
def J_tc_2early_SLOT2 : InstrItinClass;
|
||||
def LD_tc_ld_SLOT01 : InstrItinClass;
|
||||
def LD_tc_ld_SLOT0 : InstrItinClass;
|
||||
def LD_tc_3or4stall_SLOT0 : InstrItinClass;
|
||||
def M_tc_1_SLOT23 : InstrItinClass;
|
||||
def M_tc_1or2_SLOT23 : InstrItinClass;
|
||||
def M_tc_2_SLOT23 : InstrItinClass;
|
||||
def M_tc_3_SLOT23 : InstrItinClass;
|
||||
def M_tc_3x_SLOT23 : InstrItinClass;
|
||||
def M_tc_3or4x_SLOT23 : InstrItinClass;
|
||||
def ST_tc_st_SLOT01 : InstrItinClass;
|
||||
def ST_tc_st_SLOT0 : InstrItinClass;
|
||||
def ST_tc_ld_SLOT0 : InstrItinClass;
|
||||
def ST_tc_3stall_SLOT0 : InstrItinClass;
|
||||
def S_2op_tc_1_SLOT23 : InstrItinClass;
|
||||
def S_2op_tc_2_SLOT23 : InstrItinClass;
|
||||
def S_2op_tc_2early_SLOT23 : InstrItinClass;
|
||||
def S_2op_tc_3or4x_SLOT23 : InstrItinClass;
|
||||
def S_3op_tc_1_SLOT23 : InstrItinClass;
|
||||
def S_3op_tc_1or2_SLOT23 : InstrItinClass;
|
||||
def S_3op_tc_2_SLOT23 : InstrItinClass;
|
||||
def S_3op_tc_2early_SLOT23 : InstrItinClass;
|
||||
def S_3op_tc_3_SLOT23 : InstrItinClass;
|
||||
def S_3op_tc_3x_SLOT23 : InstrItinClass;
|
||||
def NCJ_tc_3or4stall_SLOT0 : InstrItinClass;
|
||||
def V2LDST_tc_ld_SLOT01 : InstrItinClass;
|
||||
def V2LDST_tc_st_SLOT0 : InstrItinClass;
|
||||
def V2LDST_tc_st_SLOT01 : InstrItinClass;
|
||||
def V4LDST_tc_ld_SLOT01 : InstrItinClass;
|
||||
def V4LDST_tc_st_SLOT0 : InstrItinClass;
|
||||
def V4LDST_tc_st_SLOT01 : InstrItinClass;
|
||||
def J_tc_2early_SLOT0123 : InstrItinClass;
|
||||
def EXTENDER_tc_1_SLOT0123 : InstrItinClass;
|
||||
|
||||
|
||||
def HexagonItinerariesV4 :
|
||||
ProcessorItineraries<[SLOT0, SLOT1, SLOT2, SLOT3, SLOT_ENDLOOP], [], [
|
||||
InstrItinData<ALU32 , [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>]>,
|
||||
InstrItinData<ALU64 , [InstrStage<1, [SLOT2, SLOT3]>]>,
|
||||
InstrItinData<CR , [InstrStage<1, [SLOT3]>]>,
|
||||
InstrItinData<J , [InstrStage<1, [SLOT2, SLOT3]>]>,
|
||||
InstrItinData<JR , [InstrStage<1, [SLOT2]>]>,
|
||||
InstrItinData<LD , [InstrStage<1, [SLOT0, SLOT1]>]>,
|
||||
InstrItinData<LD0 , [InstrStage<1, [SLOT0]>]>,
|
||||
InstrItinData<M , [InstrStage<1, [SLOT2, SLOT3]>]>,
|
||||
InstrItinData<ST , [InstrStage<1, [SLOT0, SLOT1]>]>,
|
||||
InstrItinData<ST0 , [InstrStage<1, [SLOT0]>]>,
|
||||
InstrItinData<S , [InstrStage<1, [SLOT2, SLOT3]>]>,
|
||||
InstrItinData<SYS , [InstrStage<1, [SLOT0]>]>,
|
||||
InstrItinData<NV_V4 , [InstrStage<1, [SLOT0]>]>,
|
||||
InstrItinData<MEM_V4 , [InstrStage<1, [SLOT0]>]>,
|
||||
InstrItinData<ENDLOOP, [InstrStage<1, [SLOT_ENDLOOP]>]>,
|
||||
InstrItinData<PREFIX , [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>]>,
|
||||
// ALU32
|
||||
InstrItinData<ALU32_2op_tc_1_SLOT0123 ,
|
||||
[InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>]>,
|
||||
InstrItinData<ALU32_2op_tc_2early_SLOT0123,
|
||||
[InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>]>,
|
||||
InstrItinData<ALU32_3op_tc_1_SLOT0123 ,
|
||||
[InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>]>,
|
||||
InstrItinData<ALU32_3op_tc_2early_SLOT0123,
|
||||
[InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>]>,
|
||||
InstrItinData<ALU32_3op_tc_2_SLOT0123 ,
|
||||
[InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>]>,
|
||||
InstrItinData<ALU32_ADDI_tc_1_SLOT0123 ,
|
||||
[InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>]>,
|
||||
|
||||
// ALU64
|
||||
InstrItinData<ALU64_tc_1_SLOT23 , [InstrStage<1, [SLOT2, SLOT3]>]>,
|
||||
InstrItinData<ALU64_tc_1or2_SLOT23 , [InstrStage<1, [SLOT2, SLOT3]>]>,
|
||||
InstrItinData<ALU64_tc_2_SLOT23 , [InstrStage<1, [SLOT2, SLOT3]>]>,
|
||||
InstrItinData<ALU64_tc_2early_SLOT23 , [InstrStage<1, [SLOT2, SLOT3]>]>,
|
||||
InstrItinData<ALU64_tc_3x_SLOT23 , [InstrStage<1, [SLOT2, SLOT3]>]>,
|
||||
|
||||
// CR -> System
|
||||
InstrItinData<CR_tc_2_SLOT3 , [InstrStage<1, [SLOT3]>]>,
|
||||
InstrItinData<CR_tc_2early_SLOT3 , [InstrStage<1, [SLOT3]>]>,
|
||||
InstrItinData<CR_tc_3x_SLOT3 , [InstrStage<1, [SLOT3]>]>,
|
||||
|
||||
// Jump (conditional/unconditional/return etc)
|
||||
// CR
|
||||
InstrItinData<CR_tc_2early_SLOT23 , [InstrStage<1, [SLOT2, SLOT3]>]>,
|
||||
InstrItinData<CR_tc_3x_SLOT23 , [InstrStage<1, [SLOT2, SLOT3]>]>,
|
||||
// J
|
||||
InstrItinData<J_tc_2early_SLOT23 , [InstrStage<1, [SLOT2, SLOT3]>]>,
|
||||
// JR
|
||||
InstrItinData<J_tc_2early_SLOT2 , [InstrStage<1, [SLOT2]>]>,
|
||||
|
||||
//Load
|
||||
InstrItinData<LD_tc_ld_SLOT01 , [InstrStage<1, [SLOT0, SLOT1]>]>,
|
||||
InstrItinData<LD_tc_ld_SLOT0 , [InstrStage<1, [SLOT0]>]>,
|
||||
InstrItinData<LD_tc_3or4stall_SLOT0 , [InstrStage<1, [SLOT0]>]>,
|
||||
|
||||
// M
|
||||
InstrItinData<M_tc_1_SLOT23 , [InstrStage<1, [SLOT2, SLOT3]>]>,
|
||||
InstrItinData<M_tc_1or2_SLOT23 , [InstrStage<1, [SLOT2, SLOT3]>]>,
|
||||
InstrItinData<M_tc_2_SLOT23 , [InstrStage<1, [SLOT2, SLOT3]>]>,
|
||||
InstrItinData<M_tc_3_SLOT23 , [InstrStage<1, [SLOT2, SLOT3]>]>,
|
||||
InstrItinData<M_tc_3x_SLOT23 , [InstrStage<1, [SLOT2, SLOT3]>]>,
|
||||
InstrItinData<M_tc_3or4x_SLOT23 , [InstrStage<1, [SLOT2, SLOT3]>]>,
|
||||
|
||||
// Store
|
||||
// ST
|
||||
InstrItinData<ST_tc_st_SLOT01 , [InstrStage<1, [SLOT0, SLOT1]>]>,
|
||||
// ST0
|
||||
InstrItinData<ST_tc_st_SLOT0 , [InstrStage<1, [SLOT0]>]>,
|
||||
InstrItinData<ST_tc_ld_SLOT0 , [InstrStage<1, [SLOT0]>]>,
|
||||
|
||||
// S
|
||||
InstrItinData<S_2op_tc_1_SLOT23 , [InstrStage<1, [SLOT2, SLOT3]>]>,
|
||||
InstrItinData<S_2op_tc_2_SLOT23 , [InstrStage<1, [SLOT2, SLOT3]>]>,
|
||||
InstrItinData<S_2op_tc_2early_SLOT23 , [InstrStage<1, [SLOT2, SLOT3]>]>,
|
||||
InstrItinData<S_2op_tc_3or4x_SLOT23 , [InstrStage<1, [SLOT2, SLOT3]>]>,
|
||||
InstrItinData<S_3op_tc_1_SLOT23 , [InstrStage<1, [SLOT2, SLOT3]>]>,
|
||||
InstrItinData<S_3op_tc_1or2_SLOT23 , [InstrStage<1, [SLOT2, SLOT3]>]>,
|
||||
InstrItinData<S_3op_tc_2early_SLOT23 , [InstrStage<1, [SLOT2, SLOT3]>]>,
|
||||
InstrItinData<S_3op_tc_2_SLOT23 , [InstrStage<1, [SLOT2, SLOT3]>]>,
|
||||
InstrItinData<S_3op_tc_3_SLOT23 , [InstrStage<1, [SLOT2, SLOT3]>]>,
|
||||
InstrItinData<S_3op_tc_3x_SLOT23 , [InstrStage<1, [SLOT2, SLOT3]>]>,
|
||||
|
||||
// SYS
|
||||
InstrItinData<ST_tc_3stall_SLOT0 , [InstrStage<1, [SLOT0]>]>,
|
||||
|
||||
// New Value Compare Jump
|
||||
InstrItinData<NCJ_tc_3or4stall_SLOT0 , [InstrStage<1, [SLOT0]>]>,
|
||||
|
||||
// Mem ops - MEM_V4
|
||||
InstrItinData<V2LDST_tc_st_SLOT0 , [InstrStage<1, [SLOT0]>]>,
|
||||
InstrItinData<V2LDST_tc_ld_SLOT01 , [InstrStage<1, [SLOT0, SLOT1]>]>,
|
||||
InstrItinData<V2LDST_tc_st_SLOT01 , [InstrStage<1, [SLOT0, SLOT1]>]>,
|
||||
InstrItinData<V4LDST_tc_st_SLOT0 , [InstrStage<1, [SLOT0]>]>,
|
||||
InstrItinData<V4LDST_tc_ld_SLOT01 , [InstrStage<1, [SLOT0, SLOT1]>]>,
|
||||
InstrItinData<V4LDST_tc_st_SLOT01 , [InstrStage<1, [SLOT0, SLOT1]>]>,
|
||||
|
||||
InstrItinData<DUPLEX , [InstrStage<1, [SLOT0]>]>,
|
||||
|
||||
// ENDLOOP
|
||||
InstrItinData<J_tc_2early_SLOT0123 , [InstrStage<1, [SLOT_ENDLOOP]>]>,
|
||||
|
||||
// Extender/PREFIX
|
||||
InstrItinData<EXTENDER_tc_1_SLOT0123,
|
||||
[InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>]>,
|
||||
|
||||
InstrItinData<COMPOUND , [InstrStage<1, [SLOT2, SLOT3]>]>,
|
||||
InstrItinData<PSEUDO , [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>]>,
|
||||
InstrItinData<PSEUDOM, [InstrStage<1, [SLOT2, SLOT3], 0>,
|
||||
InstrStage<1, [SLOT2, SLOT3]>]>
|
||||
|
||||
Loading…
x
Reference in New Issue
Block a user