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Add binary emission stuff for VLDM/VSTM. This reuses the
"getRegisterListOpValue" logic. If the registers are double or single precision, the value returned is suitable for VLDM/VSTM. llvm-svn: 119435
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@ -1125,7 +1125,7 @@ class T1DataProcessing<bits<4> opcode> : Encoding16 {
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// A6.2.3 Special data instructions and branch and exchange encoding.
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// A6.2.3 Special data instructions and branch and exchange encoding.
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class T1Special<bits<4> opcode> : Encoding16 {
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class T1Special<bits<4> opcode> : Encoding16 {
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let Inst{15-10} = 0b010001;
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let Inst{15-10} = 0b010001;
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let Inst{9-6} = opcode;
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let Inst{9-6} = opcode;
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}
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}
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// A6.2.4 Load/store single data item encoding.
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// A6.2.4 Load/store single data item encoding.
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@ -1321,6 +1321,8 @@ class VFPXI<dag oops, dag iops, AddrMode am, SizeFlagVal sz,
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IndexMode im, Format f, InstrItinClass itin,
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IndexMode im, Format f, InstrItinClass itin,
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string asm, string cstr, list<dag> pattern>
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string asm, string cstr, list<dag> pattern>
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: InstARM<am, sz, im, f, VFPDomain, cstr, itin> {
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: InstARM<am, sz, im, f, VFPDomain, cstr, itin> {
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bits<4> p;
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let Inst{31-28} = p;
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let OutOperandList = oops;
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let OutOperandList = oops;
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let InOperandList = iops;
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let InOperandList = iops;
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let AsmString = asm;
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let AsmString = asm;
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@ -1399,6 +1401,16 @@ class AXDI4<dag oops, dag iops, IndexMode im, InstrItinClass itin,
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string asm, string cstr, list<dag> pattern>
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string asm, string cstr, list<dag> pattern>
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: VFPXI<oops, iops, AddrMode4, Size4Bytes, im,
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: VFPXI<oops, iops, AddrMode4, Size4Bytes, im,
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VFPLdStMulFrm, itin, asm, cstr, pattern> {
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VFPLdStMulFrm, itin, asm, cstr, pattern> {
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// Instruction operands.
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bits<4> Rn;
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bits<13> regs;
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// Encode instruction operands.
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let Inst{19-16} = Rn;
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let Inst{22} = regs{12};
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let Inst{15-12} = regs{11-8};
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let Inst{7-0} = regs{7-0};
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// TODO: Mark the instructions with the appropriate subtarget info.
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// TODO: Mark the instructions with the appropriate subtarget info.
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let Inst{27-25} = 0b110;
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let Inst{27-25} = 0b110;
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let Inst{11-9} = 0b101;
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let Inst{11-9} = 0b101;
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@ -1412,6 +1424,16 @@ class AXSI4<dag oops, dag iops, IndexMode im, InstrItinClass itin,
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string asm, string cstr, list<dag> pattern>
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string asm, string cstr, list<dag> pattern>
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: VFPXI<oops, iops, AddrMode4, Size4Bytes, im,
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: VFPXI<oops, iops, AddrMode4, Size4Bytes, im,
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VFPLdStMulFrm, itin, asm, cstr, pattern> {
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VFPLdStMulFrm, itin, asm, cstr, pattern> {
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// Instruction operands.
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bits<4> Rn;
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bits<13> regs;
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// Encode instruction operands.
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let Inst{19-16} = Rn;
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let Inst{22} = regs{8};
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let Inst{15-12} = regs{12-9};
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let Inst{7-0} = regs{7-0};
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// TODO: Mark the instructions with the appropriate subtarget info.
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// TODO: Mark the instructions with the appropriate subtarget info.
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let Inst{27-25} = 0b110;
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let Inst{27-25} = 0b110;
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let Inst{11-9} = 0b101;
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let Inst{11-9} = 0b101;
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@ -661,13 +661,34 @@ getBitfieldInvertedMaskOpValue(const MCInst &MI, unsigned Op,
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unsigned ARMMCCodeEmitter::
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unsigned ARMMCCodeEmitter::
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getRegisterListOpValue(const MCInst &MI, unsigned Op,
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getRegisterListOpValue(const MCInst &MI, unsigned Op,
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SmallVectorImpl<MCFixup> &Fixups) const {
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SmallVectorImpl<MCFixup> &Fixups) const {
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// Convert a list of GPRs into a bitfield (R0 -> bit 0). For each
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// VLDM/VSTM:
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// register in the list, set the corresponding bit.
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// {12-8} = Vd
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// {7-0} = Number of registers
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//
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// LDM/STM:
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// {15-0} = Bitfield of GPRs.
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unsigned Reg = MI.getOperand(Op).getReg();
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bool SPRRegs = ARM::SPRRegClass.contains(Reg);
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bool DPRRegs = ARM::DPRRegClass.contains(Reg);
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unsigned Binary = 0;
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unsigned Binary = 0;
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for (unsigned i = Op, e = MI.getNumOperands(); i < e; ++i) {
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unsigned regno = getARMRegisterNumbering(MI.getOperand(i).getReg());
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if (SPRRegs || DPRRegs) {
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Binary |= 1 << regno;
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// VLDM/VSTM
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unsigned RegNo = getARMRegisterNumbering(Reg);
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unsigned NumRegs = (MI.getNumOperands() - Op) & 0xff;
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Binary |= (RegNo & 0x1f) << 8;
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if (SPRRegs)
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Binary |= NumRegs;
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else
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Binary |= NumRegs * 2;
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} else {
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for (unsigned I = Op, E = MI.getNumOperands(); I < E; ++I) {
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unsigned RegNo = getARMRegisterNumbering(MI.getOperand(I).getReg());
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Binary |= 1 << RegNo;
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}
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}
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}
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return Binary;
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return Binary;
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}
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}
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