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[PowerPC] fix trivial typos in comment, NFC

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llvm-svn: 357981
This commit is contained in:
Hiroshi Inoue 2019-04-09 08:40:02 +00:00
parent 5628f415b9
commit 0b83d956b3
3 changed files with 6 additions and 6 deletions
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2
lib/Target/PowerPC/PPCFrameLowering.cpp
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@ -756,7 +756,7 @@ bool PPCFrameLowering::stackUpdateCanBeMoved(MachineFunction &MF) const {
if (FI->hasFastCall() || FI->usesPICBase())
return false;
// Finally we can move the stack update if we do not require regiser
// Finally we can move the stack update if we do not require register
// scavenging. Register scavenging can introduce more spills and so
// may make the frame size larger than we have computed.
return !RegInfo->requiresFrameIndexScavenging(MF);

6
lib/Target/PowerPC/PPCISelDAGToDAG.cpp
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@ -2372,7 +2372,7 @@ public:
// Here we try to match complex bit permutations into a set of
// rotate-and-shift/shift/and/or instructions, using a set of heuristics
// known to produce optimial code for common cases (like i32 byte swapping).
// known to produce optimal code for common cases (like i32 byte swapping).
SDNode *Select(SDNode *N) {
Memoizer.clear();
auto Result =
@ -4213,12 +4213,12 @@ static bool mayUseP9Setb(SDNode *N, const ISD::CondCode &CC, SelectionDAG *DAG,
// Without this setb optimization, the outer SELECT_CC will be manually
// selected to SELECT_CC_I4/SELECT_CC_I8 Pseudo, then expand-isel-pseudos pass
// transforms pseduo instruction to isel instruction. When there are more than
// transforms pseudo instruction to isel instruction. When there are more than
// one use for result like zext/sext, with current optimization we only see
// isel is replaced by setb but can't see any significant gain. Since
// setb has longer latency than original isel, we should avoid this. Another
// point is that setb requires comparison always kept, it can break the
// oppotunity to get the comparison away if we have in future.
// opportunity to get the comparison away if we have in future.
if (!SetOrSelCC.hasOneUse() || (!InnerIsSel && !FalseRes.hasOneUse()))
return false;

4
lib/Target/PowerPC/PPCISelLowering.h
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@ -40,7 +40,7 @@ namespace llvm {
// the enum. The order of elements in this enum matters!
// Values that are added after this entry:
// STBRX = ISD::FIRST_TARGET_MEMORY_OPCODE
// are considerd memory opcodes and are treated differently than entries
// are considered memory opcodes and are treated differently than entries
// that come before it. For example, ADD or MUL should be placed before
// the ISD::FIRST_TARGET_MEMORY_OPCODE while a LOAD or STORE should come
// after it.
@ -192,7 +192,7 @@ namespace llvm {
/// Direct move from a GPR to a VSX register (zero)
MTVSRZ,
/// Direct move of 2 consective GPR to a VSX register.
/// Direct move of 2 consecutive GPR to a VSX register.
BUILD_FP128,
/// Extract a subvector from signed integer vector and convert to FP.