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GlobalISel: map 128-bit values to an FPR by default.

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Eventually we may want to allow a pair of GPRs but absolutely nothing in the
entire world is ready for that yet.

llvm-svn: 309404
This commit is contained in:
Tim Northover 2017-07-28 17:11:01 +00:00
parent 45b80b71bd
commit 0b9cfde62b
3 changed files with 23 additions and 19 deletions
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3
lib/Target/AArch64/AArch64RegisterBankInfo.cpp
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@ -488,7 +488,8 @@ AArch64RegisterBankInfo::getInstrMapping(const MachineInstr &MI) const {
// As a top-level guess, vectors go in FPRs, scalars and pointers in GPRs.
// For floating-point instructions, scalars go in FPRs.
if (Ty.isVector() || isPreISelGenericFloatingPointOpcode(Opc))
if (Ty.isVector() || isPreISelGenericFloatingPointOpcode(Opc) ||
Ty.getSizeInBits() > 64)
OpRegBankIdx[Idx] = PMI_FirstFPR;
else
OpRegBankIdx[Idx] = PMI_FirstGPR;

18
test/CodeGen/AArch64/GlobalISel/arm64-fallback.ll
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@ -79,24 +79,6 @@ define void @odd_vector(<7 x i32>* %addr) {
ret void
}
; RegBankSelect crashed when given invalid mappings, and AArch64's
; implementation produce valid-but-nonsense mappings for G_SEQUENCE.
; FALLBACK-WITH-REPORT-ERR: remark: <unknown>:0:0: unable to map instruction
; FALLBACK-WITH-REPORT-ERR: warning: Instruction selection used fallback path for sequence_mapping
; FALLBACK-WITH-REPORT-OUT-LABEL: sequence_mapping:
define void @sequence_mapping([2 x i64] %in) {
ret void
}
; Legalizer was asserting when it enountered an unexpected default action.
; FALLBACK-WITH-REPORT-ERR: remark: <unknown>:0:0: unable to map instruction
; FALLBACK-WITH-REPORT-ERR: warning: Instruction selection used fallback path for legal_default
; FALLBACK-WITH-REPORT-LABEL: legal_default:
define void @legal_default([8 x i8] %in) {
insertvalue { [4 x i8], [8 x i8], [4 x i8] } undef, [8 x i8] %in, 1
ret void
}
; AArch64 was asserting instead of returning an invalid mapping for unknown
; sizes.
; FALLBACK-WITH-REPORT-ERR: remark: <unknown>:0:0: unable to translate instruction: ret: ' ret i128 undef' (in function: sequence_sizes)

21
test/CodeGen/AArch64/reg-bank-128bit.mir Normal file
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@ -0,0 +1,21 @@
# RUN: llc -mtriple=aarch64 -global-isel -run-pass=regbankselect -o - %s | FileCheck %s
---
name: test_large_merge
legalized: true
registers:
body: |
bb.0.entry:
liveins: %x0, %x1, %x2
; CHECK-LABEL: name: test_large_merge
; CHECK: registers:
; CHECK: - { id: 0, class: gpr
; CHECK: - { id: 1, class: gpr
; CHECK: - { id: 2, class: gpr
; CHECK: - { id: 3, class: fpr
%0:_(s64) = COPY %x0
%1:_(s64) = COPY %x1
%2:_(p0) = COPY %x2
%3:_(s128) = G_MERGE_VALUES %0, %1
%d0 = COPY %3
...